From 1bc5aee63eb72b341f506ad058502cd0361f0d10 Mon Sep 17 00:00:00 2001 From: Ben Cheng Date: Tue, 25 Mar 2014 22:37:19 -0700 Subject: Initial checkin of GCC 4.9.0 from trunk (r208799). Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba --- gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c (limited to 'gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c') diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c new file mode 100644 index 000000000..9534974de --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/umips-lwp-6.c @@ -0,0 +1,17 @@ +/* { dg-options "-mgp32 -fpeephole2 -mtune=m14k (-mmicromips)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +void MICROMIPS +foo (int *r4) +{ + int r5 = r4[512]; + int r6 = r4[513]; + r4[2] = r6 * r6; + { + register int r5asm asm ("$5") = r5; + register int r6asm asm ("$6") = r6; + asm ("#foo" : "=m" (r4[3]) : "d" (r5asm), "d" (r6asm)); + } +} + +/* { dg-final { scan-assembler-not "\tlwp" } }*/ -- cgit v1.2.3