From 1bc5aee63eb72b341f506ad058502cd0361f0d10 Mon Sep 17 00:00:00 2001
From: Ben Cheng <bccheng@google.com>
Date: Tue, 25 Mar 2014 22:37:19 -0700
Subject: Initial checkin of GCC 4.9.0 from trunk (r208799).

Change-Id: I48a3c08bb98542aa215912a75f03c0890e497dba
---
 .../gcc.target/mips/r10k-cache-barrier-1.c         | 45 ++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c

(limited to 'gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c')

diff --git a/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c
new file mode 100644
index 000000000..b5ffd0aeb
--- /dev/null
+++ b/gcc-4.9/gcc/testsuite/gcc.target/mips/r10k-cache-barrier-1.c
@@ -0,0 +1,45 @@
+/* { dg-options "-mabi=64 -mr10k-cache-barrier=store" } */
+
+/* Test that stores to uncached addresses do not get unnecessary
+   cache barriers.  */
+
+#define TEST(ADDR)					\
+  NOMIPS16 void						\
+  test_##ADDR (int n)					\
+  {							\
+    while (n--)						\
+      {							\
+	*(volatile char *) (0x##ADDR##UL) = 1;		\
+	*(volatile short *) (0x##ADDR##UL + 2) = 2;	\
+	*(volatile int *) (0x##ADDR##UL + 4) = 0;	\
+      }							\
+  }
+
+TEST (9000000000000000)
+TEST (900000fffffffff8)
+
+TEST (9200000000000000)
+TEST (920000fffffffff8)
+
+TEST (9400000000000000)
+TEST (940000fffffffff8)
+
+TEST (9600000000000000)
+TEST (960000fffffffff8)
+
+TEST (b800000000000000)
+TEST (b80000fffffffff8)
+
+TEST (ba00000000000000)
+TEST (ba0000fffffffff8)
+
+TEST (bc00000000000000)
+TEST (bc0000fffffffff8)
+
+TEST (be00000000000000)
+TEST (be0000fffffffff8)
+
+TEST (ffffffffa0000000)
+TEST (ffffffffbffffff8)
+
+/* { dg-final { scan-assembler-not "\tcache\t" } } */
-- 
cgit v1.2.3