From 38a8aecfb882072900434499696b5c32a2274515 Mon Sep 17 00:00:00 2001 From: Rong Xu Date: Mon, 21 Jul 2014 16:47:22 -0700 Subject: [4.9] Switch gcc-4.9 to use google/gcc-4_9 branch. This source drop uses svn version r212828 of google/gcc-4.9 branch. We also cherry-picked r213062, r213063 and r213064 to fix windows build issues. All gcc-4.9 patches before July 3rd are ported to google/gcc-4.9. The following prior commits has not been merged to google branch yet. (They are included in this commit). e7af147f979e657fe2df00808e5b4319b0e088c6, baf87df3cb2683649ba7e9872362a7e721117c23, and c231900e5dcc14d8296bd9f62b45997a49d4d5e7. Change-Id: I4bea3ea470387ff751c2be4cb0d4a12059b9299b --- .../gcc.target/aarch64/aapcs64/type-def.h | 7 +++ .../gcc.target/aarch64/aapcs64/va_arg-13.c | 59 ++++++++++++++++++++++ .../gcc.target/aarch64/aapcs64/va_arg-14.c | 35 +++++++++++++ .../gcc.target/aarch64/aapcs64/va_arg-15.c | 39 ++++++++++++++ gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c | 19 +++++++ .../gcc.target/aarch64/scalar_intrinsics.c | 26 +++++----- .../gcc.target/aarch64/vector_intrinsics.c | 14 ++--- .../gcc.target/aarch64/vqdmlal_high_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_high_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_high_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_high_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlal_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlalh_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlals_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_high_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_high_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_high_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_high_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsl_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmlslh_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmlsls_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmulh_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmulh_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmulhh_lane_s16.c | 36 +++++++++++++ .../gcc.target/aarch64/vqdmulhq_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmulhq_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmulhs_lane_s32.c | 34 +++++++++++++ .../gcc.target/aarch64/vqdmull_high_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_high_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_high_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_high_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmull_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqdmullh_lane_s16.c | 15 ++++++ .../gcc.target/aarch64/vqdmulls_lane_s32.c | 15 ++++++ .../gcc.target/aarch64/vqrdmulh_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqrdmulh_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqrdmulhh_lane_s16.c | 35 +++++++++++++ .../gcc.target/aarch64/vqrdmulhq_laneq_s16.c | 15 ++++++ .../gcc.target/aarch64/vqrdmulhq_laneq_s32.c | 15 ++++++ .../gcc.target/aarch64/vqrdmulhs_lane_s32.c | 35 +++++++++++++ 48 files changed, 874 insertions(+), 20 deletions(-) create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c create mode 100644 gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c (limited to 'gcc-4.9/gcc/testsuite/gcc.target/aarch64') diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h index a95d06aa2..07e56fff8 100644 --- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/type-def.h @@ -34,6 +34,13 @@ struct hfa_fx2_t float b; }; +struct hfa_fx3_t +{ + float a; + float b; + float c; +}; + struct hfa_dx2_t { double a; diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c new file mode 100644 index 000000000..ae1e3ec45 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-13.c @@ -0,0 +1,59 @@ +/* Test AAPCS64 layout and __builtin_va_start. + + Pass named HFA/HVA argument on stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-13.c" + +struct float_float_t +{ + float a; + float b; +} float_float; + +union float_int_t +{ + float b8; + int b5; +} float_int; + +#define HAS_DATA_INIT_FUNC +void +init_data () +{ + float_float.a = 1.2f; + float_float.b = 2.2f; + + float_int.b8 = 4983.80f; +} + +#include "abitest.h" +#else + ARG (float, 1.0f, S0, 0) + ARG (float, 2.0f, S1, 1) + ARG (float, 3.0f, S2, 2) + ARG (float, 4.0f, S3, 3) + ARG (float, 5.0f, S4, 4) + ARG (float, 6.0f, S5, 5) + ARG (float, 7.0f, S6, 6) + ARG (struct float_float_t, float_float, STACK, 7) + ARG (int, 9, W0, 8) + ARG (int, 10, W1, 9) + ARG (int, 11, W2, 10) + ARG (int, 12, W3, 11) + ARG (int, 13, W4, 12) + ARG (int, 14, W5, 13) + ARG (int, 15, W6, LAST_NAMED_ARG_ID) + DOTS + /* Note on the reason of using 'X7' instead of 'W7' here: + Using 'X7' makes sure the test works in the big-endian mode. + According to PCS rules B.4 and C.10, the size of float_int is rounded + to 8 bytes and prepared in the register X7 as if loaded via LDR from + the memory, with the content of the other 4 bytes unspecified. The + test framework will only compare the 4 relavent bytes. */ + ANON (union float_int_t, float_int, X7, 15) + LAST_ANON (long long, 12683143434LL, STACK + 8, 16) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c new file mode 100644 index 000000000..91080d5af --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-14.c @@ -0,0 +1,35 @@ +/* Test AAPCS64 layout and __builtin_va_start. + + Pass named HFA/HVA argument on stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-14.c" +#include "type-def.h" + +struct hfa_fx2_t hfa_fx2 = {1.2f, 2.2f}; +struct hfa_fx3_t hfa_fx3 = {3.2f, 4.2f, 5.2f}; +vf4_t float32x4 = {6.2f, 7.2f, 8.2f, 9.2f}; +vf4_t float32x4_2 = {10.2f, 11.2f, 12.2f, 13.2f}; + +#include "abitest.h" +#else + ARG (float, 1.0f, S0, 0) + ARG (float, 2.0f, S1, 1) + ARG (float, 3.0f, S2, 2) + ARG (float, 4.0f, S3, 3) + ARG (float, 5.0f, S4, 4) + ARG (float, 6.0f, S5, 5) + ARG (float, 7.0f, S6, 6) + ARG (struct hfa_fx3_t, hfa_fx3, STACK, 7) + /* Previous argument size has been rounded up to the nearest multiple of + 8 bytes. */ + ARG (struct hfa_fx2_t, hfa_fx2, STACK + 16, 8) + /* NSAA is rounded up to the nearest natural alignment of float32x4. */ + ARG (vf4_t, float32x4, STACK + 32, 9) + ARG (vf4_t, float32x4_2, STACK + 48, LAST_NAMED_ARG_ID) + DOTS + LAST_ANON (double, 123456789.987, STACK + 64, 11) +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c new file mode 100644 index 000000000..d8fdb322b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/aapcs64/va_arg-15.c @@ -0,0 +1,39 @@ +/* Test AAPCS64 layout and __builtin_va_start. + + Pass named __128int argument on stack. */ + +/* { dg-do run { target aarch64*-*-* } } */ + +#ifndef IN_FRAMEWORK +#define AAPCS64_TEST_STDARG +#define TESTFILE "va_arg-15.c" +#include "type-def.h" + +union int128_t qword; + +#define HAS_DATA_INIT_FUNC +void +init_data () +{ + /* Init signed quad-word integer. */ + qword.l64 = 0xfdb9753102468aceLL; + qword.h64 = 0xeca8642013579bdfLL; +} + +#include "abitest.h" +#else + ARG (int, 1, W0, 0) + ARG (int, 2, W1, 1) + ARG (int, 3, W2, 2) + ARG (int, 4, W3, 3) + ARG (int, 5, W4, 4) + ARG (int, 6, W5, 5) + ARG (int, 7, W6, 6) + ARG (__int128, qword.i, STACK, LAST_NAMED_ARG_ID) + DOTS +#ifndef __AAPCS64_BIG_ENDIAN__ + LAST_ANON (int, 8, STACK + 16, 8) +#else + LAST_ANON (int, 8, STACK + 20, 8) +#endif +#endif diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c new file mode 100644 index 000000000..45ece5344 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/pr61325.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ +typedef unsigned int wchar_t; +typedef long unsigned int size_t; + +size_t +wcstombs(char *s , const wchar_t *pwcs , size_t n) +{ + int count = 0; + + if (n != 0) { + do { + if ((*s++ = (char) *pwcs++) == 0) + break; + count++; + } while (--n != 0); + } + return count; +} diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c index aa041cc2c..782f6d194 100644 --- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/scalar_intrinsics.c @@ -387,7 +387,7 @@ test_vqdmlalh_s16 (int32x1_t a, int16x1_t b, int16x1_t c) /* { dg-final { scan-assembler-times "\\tsqdmlal\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ int32x1_t -test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c) +test_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) { return vqdmlalh_lane_s16 (a, b, c, 3); } @@ -403,7 +403,7 @@ test_vqdmlals_s32 (int64x1_t a, int32x1_t b, int32x1_t c) /* { dg-final { scan-assembler-times "\\tsqdmlal\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ int64x1_t -test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c) +test_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) { return vqdmlals_lane_s32 (a, b, c, 1); } @@ -419,7 +419,7 @@ test_vqdmlslh_s16 (int32x1_t a, int16x1_t b, int16x1_t c) /* { dg-final { scan-assembler-times "\\tsqdmlsl\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ int32x1_t -test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x8_t c) +test_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) { return vqdmlslh_lane_s16 (a, b, c, 3); } @@ -435,7 +435,7 @@ test_vqdmlsls_s32 (int64x1_t a, int32x1_t b, int32x1_t c) /* { dg-final { scan-assembler-times "\\tsqdmlsl\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ int64x1_t -test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x4_t c) +test_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) { return vqdmlsls_lane_s32 (a, b, c, 1); } @@ -451,7 +451,7 @@ test_vqdmulhh_s16 (int16x1_t a, int16x1_t b) /* { dg-final { scan-assembler-times "\\tsqdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */ int16x1_t -test_vqdmulhh_lane_s16 (int16x1_t a, int16x8_t b) +test_vqdmulhh_lane_s16 (int16x1_t a, int16x4_t b) { return vqdmulhh_lane_s16 (a, b, 3); } @@ -467,9 +467,9 @@ test_vqdmulhs_s32 (int32x1_t a, int32x1_t b) /* { dg-final { scan-assembler-times "\\tsqdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */ int32x1_t -test_vqdmulhs_lane_s32 (int32x1_t a, int32x4_t b) +test_vqdmulhs_lane_s32 (int32x1_t a, int32x2_t b) { - return vqdmulhs_lane_s32 (a, b, 3); + return vqdmulhs_lane_s32 (a, b, 1); } /* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, h\[0-9\]+" 1 } } */ @@ -483,7 +483,7 @@ test_vqdmullh_s16 (int16x1_t a, int16x1_t b) /* { dg-final { scan-assembler-times "\\tsqdmull\\ts\[0-9\]+, h\[0-9\]+, v" 1 } } */ int32x1_t -test_vqdmullh_lane_s16 (int16x1_t a, int16x8_t b) +test_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b) { return vqdmullh_lane_s16 (a, b, 3); } @@ -499,7 +499,7 @@ test_vqdmulls_s32 (int32x1_t a, int32x1_t b) /* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */ int64x1_t -test_vqdmulls_lane_s32 (int32x1_t a, int32x4_t b) +test_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b) { return vqdmulls_lane_s32 (a, b, 1); } @@ -515,9 +515,9 @@ test_vqrdmulhh_s16 (int16x1_t a, int16x1_t b) /* { dg-final { scan-assembler-times "\\tsqrdmulh\\th\[0-9\]+, h\[0-9\]+, v" 1 } } */ int16x1_t -test_vqrdmulhh_lane_s16 (int16x1_t a, int16x8_t b) +test_vqrdmulhh_lane_s16 (int16x1_t a, int16x4_t b) { - return vqrdmulhh_lane_s16 (a, b, 6); + return vqrdmulhh_lane_s16 (a, b, 3); } /* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, s\[0-9\]+" 1 } } */ @@ -531,9 +531,9 @@ test_vqrdmulhs_s32 (int32x1_t a, int32x1_t b) /* { dg-final { scan-assembler-times "\\tsqrdmulh\\ts\[0-9\]+, s\[0-9\]+, v" 1 } } */ int32x1_t -test_vqrdmulhs_lane_s32 (int32x1_t a, int32x4_t b) +test_vqrdmulhs_lane_s32 (int32x1_t a, int32x2_t b) { - return vqrdmulhs_lane_s32 (a, b, 2); + return vqrdmulhs_lane_s32 (a, b, 1); } /* { dg-final { scan-assembler-times "\\tsuqadd\\tb\[0-9\]+" 1 } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c index affb8a8a1..52b0496c8 100644 --- a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vector_intrinsics.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-O2" } */ -#include "../../../config/aarch64/arm_neon.h" +#include "arm_neon.h" /* { dg-final { scan-assembler-times "\\tfmax\\tv\[0-9\]+\.2s, v\[0-9\].2s, v\[0-9\].2s" 1 } } */ @@ -305,7 +305,7 @@ test_vqdmlal_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) /* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */ int32x4_t -test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c) +test_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c) { return vqdmlal_high_lane_s16 (a, b, c, 3); } @@ -361,7 +361,7 @@ test_vqdmlal_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) /* { dg-final { scan-assembler-times "\\tsqdmlal2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */ int64x2_t -test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) +test_vqdmlal_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c) { return vqdmlal_high_lane_s32 (__a, __b, __c, 1); } @@ -417,7 +417,7 @@ test_vqdmlsl_high_s16 (int32x4_t __a, int16x8_t __b, int16x8_t __c) /* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */ int32x4_t -test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x8_t c) +test_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c) { return vqdmlsl_high_lane_s16 (a, b, c, 3); } @@ -473,7 +473,7 @@ test_vqdmlsl_high_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) /* { dg-final { scan-assembler-times "\\tsqdmlsl2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */ int64x2_t -test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x4_t __c) +test_vqdmlsl_high_lane_s32 (int64x2_t __a, int32x4_t __b, int32x2_t __c) { return vqdmlsl_high_lane_s32 (__a, __b, __c, 1); } @@ -529,7 +529,7 @@ test_vqdmull_high_s16 (int16x8_t __a, int16x8_t __b) /* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.4s, v\[0-9\]+\.8h, v\[0-9\]+\.h" 3 } } */ int32x4_t -test_vqdmull_high_lane_s16 (int16x8_t a, int16x8_t b) +test_vqdmull_high_lane_s16 (int16x8_t a, int16x4_t b) { return vqdmull_high_lane_s16 (a, b, 3); } @@ -585,7 +585,7 @@ test_vqdmull_high_s32 (int32x4_t __a, int32x4_t __b) /* { dg-final { scan-assembler-times "\\tsqdmull2\\tv\[0-9\]+\.2d, v\[0-9\]+\.4s, v\[0-9\]+\.s" 3 } } */ int64x2_t -test_vqdmull_high_lane_s32 (int32x4_t __a, int32x4_t __b) +test_vqdmull_high_lane_s32 (int32x4_t __a, int32x2_t __b) { return vqdmull_high_lane_s32 (__a, __b, 1); } diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c new file mode 100644 index 000000000..1388c3b61 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_high_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c) +{ + return vqdmlal_high_lane_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c new file mode 100644 index 000000000..f90387dba --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_high_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlal_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t c) +{ + return vqdmlal_high_lane_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c new file mode 100644 index 000000000..5399ce985 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_high_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c) +{ + return vqdmlal_high_laneq_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c new file mode 100644 index 000000000..e4b55582e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_high_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_high_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlal_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t c) +{ + return vqdmlal_high_laneq_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c new file mode 100644 index 000000000..7e60c8220 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c) +{ + return vqdmlal_lane_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c new file mode 100644 index 000000000..c0f508dc9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlal_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t c) +{ + return vqdmlal_lane_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c new file mode 100644 index 000000000..9bf130435 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t c) +{ + return vqdmlal_laneq_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c new file mode 100644 index 000000000..5fd9c56dc --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlal_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlal_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlal_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t c) +{ + return vqdmlal_laneq_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c new file mode 100644 index 000000000..83f5af596 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlalh_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlalh_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x1_t +t_vqdmlalh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) +{ + return vqdmlalh_lane_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c new file mode 100644 index 000000000..ef94e95d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlals_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlals_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x1_t +t_vqdmlals_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) +{ + return vqdmlals_lane_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlal\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c new file mode 100644 index 000000000..276a1a2a9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_high_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t c) +{ + return vqdmlsl_high_lane_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c new file mode 100644 index 000000000..2ae58ef0b --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_high_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlsl_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t c) +{ + return vqdmlsl_high_lane_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c new file mode 100644 index 000000000..1db5db4c9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_high_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t c) +{ + return vqdmlsl_high_laneq_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c new file mode 100644 index 000000000..3a72a7bca --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_high_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_high_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlsl_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t c) +{ + return vqdmlsl_high_laneq_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c new file mode 100644 index 000000000..0535378e4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t c) +{ + return vqdmlsl_lane_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c new file mode 100644 index 000000000..b52e51e1a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t c) +{ + return vqdmlsl_lane_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c new file mode 100644 index 000000000..7009a35f2 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsl_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsl_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x4_t c) +{ + return vqdmlsl_laneq_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c new file mode 100644 index 000000000..056dfbb11 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlslh_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmlslh_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x1_t +t_vqdmlslh_lane_s16 (int32x1_t a, int16x1_t b, int16x4_t c) +{ + return vqdmlslh_lane_s16 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c new file mode 100644 index 000000000..9e351bc36 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmlsls_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmlsls_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x1_t +t_vqdmlsls_lane_s32 (int64x1_t a, int32x1_t b, int32x2_t c) +{ + return vqdmlsls_lane_s32 (a, b, c, 0); +} + +/* { dg-final { scan-assembler-times "sqdmlsl\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c new file mode 100644 index 000000000..d3c699bd3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmulh_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int16x4_t +t_vqdmulh_laneq_s16 (int16x4_t a, int16x8_t b) +{ + return vqdmulh_laneq_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c new file mode 100644 index 000000000..c6202ce19 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulh_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmulh_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x2_t +t_vqdmulh_laneq_s32 (int32x2_t a, int32x4_t b) +{ + return vqdmulh_laneq_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c new file mode 100644 index 000000000..763585100 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhh_lane_s16.c @@ -0,0 +1,36 @@ +/* Test the vqdmulhh_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" +#include + +extern void abort (void); + +int +main (void) +{ + int16_t arg1; + int16x4_t arg2; + int16_t result; + int16_t actual; + int16_t expected; + + arg1 = -32768; + arg2 = vcreate_s16 (0x0000ffff2489e398ULL); + actual = vqdmulhh_lane_s16 (arg1, arg2, 2); + expected = 1; + + if (expected != actual) + { + fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual); + abort (); + } + + return 0; +} + + +/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[hH\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[2\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c new file mode 100644 index 000000000..809c85a77 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmulhq_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int16x8_t +t_vqdmulhq_laneq_s16 (int16x8_t a, int16x8_t b) +{ + return vqdmulhq_laneq_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c new file mode 100644 index 000000000..d375fe818 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhq_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmulhq_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmulhq_laneq_s32 (int32x4_t a, int32x4_t b) +{ + return vqdmulhq_laneq_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c new file mode 100644 index 000000000..9c27f5f3a --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulhs_lane_s32.c @@ -0,0 +1,34 @@ +/* Test the vqdmulhs_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" +#include + +extern void abort (void); + +int +main (void) +{ + int32_t arg1; + int32x2_t arg2; + int32_t result; + int32_t actual; + int32_t expected; + + arg1 = 57336; + arg2 = vcreate_s32 (0x55897fff7fff0000ULL); + actual = vqdmulhs_lane_s32 (arg1, arg2, 0); + expected = 57334; + + if (expected != actual) + { + fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual); + abort (); + } + + return 0; +} +/* { dg-final { scan-assembler-times "sqdmulh\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c new file mode 100644 index 000000000..0af320e2c --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_high_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmull_high_lane_s16 (int16x8_t a, int16x4_t b) +{ + return vqdmull_high_lane_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c new file mode 100644 index 000000000..583e8a172 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_high_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmull_high_lane_s32 (int32x4_t a, int32x2_t b) +{ + return vqdmull_high_lane_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c new file mode 100644 index 000000000..dcfd14c71 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_high_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmull_high_laneq_s16 (int16x8_t a, int16x8_t b) +{ + return vqdmull_high_laneq_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c new file mode 100644 index 000000000..3e8b652d9 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_high_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_high_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmull_high_laneq_s32 (int32x4_t a, int32x4_t b) +{ + return vqdmull_high_laneq_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull2\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c new file mode 100644 index 000000000..695d4e3fb --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmull_lane_s16 (int16x4_t a, int16x4_t b) +{ + return vqdmull_lane_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c new file mode 100644 index 000000000..e6a02b573 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmull_lane_s32 (int32x2_t a, int32x2_t b) +{ + return vqdmull_lane_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c new file mode 100644 index 000000000..ba761b231 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqdmull_laneq_s16 (int16x4_t a, int16x8_t b) +{ + return vqdmull_laneq_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c new file mode 100644 index 000000000..82b8e19ed --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmull_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmull_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x2_t +t_vqdmull_laneq_s32 (int32x2_t a, int32x4_t b) +{ + return vqdmull_laneq_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[vV\]\[0-9\]+\.2\[dD\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c new file mode 100644 index 000000000..fd271e0b3 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmullh_lane_s16.c @@ -0,0 +1,15 @@ +/* Test the vqdmullh_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x1_t +t_vqdmullh_lane_s16 (int16x1_t a, int16x4_t b) +{ + return vqdmullh_lane_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c new file mode 100644 index 000000000..110333375 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqdmulls_lane_s32.c @@ -0,0 +1,15 @@ +/* Test the vqdmulls_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int64x1_t +t_vqdmulls_lane_s32 (int32x1_t a, int32x2_t b) +{ + return vqdmulls_lane_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c new file mode 100644 index 000000000..0313f1c07 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqrdmulh_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int16x4_t +t_vqrdmulh_laneq_s16 (int16x4_t a, int16x8_t b) +{ + return vqrdmulh_laneq_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.4\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c new file mode 100644 index 000000000..a9124ee10 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulh_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqrdmulh_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x2_t +t_vqrdmulh_laneq_s32 (int32x2_t a, int32x4_t b) +{ + return vqrdmulh_laneq_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.2\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c new file mode 100644 index 000000000..f21863ab4 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhh_lane_s16.c @@ -0,0 +1,35 @@ +/* Test the vqrdmulhh_lane_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" +#include + +extern void abort (void); + +int +main (void) +{ + int16_t arg1; + int16x4_t arg2; + int16_t result; + int16_t actual; + int16_t expected; + + arg1 = -32768; + arg2 = vcreate_s16 (0xd78e000005d78000ULL); + actual = vqrdmulhh_lane_s16 (arg1, arg2, 3); + expected = 10354; + + if (expected != actual) + { + fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual); + abort (); + } + + return 0; +} + +/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[hH\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[3\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c new file mode 100644 index 000000000..488e694ab --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s16.c @@ -0,0 +1,15 @@ +/* Test the vqrdmulhq_laneq_s16 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int16x8_t +t_vqrdmulhq_laneq_s16 (int16x8_t a, int16x8_t b) +{ + return vqrdmulhq_laneq_s16 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.8\[hH\], ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c new file mode 100644 index 000000000..42519f615 --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhq_laneq_s32.c @@ -0,0 +1,15 @@ +/* Test the vqrdmulhq_laneq_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do compile } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" + +int32x4_t +t_vqrdmulhq_laneq_s32 (int32x4_t a, int32x4_t b) +{ + return vqrdmulhq_laneq_s32 (a, b, 0); +} + +/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.4\[sS\], ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c new file mode 100644 index 000000000..83d2ba28e --- /dev/null +++ b/gcc-4.9/gcc/testsuite/gcc.target/aarch64/vqrdmulhs_lane_s32.c @@ -0,0 +1,35 @@ +/* Test the vqrdmulhs_lane_s32 AArch64 SIMD intrinsic. */ + +/* { dg-do run } */ +/* { dg-options "-save-temps -O3 -fno-inline" } */ + +#include "arm_neon.h" +#include + +extern void abort (void); + +int +main (void) +{ + int32_t arg1; + int32x2_t arg2; + int32_t result; + int32_t actual; + int32_t expected; + + arg1 = -2099281921; + arg2 = vcreate_s32 (0x000080007fff0000ULL); + actual = vqrdmulhs_lane_s32 (arg1, arg2, 1); + expected = -32033; + + if (expected != actual) + { + fprintf (stderr, "Expected: %xd, got %xd\n", expected, actual); + abort (); + } + + return 0; +} + +/* { dg-final { scan-assembler-times "sqrdmulh\[ \t\]+\[sS\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[1\\\]\n" 1 } } */ +/* { dg-final { cleanup-saved-temps } } */ -- cgit v1.2.3