From e97c99f15937e5762a973b25192aab824126a6d3 Mon Sep 17 00:00:00 2001 From: Rong Xu Date: Tue, 2 Sep 2014 15:29:57 -0700 Subject: [gcc-4.9] Merge svn r214745 from google/gcc-4_9 branch. Merge gcc-4_9 source r214745 from google/gcc-4_9 branch. Change-Id: Ie6fa0fd72f4b4eec3adc4db4bb922e652d1c2605 --- gcc-4.9/gcc/config/arm/vfp.md | 10 +- gcc-4.9/gcc/config/i386/driver-i386.c | 5 +- gcc-4.9/gcc/config/i386/i386.c | 15 +- gcc-4.9/gcc/config/i386/i386.h | 2 + gcc-4.9/gcc/config/i386/i386.md | 175 ++++++++++++---- gcc-4.9/gcc/config/i386/sse.md | 4 +- gcc-4.9/gcc/config/i386/x86-tune.def | 5 + gcc-4.9/gcc/config/nios2/rtems.h | 34 ++++ gcc-4.9/gcc/config/nios2/t-rtems | 133 +++++++++++++ gcc-4.9/gcc/config/pa/pa-protos.h | 2 + gcc-4.9/gcc/config/pa/pa.c | 87 +++++--- gcc-4.9/gcc/config/pa/pa.h | 10 + gcc-4.9/gcc/config/pa/pa.md | 30 --- gcc-4.9/gcc/config/rs6000/constraints.md | 16 +- gcc-4.9/gcc/config/rs6000/rs6000.c | 149 +++++++++----- gcc-4.9/gcc/config/rs6000/rs6000.h | 171 ++++++++++++---- gcc-4.9/gcc/config/rs6000/rs6000.md | 28 +-- gcc-4.9/gcc/config/rs6000/vsx.md | 331 +++++++++++++++++-------------- gcc-4.9/gcc/config/sh/sh.c | 6 + gcc-4.9/gcc/config/sh/sh.opt | 2 +- 20 files changed, 844 insertions(+), 371 deletions(-) create mode 100644 gcc-4.9/gcc/config/nios2/rtems.h create mode 100644 gcc-4.9/gcc/config/nios2/t-rtems (limited to 'gcc-4.9/gcc/config') diff --git a/gcc-4.9/gcc/config/arm/vfp.md b/gcc-4.9/gcc/config/arm/vfp.md index e1a48eeea..76464849d 100644 --- a/gcc-4.9/gcc/config/arm/vfp.md +++ b/gcc-4.9/gcc/config/arm/vfp.md @@ -1254,17 +1254,15 @@ ) (define_insn "*combine_vcvtf2i" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "t") + [(set (match_operand:SI 0 "s_register_operand" "=t") + (fix:SI (fix:SF (mult:SF (match_operand:SF 1 "s_register_operand" "0") (match_operand 2 "const_double_vcvt_power_of_two" "Dp")))))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP3 && !flag_rounding_math" - "vcvt%?.s32.f32\\t%1, %1, %v2\;vmov%?\\t%0, %1" + "vcvt%?.s32.f32\\t%0, %1, %v2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "ce_count" "2") - (set_attr "type" "f_cvtf2i") - (set_attr "length" "8")] + (set_attr "type" "f_cvtf2i")] ) ;; Store multiple insn used in function prologue. diff --git a/gcc-4.9/gcc/config/i386/driver-i386.c b/gcc-4.9/gcc/config/i386/driver-i386.c index 80f6a0879..722c54692 100644 --- a/gcc-4.9/gcc/config/i386/driver-i386.c +++ b/gcc-4.9/gcc/config/i386/driver-i386.c @@ -431,7 +431,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) model = (eax >> 4) & 0x0f; family = (eax >> 8) & 0x0f; - if (vendor == signature_INTEL_ebx) + if (vendor == signature_INTEL_ebx + || vendor == signature_AMD_ebx) { unsigned int extended_model, extended_family; @@ -570,7 +571,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (name == signature_NSC_ebx) processor = PROCESSOR_GEODE; - else if (has_movbe) + else if (has_movbe && family == 22) processor = PROCESSOR_BTVER2; else if (has_avx2) processor = PROCESSOR_BDVER4; diff --git a/gcc-4.9/gcc/config/i386/i386.c b/gcc-4.9/gcc/config/i386/i386.c index 70f18ad7b..85ceff337 100644 --- a/gcc-4.9/gcc/config/i386/i386.c +++ b/gcc-4.9/gcc/config/i386/i386.c @@ -3259,12 +3259,13 @@ ix86_option_override_internal (bool main_args_p, | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE}, {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4, - PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 - | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 - | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 + PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1 + | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR - | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE}, + | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND + | PTA_MOVBE}, {"btver1", PROCESSOR_BTVER1, CPU_GENERIC, PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW @@ -45348,8 +45349,10 @@ ix86_expand_sse2_mulvxdi3 (rtx op0, rtx op1, rtx op2) /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */ emit_insn (gen_ashlv2di3 (t4, t3, GEN_INT (32))); - /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */ - emit_insn (gen_xop_pmacsdql (op0, op1, op2, t4)); + /* Multiply lower parts and add all */ + t5 = gen_reg_rtx (V2DImode); + emit_insn (gen_vec_widen_umult_even_v4si (t5, gen_lowpart (V4SImode, op1), gen_lowpart (V4SImode, op2))); + op0 = expand_binop (mode, add_optab, t5, t4, op0, 1, OPTAB_DIRECT); } else { diff --git a/gcc-4.9/gcc/config/i386/i386.h b/gcc-4.9/gcc/config/i386/i386.h index 51659deb3..b3b7c8d30 100644 --- a/gcc-4.9/gcc/config/i386/i386.h +++ b/gcc-4.9/gcc/config/i386/i386.h @@ -457,6 +457,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; ix86_tune_features[X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS] #define TARGET_ADJUST_UNROLL \ ix86_tune_features[X86_TUNE_ADJUST_UNROLL] +#define TARGET_AVOID_FALSE_DEP_FOR_BMI \ + ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] /* Feature tests against the various architecture variations. */ enum ix86_arch_indices { diff --git a/gcc-4.9/gcc/config/i386/i386.md b/gcc-4.9/gcc/config/i386/i386.md index 058702904..39d395875 100644 --- a/gcc-4.9/gcc/config/i386/i386.md +++ b/gcc-4.9/gcc/config/i386/i386.md @@ -111,6 +111,7 @@ UNSPEC_LEA_ADDR UNSPEC_XBEGIN_ABORT UNSPEC_STOS + UNSPEC_INSN_FALSE_DEP ;; For SSE/MMX support: UNSPEC_FIX_NOTRUNC @@ -11878,7 +11879,8 @@ DONE; } - flags_mode = TARGET_BMI ? CCCmode : CCZmode; + flags_mode + = (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode; operands[2] = gen_reg_rtx (mode); operands[3] = gen_rtx_REG (flags_mode, FLAGS_REG); @@ -11904,7 +11906,8 @@ (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (const_int 1))) (clobber (reg:CC FLAGS_REG))])] { - enum machine_mode flags_mode = TARGET_BMI ? CCCmode : CCZmode; + enum machine_mode flags_mode + = (TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI) ? CCCmode : CCZmode; operands[3] = gen_lowpart (QImode, operands[2]); operands[4] = gen_rtx_REG (flags_mode, FLAGS_REG); @@ -11919,7 +11922,7 @@ (const_int 0))) (set (match_operand:SWI48 0 "register_operand" "=r") (ctz:SWI48 (match_dup 1)))] - "TARGET_BMI" + "TARGET_BMI && !TARGET_AVOID_FALSE_DEP_FOR_BMI" "tzcnt{}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") (set_attr "prefix_0f" "1") @@ -11940,7 +11943,58 @@ (set_attr "btver2_decode" "double") (set_attr "mode" "")]) -(define_insn "ctz2" +(define_expand "ctz2" + [(parallel + [(set (match_operand:SWI248 0 "register_operand") + (ctz:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))])]) + +; False dependency happens when destination is only updated by tzcnt, +; lzcnt or popcnt. There is no false dependency when destination is +; also used in source. +(define_insn_and_split "*ctz2_falsedep_1" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (ctz:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) + (clobber (reg:CC FLAGS_REG))] + "(TARGET_BMI || TARGET_GENERIC) + && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) + (ctz:SWI48 (match_dup 1))) + (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))])] +{ + if (!reg_mentioned_p (operands[0], operands[1])) + ix86_expand_clear (operands[0]); +}) + +(define_insn "*ctz2_falsedep" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (ctz:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) + (unspec [(match_operand:SWI48 2 "register_operand" "0")] + UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))] + "" +{ + if (TARGET_BMI) + return "tzcnt{}\t{%1, %0|%0, %1}"; + else if (TARGET_GENERIC) + /* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */ + return "rep%; bsf{}\t{%1, %0|%0, %1}"; + else + gcc_unreachable (); +} + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1") + (set_attr "mode" "")]) + +(define_insn "*ctz2" [(set (match_operand:SWI248 0 "register_operand" "=r") (ctz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm"))) (clobber (reg:CC FLAGS_REG))] @@ -11987,7 +12041,47 @@ operands[2] = GEN_INT (GET_MODE_BITSIZE (mode)-1); }) -(define_insn "clz2_lzcnt" +(define_expand "clz2_lzcnt" + [(parallel + [(set (match_operand:SWI248 0 "register_operand") + (clz:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_LZCNT") + +(define_insn_and_split "*clz2_lzcnt_falsedep_1" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (clz:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_LZCNT + && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) + (clz:SWI48 (match_dup 1))) + (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))])] +{ + if (!reg_mentioned_p (operands[0], operands[1])) + ix86_expand_clear (operands[0]); +}) + +(define_insn "*clz2_lzcnt_falsedep" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (clz:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) + (unspec [(match_operand:SWI48 2 "register_operand" "0")] + UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))] + "TARGET_LZCNT" + "lzcnt{}\t{%1, %0|%0, %1}" + [(set_attr "prefix_rep" "1") + (set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*clz2_lzcnt" [(set (match_operand:SWI248 0 "register_operand" "=r") (clz:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "rm"))) (clobber (reg:CC FLAGS_REG))] @@ -12270,10 +12364,39 @@ (set_attr "prefix_0f" "1") (set_attr "mode" "HI")]) -(define_insn "popcount2" - [(set (match_operand:SWI248 0 "register_operand" "=r") - (popcount:SWI248 - (match_operand:SWI248 1 "nonimmediate_operand" "rm"))) +(define_expand "popcount2" + [(parallel + [(set (match_operand:SWI248 0 "register_operand") + (popcount:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))])] + "TARGET_POPCNT") + +(define_insn_and_split "*popcount2_falsedep_1" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (popcount:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_POPCNT + && TARGET_AVOID_FALSE_DEP_FOR_BMI && optimize_function_for_speed_p (cfun)" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) + (popcount:SWI48 (match_dup 1))) + (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))])] +{ + if (!reg_mentioned_p (operands[0], operands[1])) + ix86_expand_clear (operands[0]); +}) + +(define_insn "*popcount2_falsedep" + [(set (match_operand:SWI48 0 "register_operand" "=r") + (popcount:SWI48 + (match_operand:SWI48 1 "nonimmediate_operand" "rm"))) + (unspec [(match_operand:SWI48 2 "register_operand" "0")] + UNSPEC_INSN_FALSE_DEP) (clobber (reg:CC FLAGS_REG))] "TARGET_POPCNT" { @@ -12287,15 +12410,12 @@ (set_attr "type" "bitmanip") (set_attr "mode" "")]) -(define_insn "*popcount2_cmp" - [(set (reg FLAGS_REG) - (compare - (popcount:SWI248 - (match_operand:SWI248 1 "nonimmediate_operand" "rm")) - (const_int 0))) - (set (match_operand:SWI248 0 "register_operand" "=r") - (popcount:SWI248 (match_dup 1)))] - "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)" +(define_insn "*popcount2" + [(set (match_operand:SWI248 0 "register_operand" "=r") + (popcount:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand" "rm"))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_POPCNT" { #if TARGET_MACHO return "popcnt\t{%1, %0|%0, %1}"; @@ -12307,25 +12427,6 @@ (set_attr "type" "bitmanip") (set_attr "mode" "")]) -(define_insn "*popcountsi2_cmp_zext" - [(set (reg FLAGS_REG) - (compare - (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI(popcount:SI (match_dup 1))))] - "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)" -{ -#if TARGET_MACHO - return "popcnt\t{%1, %0|%0, %1}"; -#else - return "popcnt{l}\t{%1, %0|%0, %1}"; -#endif -} - [(set_attr "prefix_rep" "1") - (set_attr "type" "bitmanip") - (set_attr "mode" "SI")]) - (define_expand "bswapdi2" [(set (match_operand:DI 0 "register_operand") (bswap:DI (match_operand:DI 1 "nonimmediate_operand")))] diff --git a/gcc-4.9/gcc/config/i386/sse.md b/gcc-4.9/gcc/config/i386/sse.md index b60a8226d..8d061da95 100644 --- a/gcc-4.9/gcc/config/i386/sse.md +++ b/gcc-4.9/gcc/config/i386/sse.md @@ -5994,9 +5994,9 @@ (set_attr "mode" "")]) (define_insn "vec_extract_lo_" - [(set (match_operand: 0 "" "=") + [(set (match_operand: 0 "" "=,v") (vec_select: - (match_operand:V8FI 1 "nonimmediate_operand" "vm") + (match_operand:V8FI 1 "nonimmediate_operand" "v,m") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)])))] "TARGET_AVX512F && !(MEM_P (operands[0]) && MEM_P (operands[1]))" diff --git a/gcc-4.9/gcc/config/i386/x86-tune.def b/gcc-4.9/gcc/config/i386/x86-tune.def index 839910267..c36174855 100644 --- a/gcc-4.9/gcc/config/i386/x86-tune.def +++ b/gcc-4.9/gcc/config/i386/x86-tune.def @@ -500,6 +500,11 @@ DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6) DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode", m_K8) +/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency + for bit-manipulation instructions. */ +DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi", + m_SANDYBRIDGE | m_HASWELL | m_INTEL | m_GENERIC) + /*****************************************************************************/ /* This never worked well before. */ /*****************************************************************************/ diff --git a/gcc-4.9/gcc/config/nios2/rtems.h b/gcc-4.9/gcc/config/nios2/rtems.h new file mode 100644 index 000000000..18caa5809 --- /dev/null +++ b/gcc-4.9/gcc/config/nios2/rtems.h @@ -0,0 +1,34 @@ +/* Definitions for rtems targeting a NIOS2 using ELF. + Copyright (C) 2011-2014 Free Software Foundation, Inc. + + Contributed by Chris Johns (chrisj@rtems.org). + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* Specify predefined symbols in preprocessor. */ +#define TARGET_OS_CPP_BUILTINS() \ +do { \ + builtin_define ("__rtems__"); \ + builtin_define ("__USE_INIT_FINI__"); \ + builtin_assert ("system=rtems"); \ +} while (0) + +/* This toolchain implements the ABI for Linux Systems documented in the + Nios II Processor Reference Handbook. + + This is done so RTEMS targets have Thread Local Storage like Linux. */ +#define TARGET_LINUX_ABI 1 diff --git a/gcc-4.9/gcc/config/nios2/t-rtems b/gcc-4.9/gcc/config/nios2/t-rtems new file mode 100644 index 000000000..f95fa3c47 --- /dev/null +++ b/gcc-4.9/gcc/config/nios2/t-rtems @@ -0,0 +1,133 @@ +# Custom RTEMS multilibs + +MULTILIB_OPTIONS = mhw-mul mhw-mulx mhw-div mcustom-fadds=253 mcustom-fdivs=255 mcustom-fmuls=252 mcustom-fsubs=254 + +# Enumeration of multilibs + +# MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div/mcustom-fsubs=254 +# MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mhw-div +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-mulx +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mhw-div +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mul/mcustom-fsubs=254 +# MULTILIB_EXCEPTIONS += mhw-mul +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mhw-div +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-mulx/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-mulx +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mhw-div/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mhw-div +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mcustom-fadds=253/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fadds=253 +MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mcustom-fdivs=255/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fdivs=255 +MULTILIB_EXCEPTIONS += mcustom-fmuls=252/mcustom-fsubs=254 +MULTILIB_EXCEPTIONS += mcustom-fmuls=252 +MULTILIB_EXCEPTIONS += mcustom-fsubs=254 diff --git a/gcc-4.9/gcc/config/pa/pa-protos.h b/gcc-4.9/gcc/config/pa/pa-protos.h index 2659dcdf0..1e48da512 100644 --- a/gcc-4.9/gcc/config/pa/pa-protos.h +++ b/gcc-4.9/gcc/config/pa/pa-protos.h @@ -49,6 +49,8 @@ extern const char *pa_output_mul_insn (int, rtx); extern const char *pa_output_div_insn (rtx *, int, rtx); extern const char *pa_output_mod_insn (int, rtx); extern const char *pa_singlemove_string (rtx *); +extern void pa_output_addr_vec (rtx, rtx); +extern void pa_output_addr_diff_vec (rtx, rtx); extern void pa_output_arg_descriptor (rtx); extern void pa_output_global_address (FILE *, rtx, int); extern void pa_print_operand (FILE *, rtx, int); diff --git a/gcc-4.9/gcc/config/pa/pa.c b/gcc-4.9/gcc/config/pa/pa.c index 871e4e5c6..5a7598ca7 100644 --- a/gcc-4.9/gcc/config/pa/pa.c +++ b/gcc-4.9/gcc/config/pa/pa.c @@ -4155,8 +4155,7 @@ static void pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { rtx insn = get_last_insn (); - - last_address = 0; + bool extra_nop; /* pa_expand_epilogue does the dirty work now. We just need to output the assembler directives which denote the end @@ -4180,8 +4179,10 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) if (insn && CALL_P (insn)) { fputs ("\tnop\n", file); - last_address += 4; + extra_nop = true; } + else + extra_nop = false; fputs ("\t.EXIT\n\t.PROCEND\n", file); @@ -4194,12 +4195,13 @@ pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) cfun->machine->in_nsubspa = 2; } - /* Thunks do their own accounting. */ + /* Thunks do their own insn accounting. */ if (cfun->is_thunk) return; if (INSN_ADDRESSES_SET_P ()) { + last_address = extra_nop ? 4 : 0; insn = get_last_nonnote_insn (); last_address += INSN_ADDRESSES (INSN_UID (insn)); if (INSN_P (insn)) @@ -8293,12 +8295,16 @@ pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta, || ((DECL_SECTION_NAME (thunk_fndecl) == DECL_SECTION_NAME (function)) && last_address < 262132))) + /* In this case, we need to be able to reach the start of + the stub table even though the function is likely closer + and can be jumped to directly. */ || (targetm_common.have_named_sections && DECL_SECTION_NAME (thunk_fndecl) == NULL && DECL_SECTION_NAME (function) == NULL - && last_address < 262132) + && total_code_bytes < MAX_PCREL17F_OFFSET) + /* Likewise. */ || (!targetm_common.have_named_sections - && last_address < 262132)))) + && total_code_bytes < MAX_PCREL17F_OFFSET)))) { if (!val_14) output_asm_insn ("addil L'%2,%%r26", xoperands); @@ -8944,40 +8950,15 @@ pa_following_call (rtx insn) } /* We use this hook to perform a PA specific optimization which is difficult - to do in earlier passes. - - We surround the jump table itself with BEGIN_BRTAB and END_BRTAB - insns. Those insns mark where we should emit .begin_brtab and - .end_brtab directives when using GAS. This allows for better link - time optimizations. */ + to do in earlier passes. */ static void pa_reorg (void) { - rtx insn; - remove_useless_addtr_insns (1); if (pa_cpu < PROCESSOR_8000) pa_combine_instructions (); - - /* Still need brtab marker insns. FIXME: the presence of these - markers disables output of the branch table to readonly memory, - and any alignment directives that might be needed. Possibly, - the begin_brtab insn should be output before the label for the - table. This doesn't matter at the moment since the tables are - always output in the text section. */ - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - /* Find an ADDR_VEC insn. */ - if (! JUMP_TABLE_DATA_P (insn)) - continue; - - /* Now generate markers for the beginning and end of the - branch table. */ - emit_insn_before (gen_begin_brtab (), insn); - emit_insn_after (gen_end_brtab (), insn); - } } /* The PA has a number of odd instructions which can perform multiple @@ -10572,4 +10553,46 @@ pa_legitimize_reload_address (rtx ad, enum machine_mode mode, return NULL_RTX; } +/* Output address vector. */ + +void +pa_output_addr_vec (rtx lab, rtx body) +{ + int idx, vlen = XVECLEN (body, 0); + + targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); + if (TARGET_GAS) + fputs ("\t.begin_brtab\n", asm_out_file); + for (idx = 0; idx < vlen; idx++) + { + ASM_OUTPUT_ADDR_VEC_ELT + (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); + } + if (TARGET_GAS) + fputs ("\t.end_brtab\n", asm_out_file); +} + +/* Output address difference vector. */ + +void +pa_output_addr_diff_vec (rtx lab, rtx body) +{ + rtx base = XEXP (XEXP (body, 0), 0); + int idx, vlen = XVECLEN (body, 1); + + targetm.asm_out.internal_label (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); + if (TARGET_GAS) + fputs ("\t.begin_brtab\n", asm_out_file); + for (idx = 0; idx < vlen; idx++) + { + ASM_OUTPUT_ADDR_DIFF_ELT + (asm_out_file, + body, + CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), + CODE_LABEL_NUMBER (base)); + } + if (TARGET_GAS) + fputs ("\t.end_brtab\n", asm_out_file); +} + #include "gt-pa.h" diff --git a/gcc-4.9/gcc/config/pa/pa.h b/gcc-4.9/gcc/config/pa/pa.h index ac3f0ebe7..f6c9751a2 100644 --- a/gcc-4.9/gcc/config/pa/pa.h +++ b/gcc-4.9/gcc/config/pa/pa.h @@ -1193,6 +1193,16 @@ do { \ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL) +/* This is how to output an absolute case-vector. */ + +#define ASM_OUTPUT_ADDR_VEC(LAB,BODY) \ + pa_output_addr_vec ((LAB),(BODY)) + +/* This is how to output a relative case-vector. */ + +#define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,BODY) \ + pa_output_addr_diff_vec ((LAB),(BODY)) + /* This is how to output an assembler line that says to advance the location counter to a multiple of 2**LOG bytes. */ diff --git a/gcc-4.9/gcc/config/pa/pa.md b/gcc-4.9/gcc/config/pa/pa.md index e55d0b86b..a9421ac2e 100644 --- a/gcc-4.9/gcc/config/pa/pa.md +++ b/gcc-4.9/gcc/config/pa/pa.md @@ -8508,36 +8508,6 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" [(set_attr "type" "move") (set_attr "length" "4")]) -;; These are just placeholders so we know where branch tables -;; begin and end. -(define_insn "begin_brtab" - [(const_int 1)] - "" - "* -{ - /* Only GAS actually supports this pseudo-op. */ - if (TARGET_GAS) - return \".begin_brtab\"; - else - return \"\"; -}" - [(set_attr "type" "move") - (set_attr "length" "0")]) - -(define_insn "end_brtab" - [(const_int 2)] - "" - "* -{ - /* Only GAS actually supports this pseudo-op. */ - if (TARGET_GAS) - return \".end_brtab\"; - else - return \"\"; -}" - [(set_attr "type" "move") - (set_attr "length" "0")]) - ;;; EH does longjmp's from and within the data section. Thus, ;;; an interspace branch is required for the longjmp implementation. ;;; Registers r1 and r2 are used as scratch registers for the jump diff --git a/gcc-4.9/gcc/config/rs6000/constraints.md b/gcc-4.9/gcc/config/rs6000/constraints.md index 9d6a3bbe7..78a3ff0d2 100644 --- a/gcc-4.9/gcc/config/rs6000/constraints.md +++ b/gcc-4.9/gcc/config/rs6000/constraints.md @@ -68,6 +68,20 @@ (define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" "If -mmfpgpr was used, a floating point register or NO_REGS.") +(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" + "Floating point register if direct moves are available, or NO_REGS.") + +;; At present, DImode is not allowed in the Altivec registers. If in the +;; future it is allowed, wi/wj can be set to VSX_REGS instead of FLOAT_REGS. +(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" + "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") + +(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" + "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") + +(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" + "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") + (define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") @@ -101,7 +115,7 @@ "Floating point register if the STFIWX instruction is enabled or NO_REGS.") (define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" - "VSX vector register to hold scalar float values or NO_REGS.") + "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.c b/gcc-4.9/gcc/config/rs6000/rs6000.c index d7cbc6cde..28ccf86df 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.c +++ b/gcc-4.9/gcc/config/rs6000/rs6000.c @@ -388,6 +388,7 @@ struct rs6000_reg_addr { enum insn_code reload_gpr_vsx; /* INSN to move from GPR to VSX. */ enum insn_code reload_vsx_gpr; /* INSN to move from VSX to GPR. */ addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks. */ + bool scalar_in_vmx_p; /* Scalar value can go in VMX. */ }; static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES]; @@ -1221,7 +1222,12 @@ char rs6000_reg_names[][8] = /* Soft frame pointer. */ "sfp", /* HTM SPR registers. */ - "tfhar", "tfiar", "texasr" + "tfhar", "tfiar", "texasr", + /* SPE High registers. */ + "0", "1", "2", "3", "4", "5", "6", "7", + "8", "9", "10", "11", "12", "13", "14", "15", + "16", "17", "18", "19", "20", "21", "22", "23", + "24", "25", "26", "27", "28", "29", "30", "31" }; #ifdef TARGET_REGNAMES @@ -1249,7 +1255,12 @@ static const char alt_reg_names[][8] = /* Soft frame pointer. */ "sfp", /* HTM SPR registers. */ - "tfhar", "tfiar", "texasr" + "tfhar", "tfiar", "texasr", + /* SPE High registers. */ + "%rh0", "%rh1", "%rh2", "%rh3", "%rh4", "%rh5", "%rh6", "%rh7", + "%rh8", "%rh9", "%rh10", "%r11", "%rh12", "%rh13", "%rh14", "%rh15", + "%rh16", "%rh17", "%rh18", "%rh19", "%rh20", "%rh21", "%rh22", "%rh23", + "%rh24", "%rh25", "%rh26", "%rh27", "%rh28", "%rh29", "%rh30", "%rh31" }; #endif @@ -1723,8 +1734,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) asked for it. */ if (TARGET_VSX && VSX_REGNO_P (regno) && (VECTOR_MEM_VSX_P (mode) - || (TARGET_VSX_SCALAR_FLOAT && mode == SFmode) - || (TARGET_VSX_SCALAR_DOUBLE && (mode == DFmode || mode == DImode)) + || reg_addr[mode].scalar_in_vmx_p || (TARGET_VSX_TIMODE && mode == TImode) || (TARGET_VADDUQM && mode == V1TImode))) { @@ -1733,10 +1743,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode) if (ALTIVEC_REGNO_P (regno)) { - if (mode == SFmode && !TARGET_UPPER_REGS_SF) - return 0; - - if ((mode == DFmode || mode == DImode) && !TARGET_UPPER_REGS_DF) + if (GET_MODE_SIZE (mode) != 16 && !reg_addr[mode].scalar_in_vmx_p) return 0; return ALTIVEC_REGNO_P (last_regno); @@ -1916,14 +1923,16 @@ rs6000_debug_print_mode (ssize_t m) if (rs6000_vector_unit[m] != VECTOR_NONE || rs6000_vector_mem[m] != VECTOR_NONE || (reg_addr[m].reload_store != CODE_FOR_nothing) - || (reg_addr[m].reload_load != CODE_FOR_nothing)) + || (reg_addr[m].reload_load != CODE_FOR_nothing) + || reg_addr[m].scalar_in_vmx_p) { fprintf (stderr, - " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c", + " Vector-arith=%-10s Vector-mem=%-10s Reload=%c%c Upper=%c", rs6000_debug_vector_unit (rs6000_vector_unit[m]), rs6000_debug_vector_unit (rs6000_vector_mem[m]), (reg_addr[m].reload_store != CODE_FOR_nothing) ? 's' : '*', - (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*'); + (reg_addr[m].reload_load != CODE_FOR_nothing) ? 'l' : '*', + (reg_addr[m].scalar_in_vmx_p) ? 'y' : 'n'); } fputs ("\n", stderr); @@ -2040,6 +2049,10 @@ rs6000_debug_reg_global (void) "wd reg_class = %s\n" "wf reg_class = %s\n" "wg reg_class = %s\n" + "wh reg_class = %s\n" + "wi reg_class = %s\n" + "wj reg_class = %s\n" + "wk reg_class = %s\n" "wl reg_class = %s\n" "wm reg_class = %s\n" "wr reg_class = %s\n" @@ -2059,6 +2072,10 @@ rs6000_debug_reg_global (void) reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wd]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wf]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wg]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wh]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wi]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wj]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wk]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wl]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wm]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]], @@ -2347,6 +2364,8 @@ rs6000_setup_reg_addr_masks (void) for (m = 0; m < NUM_MACHINE_MODES; ++m) { + enum machine_mode m2 = (enum machine_mode)m; + /* SDmode is special in that we want to access it only via REG+REG addressing on power7 and above, since we want to use the LFIWZX and STFIWZX instructions to load it. */ @@ -2381,13 +2400,12 @@ rs6000_setup_reg_addr_masks (void) if (TARGET_UPDATE && (rc == RELOAD_REG_GPR || rc == RELOAD_REG_FPR) - && GET_MODE_SIZE (m) <= 8 - && !VECTOR_MODE_P (m) - && !COMPLEX_MODE_P (m) + && GET_MODE_SIZE (m2) <= 8 + && !VECTOR_MODE_P (m2) + && !COMPLEX_MODE_P (m2) && !indexed_only_p - && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m) == 8) - && !(m == DFmode && TARGET_UPPER_REGS_DF) - && !(m == SFmode && TARGET_UPPER_REGS_SF)) + && !(TARGET_E500_DOUBLE && GET_MODE_SIZE (m2) == 8) + && !reg_addr[m2].scalar_in_vmx_p) { addr_mask |= RELOAD_REG_PRE_INCDEC; @@ -2618,37 +2636,44 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) f - Register class to use with traditional SFmode instructions. v - Altivec register. wa - Any VSX register. + wc - Reserved to represent individual CR bits (used in LLVM). wd - Preferred register class for V2DFmode. wf - Preferred register class for V4SFmode. wg - Float register for power6x move insns. + wh - FP register for direct move instructions. + wi - FP or VSX register to hold 64-bit integers for VSX insns. + wj - FP or VSX register to hold 64-bit integers for direct moves. + wk - FP or VSX register to hold 64-bit doubles for direct moves. wl - Float register if we can do 32-bit signed int loads. wm - VSX register for ISA 2.07 direct move operations. + wn - always NO_REGS. wr - GPR if 64-bit mode is permitted. ws - Register class to do ISA 2.06 DF operations. + wt - VSX register for TImode in VSX registers. wu - Altivec register for ISA 2.07 VSX SF/SI load/stores. wv - Altivec register for ISA 2.06 VSX DF/DI load/stores. - wt - VSX register for TImode in VSX registers. ww - Register class to do SF conversions in with VSX operations. wx - Float register if we can do 32-bit int stores. wy - Register class to do ISA 2.07 SF operations. wz - Float register if we can do 32-bit unsigned int loads. */ if (TARGET_HARD_FLOAT && TARGET_FPRS) - rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_f] = FLOAT_REGS; /* SFmode */ if (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) - rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_d] = FLOAT_REGS; /* DFmode */ if (TARGET_VSX) { rs6000_constraints[RS6000_CONSTRAINT_wa] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; - rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wd] = VSX_REGS; /* V2DFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wf] = VSX_REGS; /* V4SFmode */ + rs6000_constraints[RS6000_CONSTRAINT_wi] = FLOAT_REGS; /* DImode */ if (TARGET_VSX_TIMODE) - rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wt] = VSX_REGS; /* TImode */ - if (TARGET_UPPER_REGS_DF) + if (TARGET_UPPER_REGS_DF) /* DFmode */ { rs6000_constraints[RS6000_CONSTRAINT_ws] = VSX_REGS; rs6000_constraints[RS6000_CONSTRAINT_wv] = ALTIVEC_REGS; @@ -2662,19 +2687,26 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) if (TARGET_ALTIVEC) rs6000_constraints[RS6000_CONSTRAINT_v] = ALTIVEC_REGS; - if (TARGET_MFPGPR) + if (TARGET_MFPGPR) /* DFmode */ rs6000_constraints[RS6000_CONSTRAINT_wg] = FLOAT_REGS; if (TARGET_LFIWAX) - rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wl] = FLOAT_REGS; /* DImode */ if (TARGET_DIRECT_MOVE) - rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; + { + rs6000_constraints[RS6000_CONSTRAINT_wh] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wj] /* DImode */ + = rs6000_constraints[RS6000_CONSTRAINT_wi]; + rs6000_constraints[RS6000_CONSTRAINT_wk] /* DFmode */ + = rs6000_constraints[RS6000_CONSTRAINT_ws]; + rs6000_constraints[RS6000_CONSTRAINT_wm] = VSX_REGS; + } if (TARGET_POWERPC64) rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; - if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) + if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */ { rs6000_constraints[RS6000_CONSTRAINT_wu] = ALTIVEC_REGS; rs6000_constraints[RS6000_CONSTRAINT_wy] = VSX_REGS; @@ -2689,10 +2721,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) rs6000_constraints[RS6000_CONSTRAINT_ww] = FLOAT_REGS; if (TARGET_STFIWX) - rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wx] = FLOAT_REGS; /* DImode */ if (TARGET_LFIWZX) - rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wz] = FLOAT_REGS; /* DImode */ /* Set up the reload helper and direct move functions. */ if (TARGET_VSX || TARGET_ALTIVEC) @@ -2715,10 +2747,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_di_load; if (TARGET_VSX && TARGET_UPPER_REGS_DF) { - reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; - reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; - reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; - reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_di_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_di_load; + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_di_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_di_load; } if (TARGET_P8_VECTOR) { @@ -2726,6 +2759,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_di_load; reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_di_store; reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_di_load; + if (TARGET_UPPER_REGS_SF) + reg_addr[SFmode].scalar_in_vmx_p = true; } if (TARGET_VSX_TIMODE) { @@ -2782,10 +2817,11 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[V2DFmode].reload_load = CODE_FOR_reload_v2df_si_load; if (TARGET_VSX && TARGET_UPPER_REGS_DF) { - reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; - reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; - reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; - reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; + reg_addr[DFmode].reload_store = CODE_FOR_reload_df_si_store; + reg_addr[DFmode].reload_load = CODE_FOR_reload_df_si_load; + reg_addr[DFmode].scalar_in_vmx_p = true; + reg_addr[DDmode].reload_store = CODE_FOR_reload_dd_si_store; + reg_addr[DDmode].reload_load = CODE_FOR_reload_dd_si_load; } if (TARGET_P8_VECTOR) { @@ -2793,6 +2829,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_addr[SFmode].reload_load = CODE_FOR_reload_sf_si_load; reg_addr[SDmode].reload_store = CODE_FOR_reload_sd_si_store; reg_addr[SDmode].reload_load = CODE_FOR_reload_sd_si_load; + if (TARGET_UPPER_REGS_SF) + reg_addr[SFmode].scalar_in_vmx_p = true; } if (TARGET_VSX_TIMODE) { @@ -2833,6 +2871,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) for (m = 0; m < NUM_MACHINE_MODES; ++m) { + enum machine_mode m2 = (enum machine_mode)m; int reg_size2 = reg_size; /* TFmode/TDmode always takes 2 registers, even in VSX. */ @@ -2841,7 +2880,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_size2 = UNITS_PER_FP_WORD; rs6000_class_max_nregs[m][c] - = (GET_MODE_SIZE (m) + reg_size2 - 1) / reg_size2; + = (GET_MODE_SIZE (m2) + reg_size2 - 1) / reg_size2; } } @@ -17167,7 +17206,14 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) prefer Altivec loads.. */ if (rclass == VSX_REGS) { - if (GET_MODE_SIZE (mode) <= 8) + if (MEM_P (x) && reg_addr[mode].scalar_in_vmx_p) + { + rtx addr = XEXP (x, 0); + if (rs6000_legitimate_offset_address_p (mode, addr, false, true) + || legitimate_lo_sum_address_p (mode, addr, false)) + return FLOAT_REGS; + } + else if (GET_MODE_SIZE (mode) <= 8 && !reg_addr[mode].scalar_in_vmx_p) return FLOAT_REGS; if (VECTOR_UNIT_ALTIVEC_P (mode) || VECTOR_MEM_ALTIVEC_P (mode) @@ -31171,13 +31217,13 @@ rs6000_dwarf_register_span (rtx reg) { if (BYTES_BIG_ENDIAN) { - parts[2 * i] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); parts[2 * i + 1] = gen_rtx_REG (SImode, regno); } else { parts[2 * i] = gen_rtx_REG (SImode, regno); - parts[2 * i + 1] = gen_rtx_REG (SImode, regno + 1200); + parts[2 * i + 1] = gen_rtx_REG (SImode, regno + FIRST_SPE_HIGH_REGNO); } } @@ -31197,11 +31243,11 @@ rs6000_init_dwarf_reg_sizes_extra (tree address) rtx mem = gen_rtx_MEM (BLKmode, addr); rtx value = gen_int_mode (4, mode); - for (i = 1201; i < 1232; i++) + for (i = FIRST_SPE_HIGH_REGNO; i < LAST_SPE_HIGH_REGNO+1; i++) { - int column = DWARF_REG_TO_UNWIND_COLUMN (i); - HOST_WIDE_INT offset - = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + int column = DWARF_REG_TO_UNWIND_COLUMN + (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); + HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); emit_move_insn (adjust_address (mem, mode, offset), value); } @@ -31220,9 +31266,9 @@ rs6000_init_dwarf_reg_sizes_extra (tree address) for (i = FIRST_ALTIVEC_REGNO; i < LAST_ALTIVEC_REGNO+1; i++) { - int column = DWARF_REG_TO_UNWIND_COLUMN (i); - HOST_WIDE_INT offset - = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode); + int column = DWARF_REG_TO_UNWIND_COLUMN + (DWARF2_FRAME_REG_OUT (DWARF_FRAME_REGNUM (i), true)); + HOST_WIDE_INT offset = column * GET_MODE_SIZE (mode); emit_move_insn (adjust_address (mem, mode, offset), value); } @@ -31254,9 +31300,8 @@ rs6000_dbx_register_number (unsigned int regno) return 99; if (regno == SPEFSCR_REGNO) return 612; - /* SPE high reg number. We get these values of regno from - rs6000_dwarf_register_span. */ - gcc_assert (regno >= 1200 && regno < 1232); + if (SPE_HIGH_REGNO_P (regno)) + return regno - FIRST_SPE_HIGH_REGNO + 1200; return regno; } diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.h b/gcc-4.9/gcc/config/rs6000/rs6000.h index 2b5d033f8..f36386770 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.h +++ b/gcc-4.9/gcc/config/rs6000/rs6000.h @@ -930,35 +930,36 @@ enum data_align { align_abi, align_opt, align_both }; The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ -#define FIRST_PSEUDO_REGISTER 117 +#define FIRST_PSEUDO_REGISTER 149 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 -/* Add 32 dwarf columns for synthetic SPE registers. */ -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) +/* True if register is an SPE High register. */ +#define SPE_HIGH_REGNO_P(N) \ + ((N) >= FIRST_SPE_HIGH_REGNO && (N) <= LAST_SPE_HIGH_REGNO) + +/* SPE high registers added as hard regs. + The sfp register and 3 HTM registers + aren't included in DWARF_FRAME_REGISTERS. */ +#define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 4) /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame register numbering need not be the same as the debug info numbering, - we choose to number these regs for eh_frame at 1200 too. This allows - future versions of the rs6000 backend to add hard registers and - continue to use the gcc hard register numbering for eh_frame. If the - extra SPE registers in eh_frame were numbered starting from the - current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER - changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to - avoid invalidating older SPE eh_frame info. + we choose to number these regs for eh_frame at 1200 too. We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) + ((r) >= 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) /* Use gcc hard register numbering for eh_frame. */ -#define DWARF_FRAME_REGNUM(REGNO) (REGNO) +#define DWARF_FRAME_REGNUM(REGNO) \ + (SPE_HIGH_REGNO_P (REGNO) ? ((REGNO) - FIRST_SPE_HIGH_REGNO + 1200) : (REGNO)) /* Map register numbers held in the call frame info that gcc has collected using DWARF_FRAME_REGNUM to those that should be output in @@ -992,7 +993,10 @@ enum data_align { align_abi, align_opt, align_both }; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* 1 for registers not available across function calls. @@ -1012,7 +1016,10 @@ enum data_align { align_abi, align_opt, align_both }; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1, 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1, \ + /* SPE High registers. */ \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -1031,7 +1038,10 @@ enum data_align { align_abi, align_opt, align_both }; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ - , 0, 0, 0, 0, 0, 0 \ + , 0, 0, 0, 0, 0, 0, \ + /* SPE High registers. */ \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -1114,7 +1124,10 @@ enum data_align { align_abi, align_opt, align_both }; 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ - 111, 112, 113, 114, 115, 116 \ + 111, 112, 113, 114, 115, 116, \ + 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, \ + 129, 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, \ + 141, 142, 143, 144, 145, 146, 147, 148 \ } /* True if register is floating-point. */ @@ -1349,6 +1362,7 @@ enum reg_class CR_REGS, NON_FLOAT_REGS, CA_REGS, + SPE_HIGH_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -1380,6 +1394,7 @@ enum reg_class "CR_REGS", \ "NON_FLOAT_REGS", \ "CA_REGS", \ + "SPE_HIGH_REGS", \ "ALL_REGS" \ } @@ -1387,30 +1402,54 @@ enum reg_class This is an initializer for a vector of HARD_REG_SET of length N_REG_CLASSES. */ -#define REG_CLASS_CONTENTS \ -{ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ - { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ - { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ - { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \ - { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ - { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ - { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ - { 0x00000000, 0x00000000, 0x00000006, 0x00002000 }, /* SPECIAL_REGS */ \ - { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ - { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ - { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ - { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ - { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ - { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \ +#define REG_CLASS_CONTENTS \ +{ \ + /* NO_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ + /* BASE_REGS. */ \ + { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + /* GENERAL_REGS. */ \ + { 0xffffffff, 0x00000000, 0x00000008, 0x00020000, 0x00000000 }, \ + /* FLOAT_REGS. */ \ + { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000 }, \ + /* ALTIVEC_REGS. */ \ + { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff, 0x00000000 }, \ + /* VSX_REGS. */ \ + { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff, 0x00000000 }, \ + /* VRSAVE_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00002000, 0x00000000 }, \ + /* VSCR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00004000, 0x00000000 }, \ + /* SPE_ACC_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00008000, 0x00000000 }, \ + /* SPEFSCR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00010000, 0x00000000 }, \ + /* SPR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00040000, 0x00000000 }, \ + /* NON_SPECIAL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000, 0x00000000 }, \ + /* LINK_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000 }, \ + /* CTR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000 }, \ + /* LINK_OR_CTR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00000000, 0x00000000 }, \ + /* SPECIAL_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000006, 0x00002000, 0x00000000 }, \ + /* SPEC_OR_GEN_REGS. */ \ + { 0xffffffff, 0x00000000, 0x0000000e, 0x00022000, 0x00000000 }, \ + /* CR0_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000010, 0x00000000, 0x00000000 }, \ + /* CR_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000, 0x00000000 }, \ + /* NON_FLOAT_REGS. */ \ + { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000, 0x00000000 }, \ + /* CA_REGS. */ \ + { 0x00000000, 0x00000000, 0x00001000, 0x00000000, 0x00000000 }, \ + /* SPE_HIGH_REGS. */ \ + { 0x00000000, 0x00000000, 0x00000000, 0xffe00000, 0x001fffff }, \ + /* ALL_REGS. */ \ + { 0xffffffff, 0xffffffff, 0xfffffffe, 0xffe7ffff, 0x001fffff } \ } /* The same information, inverted: @@ -1439,6 +1478,10 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ + RS6000_CONSTRAINT_wh, /* FPR register for direct moves. */ + RS6000_CONSTRAINT_wi, /* FPR/VSX register to hold DImode */ + RS6000_CONSTRAINT_wj, /* FPR/VSX register for DImode direct moves. */ + RS6000_CONSTRAINT_wk, /* FPR/VSX register for DFmode direct moves. */ RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ RS6000_CONSTRAINT_wm, /* VSX register for direct move */ RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ @@ -1463,6 +1506,9 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; #define VSX_REG_CLASS_P(CLASS) \ ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) +/* Return whether a given register class targets general purpose registers. */ +#define GPR_REG_CLASS_P(CLASS) ((CLASS) == GENERAL_REGS || (CLASS) == BASE_REGS) + /* Given an rtx X being reloaded into a reg required to be in class CLASS, return the class of reg to actually use. In general this is just CLASS; but on some machines @@ -2349,6 +2395,39 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ &rs6000_reg_names[114][0], /* tfhar */ \ &rs6000_reg_names[115][0], /* tfiar */ \ &rs6000_reg_names[116][0], /* texasr */ \ + \ + &rs6000_reg_names[117][0], /* SPE rh0. */ \ + &rs6000_reg_names[118][0], /* SPE rh1. */ \ + &rs6000_reg_names[119][0], /* SPE rh2. */ \ + &rs6000_reg_names[120][0], /* SPE rh3. */ \ + &rs6000_reg_names[121][0], /* SPE rh4. */ \ + &rs6000_reg_names[122][0], /* SPE rh5. */ \ + &rs6000_reg_names[123][0], /* SPE rh6. */ \ + &rs6000_reg_names[124][0], /* SPE rh7. */ \ + &rs6000_reg_names[125][0], /* SPE rh8. */ \ + &rs6000_reg_names[126][0], /* SPE rh9. */ \ + &rs6000_reg_names[127][0], /* SPE rh10. */ \ + &rs6000_reg_names[128][0], /* SPE rh11. */ \ + &rs6000_reg_names[129][0], /* SPE rh12. */ \ + &rs6000_reg_names[130][0], /* SPE rh13. */ \ + &rs6000_reg_names[131][0], /* SPE rh14. */ \ + &rs6000_reg_names[132][0], /* SPE rh15. */ \ + &rs6000_reg_names[133][0], /* SPE rh16. */ \ + &rs6000_reg_names[134][0], /* SPE rh17. */ \ + &rs6000_reg_names[135][0], /* SPE rh18. */ \ + &rs6000_reg_names[136][0], /* SPE rh19. */ \ + &rs6000_reg_names[137][0], /* SPE rh20. */ \ + &rs6000_reg_names[138][0], /* SPE rh21. */ \ + &rs6000_reg_names[139][0], /* SPE rh22. */ \ + &rs6000_reg_names[140][0], /* SPE rh22. */ \ + &rs6000_reg_names[141][0], /* SPE rh24. */ \ + &rs6000_reg_names[142][0], /* SPE rh25. */ \ + &rs6000_reg_names[143][0], /* SPE rh26. */ \ + &rs6000_reg_names[144][0], /* SPE rh27. */ \ + &rs6000_reg_names[145][0], /* SPE rh28. */ \ + &rs6000_reg_names[146][0], /* SPE rh29. */ \ + &rs6000_reg_names[147][0], /* SPE rh30. */ \ + &rs6000_reg_names[148][0], /* SPE rh31. */ \ } /* Table of additional register names to use in user input. */ @@ -2404,7 +2483,17 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ /* Transactional Memory Facility (HTM) Registers. */ \ - {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} } + {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116}, \ + /* SPE high registers. */ \ + {"rh0", 117}, {"rh1", 118}, {"rh2", 119}, {"rh3", 120}, \ + {"rh4", 121}, {"rh5", 122}, {"rh6", 123}, {"rh7", 124}, \ + {"rh8", 125}, {"rh9", 126}, {"rh10", 127}, {"rh11", 128}, \ + {"rh12", 129}, {"rh13", 130}, {"rh14", 131}, {"rh15", 132}, \ + {"rh16", 133}, {"rh17", 134}, {"rh18", 135}, {"rh19", 136}, \ + {"rh20", 137}, {"rh21", 138}, {"rh22", 139}, {"rh23", 140}, \ + {"rh24", 141}, {"rh25", 142}, {"rh26", 143}, {"rh27", 144}, \ + {"rh28", 145}, {"rh29", 146}, {"rh30", 147}, {"rh31", 148}, \ +} /* This is how to output an element of a case-vector that is relative. */ diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.md b/gcc-4.9/gcc/config/rs6000/rs6000.md index 26d0d1530..d078491e1 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.md +++ b/gcc-4.9/gcc/config/rs6000/rs6000.md @@ -56,6 +56,8 @@ (TFHAR_REGNO 114) (TFIAR_REGNO 115) (TEXASR_REGNO 116) + (FIRST_SPE_HIGH_REGNO 117) + (LAST_SPE_HIGH_REGNO 148) ]) ;; @@ -326,7 +328,7 @@ (define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")]) ; Definitions for 32-bit fpr direct move -(define_mode_attr f32_dm [(SF "wn") (SD "wm")]) +(define_mode_attr f32_dm [(SF "wn") (SD "wh")]) ; These modes do not fit in integer registers in 32-bit mode. ; but on e500v2, the gpr are 64 bit registers @@ -575,7 +577,7 @@ "") (define_insn "*zero_extendsidi2_lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] "TARGET_POWERPC64 && TARGET_LFIWZX" "@ @@ -745,7 +747,7 @@ "") (define_insn "*extendsidi2_lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu") (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))] "TARGET_POWERPC64 && TARGET_LFIWAX" "@ @@ -5623,7 +5625,7 @@ ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] UNSPEC_LFIWAX))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" @@ -5703,7 +5705,7 @@ (set_attr "type" "fpload")]) (define_insn "lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj") (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] UNSPEC_LFIWZX))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX" @@ -9457,8 +9459,8 @@ ; ld/std require word-aligned displacements -> 'Y' constraint. ; List Y->r and r->Y before r->r for reload. (define_insn "*mov_hardfloat64" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm") - (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wk") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wk,r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -10237,8 +10239,8 @@ { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) (define_insn "*movdi_internal64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi") + (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -10258,7 +10260,8 @@ mftgpr %0,%1 mffgpr %0,%1 mfvsrd %0,%x1 - mtvsrd %x0,%1" + mtvsrd %x0,%1 + xxlxor %x0,%x0,%x0" [(set_attr_alternative "type" [(if_then_else (match_test "update_indexed_address_mem (operands[0], VOIDmode)") @@ -10299,8 +10302,9 @@ (const_string "mftgpr") (const_string "mffgpr") (const_string "mftgpr") - (const_string "mffgpr")]) - (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")]) + (const_string "mffgpr") + (const_string "vecsimple")]) + (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")]) ;; Generate all one-bits and clear left or right. ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. diff --git a/gcc-4.9/gcc/config/rs6000/vsx.md b/gcc-4.9/gcc/config/rs6000/vsx.md index 6d20eab11..2cf5e7a94 100644 --- a/gcc-4.9/gcc/config/rs6000/vsx.md +++ b/gcc-4.9/gcc/config/rs6000/vsx.md @@ -86,19 +86,26 @@ (V4SF "wf") (V2DI "wd") (V2DF "wd") + (DI "wi") (DF "ws") - (SF "d") + (SF "ww") (V1TI "v") (TI "wt")]) -;; Map the register class used for float<->int conversions +;; Map the register class used for float<->int conversions (floating point side) +;; VSr2 is the preferred register class, VSr3 is any register class that will +;; hold the data (define_mode_attr VSr2 [(V2DF "wd") (V4SF "wf") - (DF "ws")]) + (DF "ws") + (SF "ww") + (DI "wi")]) (define_mode_attr VSr3 [(V2DF "wa") (V4SF "wa") - (DF "ws")]) + (DF "ws") + (SF "ww") + (DI "wi")]) ;; Map the register class for sp<->dp float conversions, destination (define_mode_attr VSr4 [(SF "ws") @@ -106,12 +113,27 @@ (V2DF "wd") (V4SF "v")]) -;; Map the register class for sp<->dp float conversions, destination +;; Map the register class for sp<->dp float conversions, source (define_mode_attr VSr5 [(SF "ws") (DF "f") (V2DF "v") (V4SF "wd")]) +;; The VSX register class that a type can occupy, even if it is not the +;; preferred register class (VSr is the preferred register class that will get +;; allocated first). +(define_mode_attr VSa [(V16QI "wa") + (V8HI "wa") + (V4SI "wa") + (V4SF "wa") + (V2DI "wa") + (V2DF "wa") + (DI "wi") + (DF "ws") + (SF "ww") + (V1TI "wa") + (TI "wt")]) + ;; Same size integer type for floating point data (define_mode_attr VSi [(V4SF "v4si") (V2DF "v2di") @@ -207,6 +229,16 @@ (V2DF "V4DF") (V1TI "V2TI")]) +;; Map register class for 64-bit element in 128-bit vector for direct moves +;; to/from gprs +(define_mode_attr VS_64dm [(V2DF "wk") + (V2DI "wj")]) + +;; Map register class for 64-bit element in 128-bit vector for normal register +;; to register moves +(define_mode_attr VS_64reg [(V2DF "ws") + (V2DI "wi")]) + ;; Constants for creating unspecs (define_c_enum "unspec" [UNSPEC_VSX_CONCAT @@ -235,7 +267,7 @@ ;; The patterns for LE permuted loads and stores come before the general ;; VSX moves so they match first. (define_insn_and_split "*vsx_le_perm_load_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") (match_operand:VSX_LE 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" @@ -258,7 +290,7 @@ (set_attr "length" "8")]) (define_insn_and_split "*vsx_le_perm_load_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") (match_operand:VSX_W 1 "memory_operand" "Z"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" @@ -350,7 +382,7 @@ (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") - (match_operand:VSX_LE 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_LE 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" [(set_attr "type" "vecstore") @@ -395,7 +427,7 @@ (define_insn "*vsx_le_perm_store_" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") - (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] + (match_operand:VSX_W 1 "vsx_register_operand" "+"))] "!BYTES_BIG_ENDIAN && TARGET_VSX" "#" [(set_attr "type" "vecstore") @@ -585,8 +617,8 @@ (define_insn "*vsx_mov" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,,,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,,?wa,*r,v,wZ, v") - (match_operand:VSX_M 1 "input_operand" ",Z,,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] + [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,,,?Z,?,?,wQ,?&r,??Y,??r,??r,,?,*r,v,wZ, v") + (match_operand:VSX_M 1 "input_operand" ",Z,,,Z,,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] "VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" @@ -688,36 +720,36 @@ ;; instructions are now combined with the insn for the traditional floating ;; point unit. (define_insn "*vsx_add3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvadd %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_sub3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvsub %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_mul3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvmul %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_div3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvdiv %x0,%x1,%x2" [(set_attr "type" "") @@ -753,8 +785,8 @@ (define_insn "*vsx_tdiv3_internal" [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x") - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" ",") + (match_operand:VSX_B 2 "vsx_register_operand" ",")] UNSPEC_VSX_TDIV))] "VECTOR_UNIT_VSX_P (mode)" "xtdiv %0,%x1,%x2" @@ -762,8 +794,8 @@ (set_attr "fp_type" "")]) (define_insn "vsx_fre2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",")] UNSPEC_FRES))] "VECTOR_UNIT_VSX_P (mode)" "xvre %x0,%x1" @@ -771,60 +803,60 @@ (set_attr "fp_type" "")]) (define_insn "*vsx_neg2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvneg %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_abs2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvabs %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_nabs2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") (neg:VSX_F (abs:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" ",wa"))))] + (match_operand:VSX_F 1 "vsx_register_operand" ","))))] "VECTOR_UNIT_VSX_P (mode)" "xvnabs %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_smax3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvmax %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_smin3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvmin %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_sqrt2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvsqrt %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_rsqrte2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",")] UNSPEC_RSQRT))] "VECTOR_UNIT_VSX_P (mode)" "xvrsqrte %x0,%x1" @@ -859,7 +891,7 @@ (define_insn "*vsx_tsqrt2_internal" [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x") - (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" ",")] UNSPEC_VSX_TSQRT))] "VECTOR_UNIT_VSX_P (mode)" "xtsqrt %0,%x1" @@ -901,12 +933,12 @@ [(set_attr "type" "vecdouble")]) (define_insn "*vsx_fms4" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,,?wa,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,,?,?") (fma:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" "%,,wa,wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",0,wa,0") + (match_operand:VSX_F 1 "vsx_register_operand" "%,,,") + (match_operand:VSX_F 2 "vsx_register_operand" ",0,,0") (neg:VSX_F - (match_operand:VSX_F 3 "vsx_register_operand" "0,,0,wa"))))] + (match_operand:VSX_F 3 "vsx_register_operand" "0,,0,"))))] "VECTOR_UNIT_VSX_P (mode)" "@ xvmsuba %x0,%x1,%x2 @@ -916,12 +948,12 @@ [(set_attr "type" "")]) (define_insn "*vsx_nfma4" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,,?wa,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,,?,?") (neg:VSX_F (fma:VSX_F - (match_operand:VSX_F 1 "vsx_register_operand" ",,wa,wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",0,wa,0") - (match_operand:VSX_F 3 "vsx_register_operand" "0,,0,wa"))))] + (match_operand:VSX_F 1 "vsx_register_operand" ",,,") + (match_operand:VSX_F 2 "vsx_register_operand" ",0,,0") + (match_operand:VSX_F 3 "vsx_register_operand" "0,,0,"))))] "VECTOR_UNIT_VSX_P (mode)" "@ xvnmadda %x0,%x1,%x2 @@ -966,27 +998,27 @@ ;; Vector conditional expressions (no scalar version for these instructions) (define_insn "vsx_eq" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (eq:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvcmpeq %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_gt" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (gt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvcmpgt %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_ge" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (ge:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvcmpge %x0,%x1,%x2" [(set_attr "type" "") @@ -997,10 +1029,10 @@ (define_insn "*vsx_eq__p" [(set (reg:CC 74) (unspec:CC - [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",?wa"))] + [(eq:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?") + (match_operand:VSX_F 2 "vsx_register_operand" ",?"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") (eq:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (mode)" @@ -1010,10 +1042,10 @@ (define_insn "*vsx_gt__p" [(set (reg:CC 74) (unspec:CC - [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",?wa"))] + [(gt:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?") + (match_operand:VSX_F 2 "vsx_register_operand" ",?"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") (gt:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (mode)" @@ -1023,10 +1055,10 @@ (define_insn "*vsx_ge__p" [(set (reg:CC 74) (unspec:CC - [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",?wa"))] + [(ge:CC (match_operand:VSX_F 1 "vsx_register_operand" ",?") + (match_operand:VSX_F 2 "vsx_register_operand" ",?"))] UNSPEC_PREDICATE)) - (set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") (ge:VSX_F (match_dup 1) (match_dup 2)))] "VECTOR_UNIT_VSX_P (mode)" @@ -1035,33 +1067,33 @@ ;; Vector select (define_insn "*vsx_xxsel" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?") (if_then_else:VSX_L - (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" ",wa") + (ne:CC (match_operand:VSX_L 1 "vsx_register_operand" ",") (match_operand:VSX_L 4 "zero_constant" "")) - (match_operand:VSX_L 2 "vsx_register_operand" ",wa") - (match_operand:VSX_L 3 "vsx_register_operand" ",wa")))] + (match_operand:VSX_L 2 "vsx_register_operand" ",") + (match_operand:VSX_L 3 "vsx_register_operand" ",")))] "VECTOR_MEM_VSX_P (mode)" "xxsel %x0,%x3,%x2,%x1" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxsel_uns" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?") (if_then_else:VSX_L - (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" ",wa") + (ne:CCUNS (match_operand:VSX_L 1 "vsx_register_operand" ",") (match_operand:VSX_L 4 "zero_constant" "")) - (match_operand:VSX_L 2 "vsx_register_operand" ",wa") - (match_operand:VSX_L 3 "vsx_register_operand" ",wa")))] + (match_operand:VSX_L 2 "vsx_register_operand" ",") + (match_operand:VSX_L 3 "vsx_register_operand" ",")))] "VECTOR_MEM_VSX_P (mode)" "xxsel %x0,%x3,%x2,%x1" [(set_attr "type" "vecperm")]) ;; Copy sign (define_insn "vsx_copysign3" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") (unspec:VSX_F - [(match_operand:VSX_F 1 "vsx_register_operand" ",wa") - (match_operand:VSX_F 2 "vsx_register_operand" ",wa")] + [(match_operand:VSX_F 1 "vsx_register_operand" ",") + (match_operand:VSX_F 2 "vsx_register_operand" ",")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_VSX_P (mode)" "xvcpsgn %x0,%x2,%x1" @@ -1074,7 +1106,7 @@ ;; in rs6000.md so don't test VECTOR_UNIT_VSX_P, just test against VSX. ;; Don't use vsx_register_operand here, use gpc_reg_operand to match rs6000.md. (define_insn "vsx_float2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?wa") + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?") (float:VSX_B (match_operand: 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xcvsx %x0,%x1" @@ -1082,7 +1114,7 @@ (set_attr "fp_type" "")]) (define_insn "vsx_floatuns2" - [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?wa") + [(set (match_operand:VSX_B 0 "gpc_reg_operand" "=,?") (unsigned_float:VSX_B (match_operand: 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xcvux %x0,%x1" @@ -1091,7 +1123,7 @@ (define_insn "vsx_fix_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=,?") - (fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",wa")))] + (fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xcvsxs %x0,%x1" [(set_attr "type" "") @@ -1099,7 +1131,7 @@ (define_insn "vsx_fixuns_trunc2" [(set (match_operand: 0 "gpc_reg_operand" "=,?") - (unsigned_fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",wa")))] + (unsigned_fix: (match_operand:VSX_B 1 "gpc_reg_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xcvuxs %x0,%x1" [(set_attr "type" "") @@ -1107,8 +1139,8 @@ ;; Math rounding functions (define_insn "vsx_xri" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",")] UNSPEC_VSX_ROUND_I))] "VECTOR_UNIT_VSX_P (mode)" "xri %x0,%x1" @@ -1116,8 +1148,8 @@ (set_attr "fp_type" "")]) (define_insn "vsx_xric" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",")] UNSPEC_VSX_ROUND_IC))] "VECTOR_UNIT_VSX_P (mode)" "xric %x0,%x1" @@ -1125,16 +1157,16 @@ (set_attr "fp_type" "")]) (define_insn "vsx_btrunc2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",")))] "VECTOR_UNIT_VSX_P (mode)" "xvriz %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_b2trunc2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?") + (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",")] UNSPEC_FRIZ))] "VECTOR_UNIT_VSX_P (mode)" "xriz %x0,%x1" @@ -1142,8 +1174,8 @@ (set_attr "fp_type" "")]) (define_insn "vsx_floor2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",")] UNSPEC_FRIM))] "VECTOR_UNIT_VSX_P (mode)" "xvrim %x0,%x1" @@ -1151,8 +1183,8 @@ (set_attr "fp_type" "")]) (define_insn "vsx_ceil2" - [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",")] UNSPEC_FRIP))] "VECTOR_UNIT_VSX_P (mode)" "xvrip %x0,%x1" @@ -1167,8 +1199,8 @@ ;; scalar single precision instructions internally use the double format. ;; Prefer the altivec registers, since we likely will need to do a vperm (define_insn "vsx_" - [(set (match_operand: 0 "vsx_register_operand" "=,?wa") - (unspec: [(match_operand:VSX_SPDP 1 "vsx_register_operand" ",wa")] + [(set (match_operand: 0 "vsx_register_operand" "=,?") + (unspec: [(match_operand:VSX_SPDP 1 "vsx_register_operand" ",")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (mode)" " %x0,%x1" @@ -1176,8 +1208,8 @@ ;; xscvspdp, represent the scalar SF type as V4SF (define_insn "vsx_xscvspdp" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa")] UNSPEC_VSX_CVSPDP))] "VECTOR_UNIT_VSX_P (V4SFmode)" "xscvspdp %x0,%x1" @@ -1204,7 +1236,7 @@ ;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs (define_insn "vsx_xscvdpspn" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa") + [(set (match_operand:V4SF 0 "vsx_register_operand" "=ww,?ww") (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" @@ -1212,16 +1244,16 @@ [(set_attr "type" "fp")]) (define_insn "vsx_xscvspdpn" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") - (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?ws") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wf,wa")] UNSPEC_VSX_CVSPDPN))] "TARGET_XSCVSPDPN" "xscvspdpn %x0,%x1" [(set_attr "type" "fp")]) (define_insn "vsx_xscvdpspn_scalar" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") - (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")] + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,?wa") + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "ww,ww")] UNSPEC_VSX_CVDPSPN))] "TARGET_XSCVDPSPN" "xscvdpspn %x0,%x1" @@ -1309,10 +1341,10 @@ ;; since the xsrdpiz instruction does not truncate the value if the floating ;; point value is < LONG_MIN or > LONG_MAX. (define_insn "*vsx_float_fix_2" - [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=,?wa") + [(set (match_operand:VSX_DF 0 "vsx_register_operand" "=,?") (float:VSX_DF (fix: - (match_operand:VSX_DF 1 "vsx_register_operand" ",?wa"))))] + (match_operand:VSX_DF 1 "vsx_register_operand" ",?"))))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && VECTOR_UNIT_VSX_P (mode) && flag_unsafe_math_optimizations && !flag_trapping_math && TARGET_FRIZ" @@ -1325,10 +1357,10 @@ ;; Build a V2DF/V2DI vector from two scalars (define_insn "vsx_concat_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=,?wa") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=,?") (vec_concat:VSX_D - (match_operand: 1 "vsx_register_operand" "ws,wa") - (match_operand: 2 "vsx_register_operand" "ws,wa")))] + (match_operand: 1 "vsx_register_operand" "ws,") + (match_operand: 2 "vsx_register_operand" "ws,")))] "VECTOR_MEM_VSX_P (mode)" { if (BYTES_BIG_ENDIAN) @@ -1359,18 +1391,18 @@ ;; xxpermdi for little endian loads and stores. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_xxpermdi2_le_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "wa") + (match_operand:VSX_LE 1 "vsx_register_operand" "") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" "xxpermdi %x0,%x1,%x1,2" [(set_attr "type" "vecperm")]) (define_insn "*vsx_xxpermdi4_le_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 1 "vsx_register_operand" "") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" @@ -1408,7 +1440,7 @@ ;; lxvd2x for little endian loads. We need several of ;; these since the form of the PARALLEL differs by mode. (define_insn "*vsx_lxvd2x2_le_" - [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_LE 0 "vsx_register_operand" "=") (vec_select:VSX_LE (match_operand:VSX_LE 1 "memory_operand" "Z") (parallel [(const_int 1) (const_int 0)])))] @@ -1417,7 +1449,7 @@ [(set_attr "type" "vecload")]) (define_insn "*vsx_lxvd2x4_le_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=") (vec_select:VSX_W (match_operand:VSX_W 1 "memory_operand" "Z") (parallel [(const_int 2) (const_int 3) @@ -1459,7 +1491,7 @@ (define_insn "*vsx_stxvd2x2_le_" [(set (match_operand:VSX_LE 0 "memory_operand" "=Z") (vec_select:VSX_LE - (match_operand:VSX_LE 1 "vsx_register_operand" "wa") + (match_operand:VSX_LE 1 "vsx_register_operand" "") (parallel [(const_int 1) (const_int 0)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" "stxvd2x %x1,%y0" @@ -1468,7 +1500,7 @@ (define_insn "*vsx_stxvd2x4_le_" [(set (match_operand:VSX_W 0 "memory_operand" "=Z") (vec_select:VSX_W - (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (match_operand:VSX_W 1 "vsx_register_operand" "") (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" @@ -1520,11 +1552,12 @@ ;; Set the element of a V2DI/VD2F mode (define_insn "vsx_set_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa") - (unspec:VSX_D [(match_operand:VSX_D 1 "vsx_register_operand" "wd,wa") - (match_operand: 2 "vsx_register_operand" "ws,wa") - (match_operand:QI 3 "u5bit_cint_operand" "i,i")] - UNSPEC_VSX_SET))] + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?") + (unspec:VSX_D + [(match_operand:VSX_D 1 "vsx_register_operand" "wd,") + (match_operand: 2 "vsx_register_operand" ",") + (match_operand:QI 3 "u5bit_cint_operand" "i,i")] + UNSPEC_VSX_SET))] "VECTOR_MEM_VSX_P (mode)" { int idx_first = BYTES_BIG_ENDIAN ? 0 : 1; @@ -1549,11 +1582,11 @@ ;; Optimize cases were we can do a simple or direct move. ;; Or see if we can avoid doing the move at all (define_insn "*vsx_extract__internal1" - [(set (match_operand: 0 "register_operand" "=d,ws,?wa,r") + [(set (match_operand: 0 "register_operand" "=d,,r") (vec_select: - (match_operand:VSX_D 1 "register_operand" "d,wd,wa,wm") + (match_operand:VSX_D 1 "register_operand" "d,,") (parallel - [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD,wD")])))] + [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] "VECTOR_MEM_VSX_P (mode) && TARGET_POWERPC64 && TARGET_DIRECT_MOVE" { int op0_regno = REGNO (operands[0]); @@ -1570,14 +1603,14 @@ return "xxlor %x0,%x1,%x1"; } - [(set_attr "type" "fp,vecsimple,vecsimple,mftgpr") + [(set_attr "type" "fp,vecsimple,mftgpr") (set_attr "length" "4")]) (define_insn "*vsx_extract__internal2" - [(set (match_operand: 0 "vsx_register_operand" "=d,ws,ws,?wa") + [(set (match_operand: 0 "vsx_register_operand" "=d,,") (vec_select: - (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd,wa") - (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i,i")])))] + (match_operand:VSX_D 1 "vsx_register_operand" "d,wd,wd") + (parallel [(match_operand:QI 2 "u5bit_cint_operand" "wD,wD,i")])))] "VECTOR_MEM_VSX_P (mode) && (!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE || INTVAL (operands[2]) != VECTOR_ELEMENT_SCALAR_64BIT)" @@ -1605,7 +1638,7 @@ operands[3] = GEN_INT (fldDM); return "xxpermdi %x0,%x1,%x1,%3"; } - [(set_attr "type" "fp,vecsimple,vecperm,vecperm") + [(set_attr "type" "fp,vecsimple,vecperm") (set_attr "length" "4")]) ;; Optimize extracting a single scalar element from memory if the scalar is in @@ -1643,7 +1676,7 @@ (define_insn "*vsx_extract__store" [(set (match_operand: 0 "memory_operand" "=m,Z,?Z") (vec_select: - (match_operand:VSX_D 1 "register_operand" "d,wd,wa") + (match_operand:VSX_D 1 "register_operand" "d,wd,") (parallel [(match_operand:QI 2 "vsx_scalar_64bit" "wD,wD,wD")])))] "VECTOR_MEM_VSX_P (mode)" "@ @@ -1666,7 +1699,7 @@ (define_insn_and_split "vsx_extract_v4sf" [(set (match_operand:SF 0 "vsx_register_operand" "=f,f") (vec_select:SF - (match_operand:V4SF 1 "vsx_register_operand" "wa,wa") + (match_operand:V4SF 1 "vsx_register_operand" ",") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "O,i")]))) (clobber (match_scratch:V4SF 3 "=X,0"))] "VECTOR_UNIT_VSX_P (V4SFmode)" @@ -1849,9 +1882,9 @@ ;; V2DF/V2DI splat (define_insn "vsx_splat_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?wa,?wa,?wa") + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?,?,?") (vec_duplicate:VSX_D - (match_operand: 1 "splat_input_operand" "ws,f,Z,wa,wa,Z")))] + (match_operand: 1 "splat_input_operand" ",f,Z,,,Z")))] "VECTOR_MEM_VSX_P (mode)" "@ xxpermdi %x0,%x1,%x1,0 @@ -1864,10 +1897,10 @@ ;; V4SF/V4SI splat (define_insn "vsx_xxspltw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?") (vec_duplicate:VSX_W (vec_select: - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + (match_operand:VSX_W 1 "vsx_register_operand" "wf,") (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))] "VECTOR_MEM_VSX_P (mode)" @@ -1880,8 +1913,8 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxspltw__direct" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") - (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?") + (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,") (match_operand:QI 2 "u5bit_cint_operand" "i,i")] UNSPEC_VSX_XXSPLTW))] "VECTOR_MEM_VSX_P (mode)" @@ -1890,11 +1923,11 @@ ;; V4SF/V4SI interleave (define_insn "vsx_xxmrghw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?") (vec_select:VSX_W (vec_concat: - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") - (match_operand:VSX_W 2 "vsx_register_operand" "wf,wa")) + (match_operand:VSX_W 1 "vsx_register_operand" "wf,") + (match_operand:VSX_W 2 "vsx_register_operand" "wf,")) (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (mode)" @@ -1907,11 +1940,11 @@ [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_" - [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?") (vec_select:VSX_W (vec_concat: - (match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") - (match_operand:VSX_W 2 "vsx_register_operand" "wf,?wa")) + (match_operand:VSX_W 1 "vsx_register_operand" "wf,") + (match_operand:VSX_W 2 "vsx_register_operand" "wf,?")) (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (mode)" @@ -1925,9 +1958,9 @@ ;; Shift left double by word immediate (define_insn "vsx_xxsldwi_" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=wa") - (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "wa") - (match_operand:VSX_L 2 "vsx_register_operand" "wa") + [(set (match_operand:VSX_L 0 "vsx_register_operand" "=") + (unspec:VSX_L [(match_operand:VSX_L 1 "vsx_register_operand" "") + (match_operand:VSX_L 2 "vsx_register_operand" "") (match_operand:QI 3 "u5bit_cint_operand" "i")] UNSPEC_VSX_SLDWI))] "VECTOR_MEM_VSX_P (mode)" diff --git a/gcc-4.9/gcc/config/sh/sh.c b/gcc-4.9/gcc/config/sh/sh.c index 62dcf0cb3..3d4553a6e 100644 --- a/gcc-4.9/gcc/config/sh/sh.c +++ b/gcc-4.9/gcc/config/sh/sh.c @@ -861,6 +861,12 @@ sh_option_override (void) targetm.asm_out.aligned_op.di = NULL; targetm.asm_out.unaligned_op.di = NULL; } + + /* User/priviledged mode is supported only on SH3*, SH4* and SH5*. + Disable it for everything else. */ + if (! (TARGET_SH3 || TARGET_SH5) && TARGET_USERMODE) + TARGET_USERMODE = false; + if (TARGET_SH1) { if (! strcmp (sh_div_str, "call-div1")) diff --git a/gcc-4.9/gcc/config/sh/sh.opt b/gcc-4.9/gcc/config/sh/sh.opt index 1834c6bde..bb6d39581 100644 --- a/gcc-4.9/gcc/config/sh/sh.opt +++ b/gcc-4.9/gcc/config/sh/sh.opt @@ -343,7 +343,7 @@ Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1) Cost to assume for a multiply insn musermode -Target Report RejectNegative Var(TARGET_USERMODE) +Target Var(TARGET_USERMODE) Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode. ;; We might want to enable this by default for TARGET_HARD_SH4, because -- cgit v1.2.3