From e3cc64dec20832769406aa38cde83c7dd4194bf4 Mon Sep 17 00:00:00 2001 From: Ben Cheng Date: Tue, 22 Apr 2014 13:33:12 -0700 Subject: [4.9] GCC 4.9.0 official release refresh Change-Id: Ic99a7da8b44b789a48aeec93b33e93944d6e6767 --- gcc-4.9/gcc/config/rs6000/rs6000.md | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'gcc-4.9/gcc/config/rs6000/rs6000.md') diff --git a/gcc-4.9/gcc/config/rs6000/rs6000.md b/gcc-4.9/gcc/config/rs6000/rs6000.md index 4bab9591e..64c9e7c10 100644 --- a/gcc-4.9/gcc/config/rs6000/rs6000.md +++ b/gcc-4.9/gcc/config/rs6000/rs6000.md @@ -10028,13 +10028,16 @@ rtx op0 = operands[0]; rtx op1 = operands[1]; rtx op2 = operands[2]; - rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0); + /* Also use the destination register to hold the unconverted DImode value. + This is conceptually a separate value from OP0, so we use gen_rtx_REG + rather than simplify_gen_subreg. */ + rtx op0_di = gen_rtx_REG (DImode, REGNO (op0)); rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); /* Move SF value to upper 32-bits for xscvspdpn. */ emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); emit_move_insn (op0_di, op2); - emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0_di)); DONE; } [(set_attr "length" "8") -- cgit v1.2.3