From f190d6284359da8ae8694b2d2e14b01602a959ed Mon Sep 17 00:00:00 2001 From: Andrew Hsieh Date: Wed, 18 Jun 2014 13:00:04 -0700 Subject: Merge GCC 4.8.3 Change-Id: I0abe59f7705b3eccc6b2f123af75b2e30917696a --- gcc-4.8/ChangeLog | 22 + gcc-4.8/ChangeLog.backported | 8 - gcc-4.8/INSTALL/binaries.html | 4 +- gcc-4.8/INSTALL/build.html | 12 +- gcc-4.8/INSTALL/configure.html | 48 +- gcc-4.8/INSTALL/download.html | 4 +- gcc-4.8/INSTALL/finalinstall.html | 8 +- gcc-4.8/INSTALL/gfdl.html | 38 +- gcc-4.8/INSTALL/index.html | 8 +- gcc-4.8/INSTALL/old.html | 14 +- gcc-4.8/INSTALL/prerequisites.html | 6 +- gcc-4.8/INSTALL/specific.html | 84 +- gcc-4.8/INSTALL/test.html | 20 +- gcc-4.8/LAST_UPDATED | 2 +- gcc-4.8/MD5SUMS | 3437 ++++++----- gcc-4.8/NEWS | 199 +- gcc-4.8/boehm-gc/ChangeLog | 16 + gcc-4.8/boehm-gc/configure | 16 +- gcc-4.8/boehm-gc/include/private/gcconfig.h | 8 + gcc-4.8/config.guess | 135 +- gcc-4.8/config.sub | 38 +- gcc-4.8/config/ChangeLog | 4 + gcc-4.8/contrib/ChangeLog | 8 + gcc-4.8/contrib/gcc_update | 2 +- gcc-4.8/contrib/reghunt/ChangeLog | 4 + gcc-4.8/contrib/regression/ChangeLog | 4 + gcc-4.8/fixincludes/ChangeLog | 4 + gcc-4.8/gcc/ChangeLog | 5480 +++++++++++++++++ gcc-4.8/gcc/DATESTAMP | 2 +- gcc-4.8/gcc/Makefile.in | 13 +- gcc-4.8/gcc/ada/ChangeLog | 61 + gcc-4.8/gcc/ada/back_end.ads | 1 + gcc-4.8/gcc/ada/cstand.adb | 23 +- gcc-4.8/gcc/ada/gcc-interface/Make-lang.in | 2 +- gcc-4.8/gcc/ada/gcc-interface/Makefile.in | 8 +- gcc-4.8/gcc/ada/gcc-interface/cuintp.c | 21 +- gcc-4.8/gcc/ada/gcc-interface/gigi.h | 2 +- gcc-4.8/gcc/ada/gcc-interface/misc.c | 25 +- gcc-4.8/gcc/ada/gcc-interface/utils.c | 128 +- gcc-4.8/gcc/ada/indepsw-darwin.adb | 67 + gcc-4.8/gcc/ada/system-linux-alpha.ads | 10 +- gcc-4.8/gcc/ada/system-linux-mips.ads | 3 +- gcc-4.8/gcc/ada/system-linux-mips64el.ads | 3 +- gcc-4.8/gcc/ada/system-linux-mipsel.ads | 3 +- gcc-4.8/gcc/ada/system-linux-s390.ads | 10 +- gcc-4.8/gcc/ada/system-linux-s390x.ads | 10 +- gcc-4.8/gcc/ada/system-linux-sparc.ads | 10 +- gcc-4.8/gcc/ada/system-linux-sparcv9.ads | 10 +- gcc-4.8/gcc/ada/system-rtems.ads | 8 +- gcc-4.8/gcc/ada/system-vxworks-arm.ads | 10 +- gcc-4.8/gcc/alias.c | 71 +- gcc-4.8/gcc/bb-reorder.c | 3 +- gcc-4.8/gcc/builtins.c | 89 +- gcc-4.8/gcc/builtins.def | 3 + gcc-4.8/gcc/c-family/ChangeLog | 79 + gcc-4.8/gcc/c-family/c-common.c | 27 +- gcc-4.8/gcc/c-family/c-opts.c | 11 +- gcc-4.8/gcc/c-family/c-pragma.c | 11 +- gcc-4.8/gcc/c-family/c.opt | 10 +- gcc-4.8/gcc/c/ChangeLog | 50 + gcc-4.8/gcc/c/c-decl.c | 6 +- gcc-4.8/gcc/c/c-parser.c | 2 +- gcc-4.8/gcc/c/c-tree.h | 2 + gcc-4.8/gcc/c/c-typeck.c | 58 +- gcc-4.8/gcc/calls.c | 9 +- gcc-4.8/gcc/cfgcleanup.c | 16 +- gcc-4.8/gcc/cfgexpand.c | 16 +- gcc-4.8/gcc/cgraph.c | 43 + gcc-4.8/gcc/cgraph.h | 1 + gcc-4.8/gcc/cgraphbuild.c | 20 +- gcc-4.8/gcc/combine.c | 46 +- gcc-4.8/gcc/config.gcc | 79 +- gcc-4.8/gcc/config.in | 12 + .../gcc/config/aarch64/aarch64-simd-builtins.def | 4 +- gcc-4.8/gcc/config/aarch64/aarch64-simd.md | 185 +- gcc-4.8/gcc/config/aarch64/aarch64.c | 9 +- gcc-4.8/gcc/config/aarch64/aarch64.h | 6 +- gcc-4.8/gcc/config/aarch64/aarch64.md | 2 +- gcc-4.8/gcc/config/aarch64/arm_neon.h | 68 +- gcc-4.8/gcc/config/aarch64/iterators.md | 61 +- gcc-4.8/gcc/config/aarch64/predicates.md | 5 + gcc-4.8/gcc/config/arm/arm-ldmstm.ml | 7 +- gcc-4.8/gcc/config/arm/arm.c | 74 +- gcc-4.8/gcc/config/arm/arm.h | 17 +- gcc-4.8/gcc/config/arm/arm.md | 6 +- gcc-4.8/gcc/config/arm/iterators.md | 4 + gcc-4.8/gcc/config/arm/ldmstm.md | 342 +- gcc-4.8/gcc/config/arm/predicates.md | 12 +- gcc-4.8/gcc/config/arm/vfp.md | 7 +- gcc-4.8/gcc/config/avr/avr.c | 25 +- gcc-4.8/gcc/config/avr/avr.md | 8 +- gcc-4.8/gcc/config/cris/cris.md | 27 +- gcc-4.8/gcc/config/cris/predicates.md | 4 + gcc-4.8/gcc/config/darwin.c | 54 +- gcc-4.8/gcc/config/i386/driver-i386.c | 63 +- gcc-4.8/gcc/config/i386/f16cintrin.h | 2 +- gcc-4.8/gcc/config/i386/i386.c | 614 +- gcc-4.8/gcc/config/i386/i386.h | 60 +- gcc-4.8/gcc/config/i386/i386.md | 91 +- gcc-4.8/gcc/config/i386/sse.md | 44 +- gcc-4.8/gcc/config/i386/t-rtems | 7 +- gcc-4.8/gcc/config/i386/winnt.c | 5 +- gcc-4.8/gcc/config/i386/xopintrin.h | 8 +- gcc-4.8/gcc/config/m68k/m68k.c | 10 +- gcc-4.8/gcc/config/microblaze/microblaze.c | 146 +- gcc-4.8/gcc/config/microblaze/microblaze.h | 9 +- gcc-4.8/gcc/config/microblaze/microblaze.md | 96 +- gcc-4.8/gcc/config/microblaze/predicates.md | 8 + gcc-4.8/gcc/config/mips/driver-native.c | 10 +- gcc-4.8/gcc/config/mips/mips.c | 22 +- gcc-4.8/gcc/config/mips/mips.h | 5 + gcc-4.8/gcc/config/mips/mips.md | 79 +- gcc-4.8/gcc/config/pa/pa.c | 34 +- gcc-4.8/gcc/config/pa/pa.h | 9 +- gcc-4.8/gcc/config/rs6000/altivec.h | 50 + gcc-4.8/gcc/config/rs6000/altivec.md | 1928 ++++-- gcc-4.8/gcc/config/rs6000/constraints.md | 58 +- gcc-4.8/gcc/config/rs6000/crypto.md | 101 + gcc-4.8/gcc/config/rs6000/darwin.h | 3 +- gcc-4.8/gcc/config/rs6000/dfp.md | 406 +- gcc-4.8/gcc/config/rs6000/htm.md | 366 ++ gcc-4.8/gcc/config/rs6000/htmintrin.h | 131 + gcc-4.8/gcc/config/rs6000/htmxlintrin.h | 213 + gcc-4.8/gcc/config/rs6000/linux64.h | 30 +- gcc-4.8/gcc/config/rs6000/option-defaults.h | 1 + gcc-4.8/gcc/config/rs6000/power8.md | 373 ++ gcc-4.8/gcc/config/rs6000/ppc-asm.h | 25 +- gcc-4.8/gcc/config/rs6000/predicates.md | 319 +- gcc-4.8/gcc/config/rs6000/rs6000-builtin.def | 536 +- gcc-4.8/gcc/config/rs6000/rs6000-c.c | 934 ++- gcc-4.8/gcc/config/rs6000/rs6000-cpus.def | 28 +- gcc-4.8/gcc/config/rs6000/rs6000-modes.def | 6 + gcc-4.8/gcc/config/rs6000/rs6000-opts.h | 11 +- gcc-4.8/gcc/config/rs6000/rs6000-protos.h | 19 +- gcc-4.8/gcc/config/rs6000/rs6000.c | 6281 +++++++++++++++++--- gcc-4.8/gcc/config/rs6000/rs6000.h | 304 +- gcc-4.8/gcc/config/rs6000/rs6000.md | 4077 +++++++++---- gcc-4.8/gcc/config/rs6000/rs6000.opt | 81 +- gcc-4.8/gcc/config/rs6000/sync.md | 365 +- gcc-4.8/gcc/config/rs6000/sysv4.h | 32 +- gcc-4.8/gcc/config/rs6000/sysv4le.h | 7 +- gcc-4.8/gcc/config/rs6000/t-linux64 | 10 +- gcc-4.8/gcc/config/rs6000/t-linux64bele | 7 + gcc-4.8/gcc/config/rs6000/t-linux64le | 3 + gcc-4.8/gcc/config/rs6000/t-linux64lebe | 7 + gcc-4.8/gcc/config/rs6000/t-rs6000 | 3 + gcc-4.8/gcc/config/rs6000/vector.md | 130 +- gcc-4.8/gcc/config/rs6000/vsx.md | 1206 ++-- gcc-4.8/gcc/config/s390/htmxlintrin.h | 25 +- gcc-4.8/gcc/config/s390/s390-protos.h | 1 + gcc-4.8/gcc/config/s390/s390.c | 302 +- gcc-4.8/gcc/config/s390/s390.h | 5 +- gcc-4.8/gcc/config/s390/s390.md | 32 +- gcc-4.8/gcc/config/s390/s390.opt | 8 + gcc-4.8/gcc/config/sh/constraints.md | 7 +- gcc-4.8/gcc/config/sh/predicates.md | 11 + gcc-4.8/gcc/config/sh/sh-protos.h | 2 + gcc-4.8/gcc/config/sh/sh.c | 28 +- gcc-4.8/gcc/config/sh/sh.md | 108 +- gcc-4.8/gcc/config/sh/sh.opt | 2 +- gcc-4.8/gcc/config/sparc/leon.md | 66 +- gcc-4.8/gcc/config/sparc/sparc-opts.h | 1 + gcc-4.8/gcc/config/sparc/sparc-protos.h | 3 +- gcc-4.8/gcc/config/sparc/sparc.c | 515 +- gcc-4.8/gcc/config/sparc/sparc.h | 46 +- gcc-4.8/gcc/config/sparc/sparc.md | 427 +- gcc-4.8/gcc/config/sparc/sparc.opt | 17 + gcc-4.8/gcc/config/sparc/sync.md | 32 +- gcc-4.8/gcc/config/sparc/t-rtems | 4 +- gcc-4.8/gcc/config/sparc/t-sparc | 2 +- gcc-4.8/gcc/config/tilegx/sync.md | 11 +- gcc-4.8/gcc/config/tilegx/tilegx-c.c | 3 + gcc-4.8/gcc/config/tilegx/tilegx.c | 37 +- gcc-4.8/gcc/config/tilegx/tilegx.md | 6 +- gcc-4.8/gcc/config/tilepro/tilepro-c.c | 5 + gcc-4.8/gcc/config/tilepro/tilepro.c | 6 + gcc-4.8/gcc/config/tilepro/tilepro.md | 6 +- gcc-4.8/gcc/configure | 108 +- gcc-4.8/gcc/configure.ac | 44 +- gcc-4.8/gcc/cp/ChangeLog | 262 + gcc-4.8/gcc/cp/call.c | 44 +- gcc-4.8/gcc/cp/cvt.c | 7 +- gcc-4.8/gcc/cp/decl.c | 21 +- gcc-4.8/gcc/cp/decl2.c | 32 +- gcc-4.8/gcc/cp/except.c | 3 + gcc-4.8/gcc/cp/mangle.c | 4 +- gcc-4.8/gcc/cp/name-lookup.c | 24 +- gcc-4.8/gcc/cp/parser.c | 31 +- gcc-4.8/gcc/cp/pt.c | 88 +- gcc-4.8/gcc/cp/semantics.c | 35 +- gcc-4.8/gcc/cp/typeck.c | 21 +- gcc-4.8/gcc/cp/typeck2.c | 13 +- gcc-4.8/gcc/cse.c | 21 +- gcc-4.8/gcc/cselib.c | 9 +- gcc-4.8/gcc/doc/aot-compile.1 | 20 +- gcc-4.8/gcc/doc/cpp.1 | 20 +- gcc-4.8/gcc/doc/cpp.info | 173 +- gcc-4.8/gcc/doc/cppinternals.info | 28 +- gcc-4.8/gcc/doc/extend.texi | 684 ++- gcc-4.8/gcc/doc/fsf-funding.7 | 22 +- gcc-4.8/gcc/doc/g++.1 | 364 +- gcc-4.8/gcc/doc/gc-analyze.1 | 20 +- gcc-4.8/gcc/doc/gcc.1 | 364 +- gcc-4.8/gcc/doc/gcc.info | 2979 +++++++--- gcc-4.8/gcc/doc/gccinstall.info | 228 +- gcc-4.8/gcc/doc/gccint.info | 1145 ++-- gcc-4.8/gcc/doc/gcj-dbtool.1 | 20 +- gcc-4.8/gcc/doc/gcj.1 | 34 +- gcc-4.8/gcc/doc/gcj.info | 152 +- gcc-4.8/gcc/doc/gcov.1 | 22 +- gcc-4.8/gcc/doc/gfdl.7 | 26 +- gcc-4.8/gcc/doc/gfortran.1 | 43 +- gcc-4.8/gcc/doc/gij.1 | 20 +- gcc-4.8/gcc/doc/gpl.7 | 32 +- gcc-4.8/gcc/doc/grmic.1 | 20 +- gcc-4.8/gcc/doc/invoke.texi | 286 +- gcc-4.8/gcc/doc/jcf-dump.1 | 20 +- gcc-4.8/gcc/doc/jv-convert.1 | 20 +- gcc-4.8/gcc/doc/md.texi | 52 +- gcc-4.8/gcc/doc/rebuild-gcj-db.1 | 20 +- gcc-4.8/gcc/doc/sourcebuild.texi | 31 +- gcc-4.8/gcc/dse.c | 3 +- gcc-4.8/gcc/expr.c | 52 +- gcc-4.8/gcc/expr.h | 4 +- gcc-4.8/gcc/fold-const.c | 28 +- gcc-4.8/gcc/fortran/ChangeLog | 260 + gcc-4.8/gcc/fortran/check.c | 2 +- gcc-4.8/gcc/fortran/class.c | 2 +- gcc-4.8/gcc/fortran/cpp.c | 1 + gcc-4.8/gcc/fortran/decl.c | 28 +- gcc-4.8/gcc/fortran/dump-parse-tree.c | 1 + gcc-4.8/gcc/fortran/expr.c | 13 +- gcc-4.8/gcc/fortran/frontend-passes.c | 29 +- gcc-4.8/gcc/fortran/gfortran.h | 1 + gcc-4.8/gcc/fortran/gfortran.info | 1841 +++--- gcc-4.8/gcc/fortran/interface.c | 7 +- gcc-4.8/gcc/fortran/intrinsic.c | 5 +- gcc-4.8/gcc/fortran/intrinsic.texi | 48 +- gcc-4.8/gcc/fortran/invoke.texi | 3 +- gcc-4.8/gcc/fortran/io.c | 33 +- gcc-4.8/gcc/fortran/match.c | 27 +- gcc-4.8/gcc/fortran/module.c | 129 +- gcc-4.8/gcc/fortran/parse.c | 3 +- gcc-4.8/gcc/fortran/primary.c | 3 +- gcc-4.8/gcc/fortran/resolve.c | 90 +- gcc-4.8/gcc/fortran/simplify.c | 4 +- gcc-4.8/gcc/fortran/symbol.c | 4 +- gcc-4.8/gcc/fortran/trans-array.c | 30 +- gcc-4.8/gcc/fortran/trans-decl.c | 9 +- gcc-4.8/gcc/fortran/trans-expr.c | 13 +- gcc-4.8/gcc/fortran/trans-intrinsic.c | 6 +- gcc-4.8/gcc/fortran/trans-io.c | 6 + gcc-4.8/gcc/fortran/trans-stmt.c | 39 + gcc-4.8/gcc/function.c | 58 +- gcc-4.8/gcc/gcc.c | 2 +- gcc-4.8/gcc/gengtype-lex.c | 120 +- gcc-4.8/gcc/gimple-fold.c | 10 +- gcc-4.8/gcc/gimple-low.c | 1 + gcc-4.8/gcc/gimple-ssa-strength-reduction.c | 7 +- gcc-4.8/gcc/gimple.c | 97 +- gcc-4.8/gcc/gimple.h | 14 +- gcc-4.8/gcc/gimplify.c | 64 +- gcc-4.8/gcc/go/ChangeLog | 23 + gcc-4.8/gcc/go/go-gcc.cc | 87 + gcc-4.8/gcc/go/go-lang.c | 4 + gcc-4.8/gcc/go/gofrontend/backend.h | 34 +- gcc-4.8/gcc/go/gofrontend/expressions.cc | 151 +- gcc-4.8/gcc/go/gofrontend/expressions.h | 4 +- gcc-4.8/gcc/go/gofrontend/gogo-tree.cc | 276 +- gcc-4.8/gcc/go/gofrontend/gogo.cc | 172 +- gcc-4.8/gcc/go/gofrontend/gogo.h | 39 +- gcc-4.8/gcc/go/gofrontend/import.h | 5 + gcc-4.8/gcc/go/gofrontend/lex.cc | 21 + gcc-4.8/gcc/go/gofrontend/parse.cc | 2 + gcc-4.8/gcc/go/gofrontend/runtime.cc | 7 + gcc-4.8/gcc/go/gofrontend/runtime.def | 6 + gcc-4.8/gcc/go/gofrontend/types.cc | 255 +- gcc-4.8/gcc/go/gofrontend/types.h | 37 +- gcc-4.8/gcc/graphite-scop-detection.c | 21 +- gcc-4.8/gcc/ifcvt.c | 11 +- gcc-4.8/gcc/ipa-cp.c | 22 +- gcc-4.8/gcc/ipa-prop.c | 64 +- gcc-4.8/gcc/ipa-pure-const.c | 8 +- gcc-4.8/gcc/ipa-split.c | 10 +- gcc-4.8/gcc/ipa.c | 2 + gcc-4.8/gcc/ira.c | 12 + gcc-4.8/gcc/java/ChangeLog | 4 + gcc-4.8/gcc/loop-iv.c | 12 +- gcc-4.8/gcc/loop-unswitch.c | 11 +- gcc-4.8/gcc/lra-coalesce.c | 31 + gcc-4.8/gcc/lra-constraints.c | 52 + gcc-4.8/gcc/lto/ChangeLog | 4 + gcc-4.8/gcc/mode-switching.c | 7 +- gcc-4.8/gcc/objc/ChangeLog | 15 + gcc-4.8/gcc/objc/objc-next-runtime-abi-01.c | 33 - gcc-4.8/gcc/objc/objc-next-runtime-abi-02.c | 28 - gcc-4.8/gcc/objcp/ChangeLog | 4 + gcc-4.8/gcc/optabs.c | 34 +- gcc-4.8/gcc/opts.c | 4 +- gcc-4.8/gcc/params.def | 6 + gcc-4.8/gcc/passes.c | 2 +- gcc-4.8/gcc/po/ChangeLog | 4 + gcc-4.8/gcc/print-rtl.c | 2 + gcc-4.8/gcc/recog.c | 5 +- gcc-4.8/gcc/regcprop.c | 18 + gcc-4.8/gcc/reginfo.c | 23 +- gcc-4.8/gcc/reorg.c | 14 +- gcc-4.8/gcc/rtl.h | 4 + gcc-4.8/gcc/rtlanal.c | 42 +- gcc-4.8/gcc/sdbout.c | 10 +- gcc-4.8/gcc/sel-sched.c | 2 +- gcc-4.8/gcc/simplify-rtx.c | 13 +- gcc-4.8/gcc/stmt.c | 15 +- gcc-4.8/gcc/testsuite/ChangeLog | 1876 +++++- gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-1.c | 8 + gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-2.c | 8 + gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-1.h | 3 + gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-2.h | 4 + gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400.c | 13 + gcc-4.8/gcc/testsuite/c-c++-common/fold-divmul-1.c | 11 + gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr58809.c | 31 + gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr59467.c | 68 + gcc-4.8/gcc/testsuite/c-c++-common/pr36282-1.c | 12 + gcc-4.8/gcc/testsuite/c-c++-common/pr36282-2.c | 10 + gcc-4.8/gcc/testsuite/c-c++-common/pr36282-3.c | 13 + gcc-4.8/gcc/testsuite/c-c++-common/pr36282-4.c | 13 + gcc-4.8/gcc/testsuite/c-c++-common/pr37743.c | 13 + gcc-4.8/gcc/testsuite/c-c++-common/pr59032.c | 30 + gcc-4.8/gcc/testsuite/c-c++-common/pr59037.c | 12 + gcc-4.8/gcc/testsuite/c-c++-common/pr59280.c | 4 + gcc-4.8/gcc/testsuite/c-c++-common/pr60101.c | 112 + gcc-4.8/gcc/testsuite/c-c++-common/pr60689.c | 10 + .../gcc/testsuite/c-c++-common/torture/pr58794-1.c | 29 + .../gcc/testsuite/c-c++-common/torture/pr58794-2.c | 21 + .../gcc/testsuite/c-c++-common/torture/pr60026.c | 28 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/access02.C | 39 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C | 18 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/auto42.C | 9 + .../testsuite/g++.dg/cpp0x/constexpr-template6.C | 20 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/decltype57.C | 8 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/defaulted48.C | 17 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/deleted3.C | 11 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/enum_base2.C | 9 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist76.C | 5 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist78.C | 12 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist79.C | 8 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist81.C | 25 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist82.C | 20 + .../testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C | 7 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/noexcept22.C | 21 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C | 10 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C | 13 + .../gcc/testsuite/g++.dg/cpp0x/static_assert9.C | 7 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic144.C | 15 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic145.C | 13 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic147.C | 10 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic148.C | 6 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic149.C | 11 + gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic150.C | 9 + gcc-4.8/gcc/testsuite/g++.dg/diagnostic/pedantic.C | 11 + gcc-4.8/gcc/testsuite/g++.dg/diagnostic/pr58979.C | 4 + gcc-4.8/gcc/testsuite/g++.dg/diagnostic/pr59838.C | 4 + .../gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C | 54 + gcc-4.8/gcc/testsuite/g++.dg/eh/uncaught1.C | 2 +- gcc-4.8/gcc/testsuite/g++.dg/eh/uncaught4.C | 29 + gcc-4.8/gcc/testsuite/g++.dg/ext/attrib48.C | 6 + gcc-4.8/gcc/testsuite/g++.dg/ext/builtin-bswap1.C | 22 + gcc-4.8/gcc/testsuite/g++.dg/ext/stmtexpr15.C | 7 + gcc-4.8/gcc/testsuite/g++.dg/ext/timevar2.C | 14 + gcc-4.8/gcc/testsuite/g++.dg/ext/traits1.C | 4 + gcc-4.8/gcc/testsuite/g++.dg/ext/vector25.C | 6 + gcc-4.8/gcc/testsuite/g++.dg/ext/vector27.C | 7 + gcc-4.8/gcc/testsuite/g++.dg/gomp/for-20.C | 16 + gcc-4.8/gcc/testsuite/g++.dg/gomp/pr59297.C | 25 + gcc-4.8/gcc/testsuite/g++.dg/inherit/virtual11.C | 17 + gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60419.C | 80 + gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60640-1.C | 50 + gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60640-2.C | 15 + gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60640-3.C | 81 + gcc-4.8/gcc/testsuite/g++.dg/opt/pr58864.C | 21 + gcc-4.8/gcc/testsuite/g++.dg/opt/pr59470.C | 188 + gcc-4.8/gcc/testsuite/g++.dg/opt/pr59647.C | 32 + gcc-4.8/gcc/testsuite/g++.dg/opt/pr60849.C | 13 + gcc-4.8/gcc/testsuite/g++.dg/overload/defarg8.C | 22 + gcc-4.8/gcc/testsuite/g++.dg/pr60769.C | 43 + gcc-4.8/gcc/testsuite/g++.dg/template/partial15.C | 19 + gcc-4.8/gcc/testsuite/g++.dg/template/ref7.C | 16 + gcc-4.8/gcc/testsuite/g++.dg/template/shadow1.C | 4 + gcc-4.8/gcc/testsuite/g++.dg/template/using27.C | 33 + gcc-4.8/gcc/testsuite/g++.dg/template/using28.C | 17 + gcc-4.8/gcc/testsuite/g++.dg/template/using29.C | 21 + .../gcc/testsuite/g++.dg/tls/thread_local-ice2.C | 11 + gcc-4.8/gcc/testsuite/g++.dg/tls/thread_local8.C | 12 + gcc-4.8/gcc/testsuite/g++.dg/tm/noexcept-6.C | 23 + gcc-4.8/gcc/testsuite/g++.dg/tm/pr60004.C | 10 + gcc-4.8/gcc/testsuite/g++.dg/torture/pr57499.C | 14 + gcc-4.8/gcc/testsuite/g++.dg/torture/pr59163.C | 30 + gcc-4.8/gcc/testsuite/g++.dg/torture/pr60609.C | 252 + gcc-4.8/gcc/testsuite/g++.dg/torture/pr60750.C | 21 + gcc-4.8/gcc/testsuite/g++.dg/torture/pr60895.C | 32 + gcc-4.8/gcc/testsuite/g++.dg/tree-prof/pr59255.C | 29 + gcc-4.8/gcc/testsuite/g++.dg/vect/pr60729.cc | 10 + gcc-4.8/gcc/testsuite/g++.dg/vect/pr60836.cc | 39 + .../testsuite/gcc.c-torture/compile/pr58970-1.c | 11 + .../testsuite/gcc.c-torture/compile/pr58970-2.c | 11 + .../gcc/testsuite/gcc.c-torture/compile/pr58997.c | 19 + .../gcc/testsuite/gcc.c-torture/compile/pr59362.c | 21 + .../gcc/testsuite/gcc.c-torture/compile/pr59803.c | 27 + .../gcc/testsuite/gcc.c-torture/compile/pr60502.c | 18 + .../testsuite/gcc.c-torture/execute/20131127-1.c | 34 + .../testsuite/gcc.c-torture/execute/20140212-1.c | 37 + .../testsuite/gcc.c-torture/execute/20140326-1.c | 10 + .../testsuite/gcc.c-torture/execute/20140425-1.c | 23 + .../gcc/testsuite/gcc.c-torture/execute/pr58726.c | 26 + .../gcc/testsuite/gcc.c-torture/execute/pr58831.c | 40 + .../gcc/testsuite/gcc.c-torture/execute/pr58984.c | 57 + .../testsuite/gcc.c-torture/execute/pr59014-2.c | 23 + .../gcc/testsuite/gcc.c-torture/execute/pr59014.c | 25 + .../gcc/testsuite/gcc.c-torture/execute/pr59101.c | 15 + .../gcc/testsuite/gcc.c-torture/execute/pr59358.c | 44 + .../gcc/testsuite/gcc.c-torture/execute/pr59388.c | 11 + .../gcc/testsuite/gcc.c-torture/execute/pr60017.c | 33 + .../gcc/testsuite/gcc.c-torture/execute/pr60062.c | 25 + .../gcc/testsuite/gcc.c-torture/execute/pr60072.c | 16 + .../gcc/testsuite/gcc.c-torture/execute/pr60454.c | 31 + .../gcc/testsuite/gcc.c-torture/execute/pr60960.c | 38 + gcc-4.8/gcc/testsuite/gcc.dg/20050922-1.c | 2 +- gcc-4.8/gcc/testsuite/gcc.dg/20050922-2.c | 3 +- gcc-4.8/gcc/testsuite/gcc.dg/atomic-store-6.c | 13 + .../gcc/testsuite/gcc.dg/builtin-object-size-14.c | 28 + .../testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c | 7 + gcc-4.8/gcc/testsuite/gcc.dg/gomp/pr58809.c | 13 + gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr55022.c | 27 + gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr59817-1.c | 16 + gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr59817-2.c | 15 + gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr60740.c | 16 + gcc-4.8/gcc/testsuite/gcc.dg/guality/pr59776.c | 29 + gcc-4.8/gcc/testsuite/gcc.dg/ipa/pr55260.c | 38 + gcc-4.8/gcc/testsuite/gcc.dg/ipa/pr59610.c | 11 + gcc-4.8/gcc/testsuite/gcc.dg/pr56824.c | 18 + gcc-4.8/gcc/testsuite/gcc.dg/pr58668.c | 25 + gcc-4.8/gcc/testsuite/gcc.dg/pr58805.c | 24 + gcc-4.8/gcc/testsuite/gcc.dg/pr59011.c | 22 + gcc-4.8/gcc/testsuite/gcc.dg/pr59351.c | 8 + gcc-4.8/gcc/testsuite/gcc.dg/pr59827.c | 15 + gcc-4.8/gcc/testsuite/gcc.dg/pr59860.c | 15 + gcc-4.8/gcc/testsuite/gcc.dg/pr60485-1.c | 29 + gcc-4.8/gcc/testsuite/gcc.dg/pr60485-2.c | 38 + gcc-4.8/gcc/testsuite/gcc.dg/stack-usage-1.c | 4 + gcc-4.8/gcc/testsuite/gcc.dg/tls/pr58595.c | 28 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57425-1.c | 37 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57425-2.c | 31 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57425-3.c | 31 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57488.c | 58 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57517.c | 16 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57569.c | 37 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57864.c | 37 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58079.c | 107 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58143-1.c | 51 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58143-2.c | 34 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58143-3.c | 18 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58779.c | 12 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58830.c | 42 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58941.c | 33 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58956.c | 30 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59047.c | 39 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59139.c | 20 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59164.c | 21 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59288.c | 9 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59330.c | 17 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59715.c | 21 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59891.c | 9 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59903.c | 56 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60115.c | 14 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60183.c | 38 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60766.c | 15 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60903.c | 22 + gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60930.c | 22 + gcc-4.8/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c | 14 + gcc-4.8/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c | 18 + gcc-4.8/gcc/testsuite/gcc.dg/unused-8b.c | 4 + gcc-4.8/gcc/testsuite/gcc.dg/vect/pr60276.c | 52 + gcc-4.8/gcc/testsuite/gcc.dg/vect/pr60382.c | 32 + .../gcc/testsuite/gcc.dg/vmx/extract-be-order.c | 33 + .../testsuite/gcc.dg/vmx/extract-vsx-be-order.c | 19 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/extract-vsx.c | 16 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/extract.c | 21 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/gcc-bug-i.c | 15 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert-be-order.c | 65 + .../gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c | 34 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert-vsx.c | 28 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert.c | 37 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld-be-order.c | 107 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c | 44 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld-vsx.c | 39 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld.c | 91 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/lde-be-order.c | 73 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/lde.c | 59 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c | 107 + .../gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c | 44 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c | 39 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl.c | 91 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge-be-order.c | 96 + .../gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c | 84 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge-vsx.c | 71 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge.c | 77 + .../testsuite/gcc.dg/vmx/mult-even-odd-be-order.c | 64 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c | 43 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/pack-be-order.c | 136 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/pack.c | 108 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/perm-be-order.c | 74 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/perm.c | 69 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/sn7153.c | 4 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat-be-order.c | 59 + .../gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c | 37 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat-vsx.c | 31 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat.c | 47 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/st-be-order.c | 83 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c | 34 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/st-vsx.c | 29 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/st.c | 67 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ste-be-order.c | 53 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/ste.c | 41 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl-be-order.c | 83 + .../gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c | 34 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl-vsx.c | 29 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl.c | 67 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c | 19 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/sum2s.c | 13 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c | 88 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/unpack.c | 67 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/vec-set.c | 14 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c | 20 + gcc-4.8/gcc/testsuite/gcc.dg/vmx/vsums.c | 12 + .../gcc.target/aarch64/scalar_intrinsics.c | 112 +- .../gcc.target/arm/neon/vst1Q_laneu64-1.c | 25 + gcc-4.8/gcc/testsuite/gcc.target/arm/pr54300.C | 61 + gcc-4.8/gcc/testsuite/gcc.target/arm/pr57637.c | 206 + gcc-4.8/gcc/testsuite/gcc.target/arm/pr59826.c | 35 + .../gcc.target/arm/require-pic-register-loc.c | 29 + .../testsuite/gcc.target/arm/thumb1-pic-high-reg.c | 11 + .../gcc.target/arm/thumb1-pic-single-base.c | 11 + gcc-4.8/gcc/testsuite/gcc.target/arm/vrinta-ce.c | 15 + gcc-4.8/gcc/testsuite/gcc.target/avr/pr60991.c | 21 + .../gcc/testsuite/gcc.target/avr/torture/pr61055.c | 88 + .../testsuite/gcc.target/i386/avx-vmovapd-256-1.c | 2 +- .../testsuite/gcc.target/i386/avx-vmovapd-256-2.c | 2 +- gcc-4.8/gcc/testsuite/gcc.target/i386/nest-1.c | 14 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr30315.c | 44 +- gcc-4.8/gcc/testsuite/gcc.target/i386/pr39162.c | 9 +- gcc-4.8/gcc/testsuite/gcc.target/i386/pr43546.c | 12 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr54694.c | 11 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr58137.c | 33 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr58690.c | 14 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59021.c | 23 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59034-1.c | 10 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59034-2.c | 10 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59405.c | 24 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59470.c | 17 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59625.c | 36 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-1.c | 15 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-2.c | 15 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-3.c | 15 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-4.c | 14 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-5.c | 14 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-6.c | 14 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-7.c | 13 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59839.c | 12 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr59929.c | 55 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr60516.c | 20 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr60693.c | 13 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr60700.c | 59 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr60909-1.c | 11 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr60909-2.c | 11 + gcc-4.8/gcc/testsuite/gcc.target/i386/pr9771-1.c | 12 +- .../gcc/testsuite/gcc.target/i386/sse2-movapd-1.c | 2 +- .../gcc/testsuite/gcc.target/i386/sse2-movapd-2.c | 2 +- gcc-4.8/gcc/testsuite/gcc.target/i386/xop-frczX.c | 60 + .../testsuite/gcc.target/microblaze/isa/fcmp4.c | 9 + .../gcc.target/microblaze/others/builtin-trap.c | 8 + .../gcc.target/microblaze/others/mem_reload.c | 74 + gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-1.c | 10 + gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-2.c | 9 + gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-3.c | 14 + gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-4.c | 10 + gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-5.c | 20 + gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-6.c | 12 + gcc-4.8/gcc/testsuite/gcc.target/mips/pr59137.c | 34 + .../testsuite/gcc.target/powerpc/altivec-perm-1.c | 15 - .../testsuite/gcc.target/powerpc/altivec-perm-3.c | 23 + .../gcc/testsuite/gcc.target/powerpc/atomic-p7.c | 207 + .../gcc/testsuite/gcc.target/powerpc/atomic-p8.c | 237 + .../gcc.target/powerpc/atomic_load_store-p8.c | 22 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-1.c | 27 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-2.c | 44 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-3.c | 103 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool.c | 14 + .../gcc/testsuite/gcc.target/powerpc/bool2-av.c | 32 + .../gcc/testsuite/gcc.target/powerpc/bool2-p5.c | 32 + .../gcc/testsuite/gcc.target/powerpc/bool2-p7.c | 31 + .../gcc/testsuite/gcc.target/powerpc/bool2-p8.c | 32 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2.h | 29 + .../gcc/testsuite/gcc.target/powerpc/bool3-av.c | 37 + .../gcc/testsuite/gcc.target/powerpc/bool3-p7.c | 37 + .../gcc/testsuite/gcc.target/powerpc/bool3-p8.c | 36 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3.h | 186 + .../gcc.target/powerpc/crypto-builtin-1.c | 130 + .../testsuite/gcc.target/powerpc/darwin-longlong.c | 4 + .../testsuite/gcc.target/powerpc/dfp-builtin-1.c | 88 + .../testsuite/gcc.target/powerpc/dfp-builtin-2.c | 88 + .../gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c | 26 + .../gcc/testsuite/gcc.target/powerpc/dfp-td-2.c | 29 + .../gcc/testsuite/gcc.target/powerpc/dfp-td-3.c | 29 + .../gcc.target/powerpc/direct-move-double1.c | 16 + .../gcc.target/powerpc/direct-move-double2.c | 15 + .../gcc.target/powerpc/direct-move-float1.c | 18 + .../gcc.target/powerpc/direct-move-float2.c | 15 + .../gcc.target/powerpc/direct-move-long1.c | 16 + .../gcc.target/powerpc/direct-move-long2.c | 15 + .../gcc.target/powerpc/direct-move-vint1.c | 14 + .../gcc.target/powerpc/direct-move-vint2.c | 13 + .../gcc/testsuite/gcc.target/powerpc/direct-move.h | 188 + .../testsuite/gcc.target/powerpc/extend-divide-1.c | 34 + .../testsuite/gcc.target/powerpc/extend-divide-2.c | 34 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/fusion.c | 24 + .../testsuite/gcc.target/powerpc/htm-builtin-1.c | 51 + .../testsuite/gcc.target/powerpc/htm-xl-intrin-1.c | 32 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c | 22 + .../gcc.target/powerpc/p8vector-builtin-1.c | 65 + .../gcc.target/powerpc/p8vector-builtin-2.c | 204 + .../gcc.target/powerpc/p8vector-builtin-3.c | 104 + .../gcc.target/powerpc/p8vector-builtin-4.c | 249 + .../gcc.target/powerpc/p8vector-builtin-5.c | 105 + .../gcc.target/powerpc/p8vector-builtin-6.c | 10 + .../gcc.target/powerpc/p8vector-builtin-7.c | 32 + .../gcc/testsuite/gcc.target/powerpc/p8vector-fp.c | 139 + .../gcc.target/powerpc/p8vector-int128-1.c | 85 + .../gcc.target/powerpc/p8vector-int128-2.c | 177 + .../testsuite/gcc.target/powerpc/p8vector-ldst.c | 42 + .../gcc.target/powerpc/p8vector-vbpermq.c | 27 + .../gcc.target/powerpc/p8vector-vectorize-1.c | 200 + .../gcc.target/powerpc/p8vector-vectorize-2.c | 30 + .../gcc.target/powerpc/p8vector-vectorize-3.c | 29 + .../gcc.target/powerpc/p8vector-vectorize-4.c | 69 + .../gcc.target/powerpc/p8vector-vectorize-5.c | 87 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack01.c | 91 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack02.c | 95 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack03.c | 88 + .../gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c | 2 + .../gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c | 20 +- .../testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c | 26 +- gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57744.c | 39 + .../gcc/testsuite/gcc.target/powerpc/pr57949-1.c | 20 + .../gcc/testsuite/gcc.target/powerpc/pr57949-2.c | 20 + .../gcc/testsuite/gcc.target/powerpc/pr58673-1.c | 78 + .../gcc/testsuite/gcc.target/powerpc/pr58673-2.c | 217 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr59054.c | 9 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60137.c | 17 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60203.c | 40 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60735.c | 11 + .../gcc/testsuite/gcc.target/powerpc/quad-atomic.c | 67 + .../gcc.target/powerpc/rs6000-ldouble-3.c | 21 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c | 19 + gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-vsx.c | 20 + .../gcc/testsuite/gcc.target/powerpc/ti_math1.c | 20 + .../gcc/testsuite/gcc.target/powerpc/ti_math2.c | 73 + .../gcc/testsuite/gcc.target/powerpc/vsx-float0.c | 16 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-1.c | 20 + .../gcc/testsuite/gcc.target/s390/hotpatch-10.c | 21 + .../gcc/testsuite/gcc.target/s390/hotpatch-11.c | 20 + .../gcc/testsuite/gcc.target/s390/hotpatch-12.c | 20 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-2.c | 20 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-3.c | 20 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-4.c | 26 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-5.c | 21 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-6.c | 21 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-7.c | 21 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-8.c | 28 + gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-9.c | 21 + .../testsuite/gcc.target/s390/hotpatch-compile-1.c | 27 + .../testsuite/gcc.target/s390/hotpatch-compile-2.c | 27 + .../testsuite/gcc.target/s390/hotpatch-compile-3.c | 27 + .../testsuite/gcc.target/s390/hotpatch-compile-4.c | 11 + .../testsuite/gcc.target/s390/hotpatch-compile-5.c | 28 + .../testsuite/gcc.target/s390/hotpatch-compile-6.c | 11 + .../testsuite/gcc.target/s390/hotpatch-compile-7.c | 68 + .../testsuite/gcc.target/s390/hotpatch-compile-8.c | 23 + gcc-4.8/gcc/testsuite/gcc.target/s390/htm-1.c | 73 - .../gcc/testsuite/gcc.target/s390/htm-builtins-1.c | 1073 ++++ .../gcc/testsuite/gcc.target/s390/htm-builtins-2.c | 682 +++ .../gcc.target/s390/htm-builtins-compile-1.c | 164 + .../gcc.target/s390/htm-builtins-compile-2.c | 12 + .../gcc.target/s390/htm-builtins-compile-3.c | 37 + .../gcc/testsuite/gcc.target/s390/htm-nofloat-1.c | 54 +- .../gcc/testsuite/gcc.target/s390/htm-nofloat-2.c | 55 - .../gcc.target/s390/htm-nofloat-compile-1.c | 12 + .../testsuite/gcc.target/s390/htm-xl-intrin-1.c | 37 - gcc-4.8/gcc/testsuite/gcc.target/s390/s390.exp | 13 + .../gcc/testsuite/gfortran.dg/allocate_class_3.f90 | 107 + gcc-4.8/gcc/testsuite/gfortran.dg/arrayio_13.f90 | 14 + .../gcc/testsuite/gfortran.dg/constructor_9.f90 | 22 + .../gfortran.dg/default_initialization_7.f90 | 22 + .../gfortran.dg/derived_external_function_1.f90 | 27 + .../testsuite/gfortran.dg/dynamic_dispatch_12.f90 | 74 + .../gfortran.dg/elemental_subroutine_9.f90 | 39 + gcc-4.8/gcc/testsuite/gfortran.dg/extends_15.f90 | 16 + gcc-4.8/gcc/testsuite/gfortran.dg/fmt_en.f90 | 186 + gcc-4.8/gcc/testsuite/gfortran.dg/fmt_g_1.f90 | 11 + gcc-4.8/gcc/testsuite/gfortran.dg/generic_28.f90 | 18 + gcc-4.8/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 | 24 + .../gcc/testsuite/gfortran.dg/graphite/pr59817.f | 14 + gcc-4.8/gcc/testsuite/gfortran.dg/ichar_3.f90 | 13 + .../gcc/testsuite/gfortran.dg/implicit_pure_4.f90 | 22 + gcc-4.8/gcc/testsuite/gfortran.dg/init_flag_12.f90 | 13 + gcc-4.8/gcc/testsuite/gfortran.dg/list_read_12.f90 | 11 + .../gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 | 16 + gcc-4.8/gcc/testsuite/gfortran.dg/lto/pr60635_1.c | 14 + gcc-4.8/gcc/testsuite/gfortran.dg/nan_7.f90 | 1 + gcc-4.8/gcc/testsuite/gfortran.dg/null_5.f90 | 2 +- gcc-4.8/gcc/testsuite/gfortran.dg/null_6.f90 | 2 +- .../gcc/testsuite/gfortran.dg/optional_class_1.f90 | 45 + gcc-4.8/gcc/testsuite/gfortran.dg/pr52370.f90 | 21 + gcc-4.8/gcc/testsuite/gfortran.dg/pr59700.f90 | 40 + gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 | 19 + gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 | 24 + gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 | 14 + .../gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 | 12 + gcc-4.8/gcc/testsuite/gfortran.dg/reshape_6.f90 | 19 + gcc-4.8/gcc/testsuite/gfortran.dg/round_3.f08 | 25 + gcc-4.8/gcc/testsuite/gfortran.dg/shape_8.f90 | 10 + .../testsuite/gfortran.dg/str_comp_optimize_1.f90 | 22 + .../testsuite/gfortran.dg/typebound_generic_15.f90 | 18 + .../gfortran.dg/unlimited_polymorphic_15.f90 | 17 + .../testsuite/gfortran.dg/unresolved_fixup_1.f90 | 44 + .../testsuite/gfortran.dg/unresolved_fixup_2.f90 | 36 + gcc-4.8/gcc/testsuite/gfortran.dg/where_4.f90 | 18 + .../gfortran.fortran-torture/compile/pr57517.f90 | 13 + gcc-4.8/gcc/testsuite/gnat.dg/opt32.adb | 37 + gcc-4.8/gcc/testsuite/go.test/go-test.exp | 11 +- gcc-4.8/gcc/testsuite/lib/target-supports.exp | 124 +- gcc-4.8/gcc/tree-cfg.c | 44 +- gcc-4.8/gcc/tree-cfgcleanup.c | 3 - gcc-4.8/gcc/tree-dfa.c | 95 +- gcc-4.8/gcc/tree-eh.c | 48 +- gcc-4.8/gcc/tree-flow.h | 1 + gcc-4.8/gcc/tree-inline.c | 3 +- gcc-4.8/gcc/tree-object-size.c | 48 +- gcc-4.8/gcc/tree-predcom.c | 124 +- gcc-4.8/gcc/tree-sra.c | 15 +- gcc-4.8/gcc/tree-ssa-dce.c | 27 +- gcc-4.8/gcc/tree-ssa-live.c | 3 +- gcc-4.8/gcc/tree-ssa-loop-im.c | 88 +- gcc-4.8/gcc/tree-ssa-loop-ivopts.c | 9 +- gcc-4.8/gcc/tree-ssa-loop-niter.c | 7 +- gcc-4.8/gcc/tree-ssa-math-opts.c | 11 + gcc-4.8/gcc/tree-ssa-operands.c | 6 +- gcc-4.8/gcc/tree-ssa-phiprop.c | 9 + gcc-4.8/gcc/tree-ssa-pre.c | 6 + gcc-4.8/gcc/tree-ssa-propagate.c | 12 +- gcc-4.8/gcc/tree-ssa-reassoc.c | 10 +- gcc-4.8/gcc/tree-ssa-sccvn.c | 12 +- gcc-4.8/gcc/tree-ssa-sink.c | 2 +- gcc-4.8/gcc/tree-ssa-structalias.c | 104 +- gcc-4.8/gcc/tree-ssa-tail-merge.c | 3 +- gcc-4.8/gcc/tree-ssa-ter.c | 49 +- gcc-4.8/gcc/tree-ssa-uninit.c | 58 +- gcc-4.8/gcc/tree-ssanames.c | 2 +- gcc-4.8/gcc/tree-vect-data-refs.c | 7 + gcc-4.8/gcc/tree-vect-generic.c | 3 +- gcc-4.8/gcc/tree-vect-loop.c | 61 +- gcc-4.8/gcc/tree-vect-stmts.c | 31 +- gcc-4.8/gcc/tree-vectorizer.h | 5 + gcc-4.8/gcc/tree-vrp.c | 16 +- gcc-4.8/gcc/tree.c | 54 + gcc-4.8/gcc/tree.h | 19 +- gcc-4.8/gcc/value-prof.c | 3 +- gcc-4.8/gnattools/ChangeLog | 24 + gcc-4.8/gnattools/Makefile.in | 30 +- gcc-4.8/gnattools/configure | 69 +- gcc-4.8/gnattools/configure.ac | 69 +- gcc-4.8/include/ChangeLog | 4 + gcc-4.8/intl/ChangeLog | 4 + gcc-4.8/libada/ChangeLog | 4 + gcc-4.8/libatomic/ChangeLog | 17 + gcc-4.8/libatomic/cas_n.c | 21 +- gcc-4.8/libatomic/configure | 16 +- gcc-4.8/libbacktrace/ChangeLog | 36 + gcc-4.8/libbacktrace/Makefile.in | 2 +- gcc-4.8/libbacktrace/alloc.c | 20 +- gcc-4.8/libbacktrace/configure | 21 +- gcc-4.8/libbacktrace/configure.ac | 2 +- gcc-4.8/libbacktrace/dwarf.c | 8 +- gcc-4.8/libbacktrace/elf.c | 7 + gcc-4.8/libbacktrace/internal.h | 14 +- gcc-4.8/libbacktrace/mmap.c | 13 +- gcc-4.8/libcpp/ChangeLog | 37 + gcc-4.8/libcpp/files.c | 26 +- gcc-4.8/libcpp/lex.c | 9 + gcc-4.8/libcpp/line-map.c | 5 + gcc-4.8/libcpp/macro.c | 17 +- gcc-4.8/libcpp/po/ChangeLog | 12 + gcc-4.8/libcpp/po/pt_BR.gmo | Bin 0 -> 21689 bytes gcc-4.8/libcpp/po/pt_BR.po | 908 +++ gcc-4.8/libcpp/po/tr.gmo | Bin 18470 -> 21337 bytes gcc-4.8/libcpp/po/tr.po | 139 +- gcc-4.8/libdecnumber/ChangeLog | 4 + gcc-4.8/libffi/ChangeLog | 40 + gcc-4.8/libffi/Makefile.am | 14 +- gcc-4.8/libffi/Makefile.in | 30 +- gcc-4.8/libffi/configure | 30 +- gcc-4.8/libffi/configure.ac | 11 +- gcc-4.8/libffi/doc/libffi.info | 68 +- gcc-4.8/libffi/doc/libffi.texi | 27 +- gcc-4.8/libffi/fficonfig.h.in | 3 + gcc-4.8/libffi/include/Makefile.in | 1 + gcc-4.8/libffi/include/ffi.h.in | 5 + gcc-4.8/libffi/man/Makefile.in | 1 + gcc-4.8/libffi/src/powerpc/ffi.c | 1480 +---- gcc-4.8/libffi/src/powerpc/ffi_linux64.c | 942 +++ gcc-4.8/libffi/src/powerpc/ffi_powerpc.h | 77 + gcc-4.8/libffi/src/powerpc/ffi_sysv.c | 931 +++ gcc-4.8/libffi/src/powerpc/ffitarget.h | 110 +- gcc-4.8/libffi/src/powerpc/linux64.S | 92 +- gcc-4.8/libffi/src/powerpc/linux64_closure.S | 319 +- gcc-4.8/libffi/src/powerpc/ppc_closure.S | 7 +- gcc-4.8/libffi/src/powerpc/sysv.S | 4 +- gcc-4.8/libffi/src/prep_cif.c | 4 + gcc-4.8/libffi/src/types.c | 15 + gcc-4.8/libffi/testsuite/Makefile.in | 1 + .../libffi/testsuite/libffi.call/cls_double_va.c | 16 +- .../testsuite/libffi.call/cls_longdouble_va.c | 17 +- gcc-4.8/libgcc/ChangeLog | 216 + gcc-4.8/libgcc/config.host | 10 +- gcc-4.8/libgcc/config/arm/sfp-machine.h | 10 +- gcc-4.8/libgcc/config/i386/cygming-crtbegin.c | 10 + gcc-4.8/libgcc/config/i386/sfp-exceptions.c | 34 +- gcc-4.8/libgcc/config/libbid/ChangeLog | 4 + gcc-4.8/libgcc/config/rs6000/ibm-ldouble.c | 11 +- gcc-4.8/libgcc/config/rs6000/linux-unwind.h | 51 +- gcc-4.8/libgcc/config/rs6000/tramp.S | 66 + gcc-4.8/libgcc/config/tilepro/atomic.c | 254 +- gcc-4.8/libgcc/unwind-seh.c | 5 +- gcc-4.8/libgfortran/ChangeLog | 76 + gcc-4.8/libgfortran/configure | 16 +- gcc-4.8/libgfortran/intrinsics/system_clock.c | 3 +- gcc-4.8/libgfortran/io/io.h | 10 +- gcc-4.8/libgfortran/io/list_read.c | 55 +- gcc-4.8/libgfortran/io/read.c | 8 +- gcc-4.8/libgfortran/io/unit.c | 68 +- gcc-4.8/libgfortran/io/write_float.def | 73 +- gcc-4.8/libgo/Makefile.am | 12 +- gcc-4.8/libgo/Makefile.in | 22 +- gcc-4.8/libgo/config.h.in | 15 + gcc-4.8/libgo/config/libtool.m4 | 12 +- gcc-4.8/libgo/configure | 18 +- gcc-4.8/libgo/configure.ac | 2 +- gcc-4.8/libgo/go/go/build/build.go | 2 +- gcc-4.8/libgo/go/go/build/syslist.go | 8 + gcc-4.8/libgo/go/net/fd_unix.go | 11 + gcc-4.8/libgo/go/reflect/all_test.go | 60 +- gcc-4.8/libgo/go/reflect/makefunc.go | 90 +- gcc-4.8/libgo/go/reflect/makefunc_386.S | 36 +- gcc-4.8/libgo/go/reflect/makefunc_amd64.S | 15 + gcc-4.8/libgo/go/reflect/makefuncgo_386.go | 24 +- gcc-4.8/libgo/go/reflect/makefuncgo_amd64.go | 2 +- gcc-4.8/libgo/go/reflect/type.go | 2 +- gcc-4.8/libgo/go/reflect/value.go | 43 +- gcc-4.8/libgo/go/syscall/libcall_linux.go | 15 + gcc-4.8/libgo/go/syscall/libcall_posix.go | 6 + gcc-4.8/libgo/go/syscall/socket.go | 2 +- gcc-4.8/libgo/mksysinfo.sh | 4 + gcc-4.8/libgo/runtime/go-callers.c | 9 + gcc-4.8/libgo/runtime/go-cdiv.c | 46 + gcc-4.8/libgo/runtime/go-defer.c | 1 + gcc-4.8/libgo/runtime/go-defer.h | 6 + gcc-4.8/libgo/runtime/go-int-array-to-string.c | 4 + gcc-4.8/libgo/runtime/go-make-slice.c | 5 +- gcc-4.8/libgo/runtime/go-nosys.c | 57 + gcc-4.8/libgo/runtime/go-recover.c | 77 +- gcc-4.8/libgo/runtime/go-reflect-call.c | 5 +- gcc-4.8/libgo/runtime/go-signal.c | 9 +- gcc-4.8/libgo/runtime/malloc.goc | 1 - gcc-4.8/libgo/runtime/mgc0.c | 6 +- gcc-4.8/libgo/runtime/mheap.c | 6 - gcc-4.8/libgo/runtime/proc.c | 32 +- gcc-4.8/libgo/runtime/runtime.h | 3 +- gcc-4.8/libgo/testsuite/gotest | 2 +- gcc-4.8/libgomp/ChangeLog | 22 + gcc-4.8/libgomp/config/linux/futex.h | 8 +- gcc-4.8/libgomp/configure | 16 +- gcc-4.8/libgomp/libgomp.info | 230 +- .../libgomp/testsuite/libgomp.fortran/crayptr2.f90 | 2 +- gcc-4.8/libiberty/ChangeLog | 4 + gcc-4.8/libitm/ChangeLog | 64 +- gcc-4.8/libitm/acinclude.m4 | 14 + gcc-4.8/libitm/beginend.cc | 10 + gcc-4.8/libitm/config/generic/asmcfi.h | 4 +- gcc-4.8/libitm/config/linux/futex_bits.h | 6 +- gcc-4.8/libitm/config/powerpc/sjlj.S | 24 +- gcc-4.8/libitm/config/powerpc/target.h | 82 + gcc-4.8/libitm/config/x86/target.h | 7 + gcc-4.8/libitm/configure | 54 +- gcc-4.8/libitm/configure.tgt | 5 +- gcc-4.8/libitm/libitm.info | 128 +- gcc-4.8/libitm/query.cc | 14 + gcc-4.8/libjava/ChangeLog | 24 + gcc-4.8/libjava/classpath/ChangeLog | 11 + gcc-4.8/libjava/classpath/ChangeLog.gcj | 6 + gcc-4.8/libjava/classpath/configure | 24 +- gcc-4.8/libjava/classpath/doc/cp-tools.info | 288 +- gcc-4.8/libjava/classpath/doc/gappletviewer.1 | 20 +- gcc-4.8/libjava/classpath/doc/gjar.1 | 20 +- gcc-4.8/libjava/classpath/doc/gjarsigner.1 | 20 +- gcc-4.8/libjava/classpath/doc/gjavah.1 | 20 +- gcc-4.8/libjava/classpath/doc/gjdoc.1 | 42 +- gcc-4.8/libjava/classpath/doc/gkeytool.1 | 20 +- gcc-4.8/libjava/classpath/doc/gnative2ascii.1 | 20 +- gcc-4.8/libjava/classpath/doc/gorbd.1 | 20 +- gcc-4.8/libjava/classpath/doc/grmid.1 | 20 +- gcc-4.8/libjava/classpath/doc/grmiregistry.1 | 20 +- gcc-4.8/libjava/classpath/doc/gserialver.1 | 20 +- gcc-4.8/libjava/classpath/doc/gtnameserv.1 | 20 +- .../gnu_java_awt_peer_gtk_FreetypeGlyphVector.c | 5 +- .../gtk-peer/gnu_java_awt_peer_gtk_GdkFontPeer.c | 9 +- gcc-4.8/libjava/configure | 18 +- gcc-4.8/libjava/java/lang/natObject.cc | 4 +- gcc-4.8/libjava/libltdl/ChangeLog | 12 + gcc-4.8/libjava/libltdl/acinclude.m4 | 12 +- gcc-4.8/libjava/libltdl/configure | 32 +- .../testsuite/libjava.lang/sourcelocation.xfail | 1 + gcc-4.8/libmudflap/ChangeLog | 11 + gcc-4.8/libmudflap/configure | 16 +- gcc-4.8/libobjc/ChangeLog | 11 + gcc-4.8/libobjc/configure | 18 +- gcc-4.8/libquadmath/ChangeLog | 11 + gcc-4.8/libquadmath/configure | 16 +- gcc-4.8/libquadmath/libquadmath.info | 36 +- gcc-4.8/libsanitizer/ChangeLog | 18 + gcc-4.8/libsanitizer/configure | 16 +- gcc-4.8/libsanitizer/configure.tgt | 3 + gcc-4.8/libssp/ChangeLog | 11 + gcc-4.8/libssp/configure | 16 +- gcc-4.8/libstdc++-v3/ChangeLog | 201 + gcc-4.8/libstdc++-v3/acinclude.m4 | 2 +- .../post/x86_64-linux-gnu/x32/baseline_symbols.txt | 17 + gcc-4.8/libstdc++-v3/configure | 34 +- gcc-4.8/libstdc++-v3/doc/html/api.html | 4 +- gcc-4.8/libstdc++-v3/doc/html/bk02.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/bk03.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/faq.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/index.html | 8 +- gcc-4.8/libstdc++-v3/doc/html/manual/abi.html | 18 +- .../libstdc++-v3/doc/html/manual/algorithms.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/manual/api.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/manual/appendix.html | 4 +- .../doc/html/manual/appendix_contributing.html | 8 +- .../doc/html/manual/appendix_free.html | 4 +- .../doc/html/manual/appendix_gfdl.html | 2 +- .../libstdc++-v3/doc/html/manual/appendix_gpl.html | 6 +- .../doc/html/manual/appendix_porting.html | 8 +- .../libstdc++-v3/doc/html/manual/associative.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/atomics.html | 6 +- .../libstdc++-v3/doc/html/manual/backwards.html | 8 +- .../doc/html/manual/bitmap_allocator.html | 4 +- .../doc/html/manual/bitmap_allocator_impl.html | 4 +- gcc-4.8/libstdc++-v3/doc/html/manual/bugs.html | 2 +- .../doc/html/manual/concept_checking.html | 2 +- .../libstdc++-v3/doc/html/manual/concurrency.html | 6 +- .../libstdc++-v3/doc/html/manual/configure.html | 2 +- .../libstdc++-v3/doc/html/manual/containers.html | 6 +- .../doc/html/manual/containers_and_c.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/debug.html | 4 +- .../libstdc++-v3/doc/html/manual/debug_mode.html | 4 +- .../doc/html/manual/debug_mode_design.html | 4 +- .../doc/html/manual/debug_mode_semantics.html | 2 +- .../doc/html/manual/debug_mode_using.html | 6 +- .../libstdc++-v3/doc/html/manual/diagnostics.html | 6 +- .../doc/html/manual/documentation_hacking.html | 15 +- .../doc/html/manual/dynamic_memory.html | 2 +- .../doc/html/manual/ext_algorithms.html | 2 +- .../doc/html/manual/ext_compile_checks.html | 2 +- .../doc/html/manual/ext_concurrency.html | 4 +- .../doc/html/manual/ext_concurrency_impl.html | 2 +- .../doc/html/manual/ext_concurrency_use.html | 2 +- .../doc/html/manual/ext_containers.html | 4 +- .../doc/html/manual/ext_demangling.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/ext_io.html | 4 +- .../doc/html/manual/ext_iterators.html | 2 +- .../libstdc++-v3/doc/html/manual/ext_numerics.html | 2 +- .../libstdc++-v3/doc/html/manual/ext_preface.html | 4 +- gcc-4.8/libstdc++-v3/doc/html/manual/ext_sgi.html | 2 +- .../doc/html/manual/ext_utilities.html | 2 +- .../libstdc++-v3/doc/html/manual/extensions.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/manual/facets.html | 58 +- gcc-4.8/libstdc++-v3/doc/html/manual/fstreams.html | 2 +- .../manual/generalized_numeric_operations.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/index.html | 24 +- .../libstdc++-v3/doc/html/manual/internals.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/intro.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/manual/io.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/manual/io_and_c.html | 2 +- .../libstdc++-v3/doc/html/manual/iterators.html | 6 +- gcc-4.8/libstdc++-v3/doc/html/manual/license.html | 2 +- .../libstdc++-v3/doc/html/manual/localization.html | 20 +- gcc-4.8/libstdc++-v3/doc/html/manual/make.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/memory.html | 46 +- .../libstdc++-v3/doc/html/manual/mt_allocator.html | 4 +- .../doc/html/manual/mt_allocator_design.html | 2 +- .../doc/html/manual/mt_allocator_ex_multi.html | 2 +- .../doc/html/manual/mt_allocator_ex_single.html | 2 +- .../doc/html/manual/mt_allocator_impl.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/numerics.html | 6 +- .../doc/html/manual/numerics_and_c.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/pairs.html | 2 +- .../doc/html/manual/parallel_mode.html | 8 +- .../doc/html/manual/parallel_mode_design.html | 2 +- .../doc/html/manual/parallel_mode_semantics.html | 2 +- .../doc/html/manual/parallel_mode_test.html | 2 +- .../doc/html/manual/parallel_mode_using.html | 4 +- .../manual/policy_based_data_structures_test.html | 2 +- .../doc/html/manual/policy_data_structures.html | 20 +- .../html/manual/policy_data_structures_ack.html | 5 +- .../html/manual/policy_data_structures_design.html | 68 +- .../html/manual/policy_data_structures_using.html | 4 +- .../libstdc++-v3/doc/html/manual/profile_mode.html | 6 +- .../doc/html/manual/profile_mode_api.html | 2 +- .../doc/html/manual/profile_mode_cost_model.html | 2 +- .../doc/html/manual/profile_mode_design.html | 4 +- .../doc/html/manual/profile_mode_devel.html | 2 +- .../doc/html/manual/profile_mode_diagnostics.html | 8 +- .../doc/html/manual/profile_mode_impl.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/setup.html | 4 +- .../doc/html/manual/source_code_style.html | 2 +- .../doc/html/manual/source_design_notes.html | 2 +- .../doc/html/manual/source_organization.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/status.html | 14 +- .../libstdc++-v3/doc/html/manual/std_contents.html | 8 +- .../libstdc++-v3/doc/html/manual/streambufs.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/strings.html | 6 +- .../doc/html/manual/stringstreams.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/support.html | 6 +- .../libstdc++-v3/doc/html/manual/termination.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/test.html | 4 +- gcc-4.8/libstdc++-v3/doc/html/manual/traits.html | 2 +- .../doc/html/manual/unordered_associative.html | 2 +- gcc-4.8/libstdc++-v3/doc/html/manual/using.html | 6 +- .../doc/html/manual/using_concurrency.html | 2 +- .../doc/html/manual/using_dynamic_or_shared.html | 2 +- .../doc/html/manual/using_exceptions.html | 18 +- .../doc/html/manual/using_headers.html | 14 +- .../libstdc++-v3/doc/html/manual/using_macros.html | 2 +- .../doc/html/manual/using_namespaces.html | 2 +- .../libstdc++-v3/doc/html/manual/utilities.html | 6 +- gcc-4.8/libstdc++-v3/doc/xml/faq.xml | 2 +- gcc-4.8/libstdc++-v3/doc/xml/manual/abi.xml | 3 + gcc-4.8/libstdc++-v3/doc/xml/manual/spine.xml | 1 + .../libstdc++-v3/doc/xml/manual/status_cxx2011.xml | 5 +- gcc-4.8/libstdc++-v3/include/bits/atomic_base.h | 4 +- .../libstdc++-v3/include/bits/shared_ptr_base.h | 6 +- gcc-4.8/libstdc++-v3/include/bits/stl_vector.h | 3 +- gcc-4.8/libstdc++-v3/include/c_global/cstdio | 1 + gcc-4.8/libstdc++-v3/include/debug/functions.h | 120 +- gcc-4.8/libstdc++-v3/include/debug/macros.h | 20 +- .../include/debug/safe_unordered_base.h | 12 +- gcc-4.8/libstdc++-v3/include/std/functional | 11 +- gcc-4.8/libstdc++-v3/include/std/future | 19 +- gcc-4.8/libstdc++-v3/include/std/iostream | 6 +- gcc-4.8/libstdc++-v3/include/std/tuple | 4 +- gcc-4.8/libstdc++-v3/libsupc++/eh_alloc.cc | 12 - gcc-4.8/libstdc++-v3/libsupc++/eh_throw.cc | 3 + gcc-4.8/libstdc++-v3/scripts/extract_symvers.in | 1 + gcc-4.8/libstdc++-v3/src/c++11/thread.cc | 2 +- .../libstdc++-v3/testsuite/20_util/bind/57899.cc | 48 + .../testsuite/20_util/function/60594.cc | 36 + .../testsuite/20_util/shared_ptr/cons/58839.cc | 33 + .../libstdc++-v3/testsuite/20_util/tuple/60497.cc | 35 + .../testsuite/23_containers/unordered_map/59548.cc | 34 + .../23_containers/vector/allocator/move.cc | 59 + .../23_containers/vector/allocator/move_assign.cc | 21 +- .../testsuite/29_atomics/atomic/60658.cc | 43 + .../testsuite/30_threads/packaged_task/60564.cc | 51 + gcc-4.8/libtool.m4 | 12 +- gcc-4.8/lto-plugin/ChangeLog | 11 + gcc-4.8/lto-plugin/configure | 16 +- gcc-4.8/maintainer-scripts/ChangeLog | 10 + gcc-4.8/maintainer-scripts/gcc_release | 4 +- gcc-4.8/zlib/ChangeLog | 11 + gcc-4.8/zlib/configure | 16 +- 1088 files changed, 60624 insertions(+), 14950 deletions(-) create mode 100644 gcc-4.8/gcc/ada/indepsw-darwin.adb create mode 100644 gcc-4.8/gcc/config/rs6000/crypto.md create mode 100644 gcc-4.8/gcc/config/rs6000/htm.md create mode 100644 gcc-4.8/gcc/config/rs6000/htmintrin.h create mode 100644 gcc-4.8/gcc/config/rs6000/htmxlintrin.h create mode 100644 gcc-4.8/gcc/config/rs6000/power8.md create mode 100644 gcc-4.8/gcc/config/rs6000/t-linux64bele create mode 100644 gcc-4.8/gcc/config/rs6000/t-linux64le create mode 100644 gcc-4.8/gcc/config/rs6000/t-linux64lebe create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-1.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-2.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-1.h create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-2.h create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/fold-divmul-1.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr58809.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr59467.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr36282-1.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr36282-2.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr36282-3.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr36282-4.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr37743.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr59032.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr59037.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr59280.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr60101.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/pr60689.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-1.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-2.c create mode 100644 gcc-4.8/gcc/testsuite/c-c++-common/torture/pr60026.c create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/access02.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/auto42.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/constexpr-template6.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/decltype57.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/defaulted48.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/deleted3.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/enum_base2.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist76.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist78.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist79.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist81.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/initlist82.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/lambda/lambda-nsdmi5.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/noexcept22.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/nsdmi-union3.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/nsdmi9.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/static_assert9.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic144.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic145.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic147.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic148.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic149.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/cpp0x/variadic150.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/diagnostic/pedantic.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/diagnostic/pr58979.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/diagnostic/pr59838.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/eh/ppc64-sighandle-cr.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/eh/uncaught4.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/attrib48.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/builtin-bswap1.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/stmtexpr15.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/timevar2.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/traits1.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/vector25.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ext/vector27.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/gomp/for-20.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/gomp/pr59297.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/inherit/virtual11.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60419.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60640-1.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60640-2.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/ipa/pr60640-3.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/opt/pr58864.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/opt/pr59470.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/opt/pr59647.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/opt/pr60849.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/overload/defarg8.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/pr60769.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/template/partial15.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/template/ref7.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/template/shadow1.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/template/using27.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/template/using28.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/template/using29.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/tls/thread_local-ice2.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/tls/thread_local8.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/tm/noexcept-6.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/tm/pr60004.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/torture/pr57499.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/torture/pr59163.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/torture/pr60609.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/torture/pr60750.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/torture/pr60895.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/tree-prof/pr59255.C create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/vect/pr60729.cc create mode 100644 gcc-4.8/gcc/testsuite/g++.dg/vect/pr60836.cc create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/compile/pr58970-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/compile/pr58970-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/compile/pr58997.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/compile/pr59362.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/compile/pr59803.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/compile/pr60502.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/20131127-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/20140212-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/20140326-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/20140425-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr58726.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr58831.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr58984.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr59014-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr59014.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr59101.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr59358.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr59388.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr60017.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr60062.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr60072.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr60454.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.c-torture/execute/pr60960.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/atomic-store-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/builtin-object-size-14.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2-macro2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/gomp/pr58809.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr55022.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr59817-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr59817-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/graphite/pr60740.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/guality/pr59776.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/ipa/pr55260.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/ipa/pr59610.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr56824.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr58668.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr58805.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr59011.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr59351.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr59827.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr59860.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr60485-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/pr60485-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/tls/pr58595.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57425-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57425-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57425-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57488.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57517.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57569.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr57864.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58079.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58143-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58143-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58143-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58779.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58830.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58941.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr58956.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59047.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59139.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59164.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59288.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59330.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59715.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59891.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr59903.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60115.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60183.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60766.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60903.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/torture/pr60930.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/tree-ssa/predcom-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/tree-ssa/predcom-7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/unused-8b.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vect/pr60276.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vect/pr60382.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/extract-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/extract-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/extract-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/extract.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/insert.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ld.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/lde-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/lde.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ldl.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/merge.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/mult-even-odd-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/mult-even-odd.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/pack-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/pack.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/perm-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/perm.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/splat.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/st-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/st-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/st-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/st.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ste-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/ste.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl-vsx-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/stl.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/sum2s-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/sum2s.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/unpack-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/unpack.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/vec-set.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/vsums-be-order.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.dg/vmx/vsums.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/neon/vst1Q_laneu64-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/pr54300.C create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/pr57637.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/pr59826.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/require-pic-register-loc.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/thumb1-pic-high-reg.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/thumb1-pic-single-base.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/arm/vrinta-ce.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/avr/pr60991.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/avr/torture/pr61055.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/nest-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr43546.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr54694.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr58137.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr58690.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59021.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59034-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59034-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59405.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59470.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59625.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59794-7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59839.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr59929.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr60516.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr60693.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr60700.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr60909-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/pr60909-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/i386/xop-frczX.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/microblaze/isa/fcmp4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/microblaze/others/builtin-trap.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/microblaze/others/mem_reload.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/bswap-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/mips/pr59137.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/altivec-perm-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic-p8.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/atomic_load_store-p8.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bcd-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-av.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2-p8.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool2.h create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-av.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3-p8.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/bool3.h create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/crypto-builtin-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-builtin-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-dd-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/dfp-td-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-double2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-float2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-long2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move-vint2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/direct-move.h create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/extend-divide-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/fusion.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-builtin-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/htm-xl-intrin-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/mmfpgpr.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-fp.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-int128-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-ldst.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vbpermq.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack01.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack02.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pack03.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57744.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr57949-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr58673-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr59054.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60137.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60203.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/pr60735.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/quad-atomic.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/rs6000-ldouble-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-pwr6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/sd-vsx.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/ti_math2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/powerpc/vsx-float0.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-10.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-11.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-12.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-8.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-9.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/hotpatch-compile-8.c delete mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-builtins-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-builtins-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-builtins-compile-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-builtins-compile-3.c delete mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-nofloat-2.c create mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-nofloat-compile-1.c delete mode 100644 gcc-4.8/gcc/testsuite/gcc.target/s390/htm-xl-intrin-1.c create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/allocate_class_3.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/arrayio_13.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/constructor_9.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/default_initialization_7.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/derived_external_function_1.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/dynamic_dispatch_12.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/elemental_subroutine_9.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/extends_15.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/fmt_en.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/fmt_g_1.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/generic_28.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/gomp/pr59467.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/graphite/pr59817.f create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/ichar_3.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/implicit_pure_4.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/init_flag_12.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/list_read_12.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/lto/pr60635_0.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/lto/pr60635_1.c create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/optional_class_1.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/pr52370.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/pr59700.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_43.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_45.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_46.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/proc_ptr_comp_38.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/reshape_6.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/shape_8.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/str_comp_optimize_1.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/typebound_generic_15.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/unlimited_polymorphic_15.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/unresolved_fixup_1.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/unresolved_fixup_2.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.dg/where_4.f90 create mode 100644 gcc-4.8/gcc/testsuite/gfortran.fortran-torture/compile/pr57517.f90 create mode 100644 gcc-4.8/gcc/testsuite/gnat.dg/opt32.adb create mode 100644 gcc-4.8/libcpp/po/pt_BR.gmo create mode 100644 gcc-4.8/libcpp/po/pt_BR.po create mode 100644 gcc-4.8/libffi/src/powerpc/ffi_linux64.c create mode 100644 gcc-4.8/libffi/src/powerpc/ffi_powerpc.h create mode 100644 gcc-4.8/libffi/src/powerpc/ffi_sysv.c create mode 100644 gcc-4.8/libgo/go/go/build/syslist.go create mode 100644 gcc-4.8/libgo/runtime/go-cdiv.c create mode 100644 gcc-4.8/libjava/testsuite/libjava.lang/sourcelocation.xfail create mode 100644 gcc-4.8/libstdc++-v3/testsuite/20_util/bind/57899.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/20_util/function/60594.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/20_util/shared_ptr/cons/58839.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/20_util/tuple/60497.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/23_containers/unordered_map/59548.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/23_containers/vector/allocator/move.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/29_atomics/atomic/60658.cc create mode 100644 gcc-4.8/libstdc++-v3/testsuite/30_threads/packaged_task/60564.cc (limited to 'gcc-4.8') diff --git a/gcc-4.8/ChangeLog b/gcc-4.8/ChangeLog index 5358ac27f..0ed008342 100644 --- a/gcc-4.8/ChangeLog +++ b/gcc-4.8/ChangeLog @@ -1,3 +1,25 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-15 Ulrich Weigand + + * libtool.m4: Update to mainline version. + * configure: Regenerate. + +2014-04-04 Bill Schmidt + + Backport from mainline r203071: + + 2013-10-01 Joern Rennecke + + Import from savannah.gnu.org: + * config.guess: Update to 2013-06-10 version. + * config.sub: Update to 2013-10-01 version. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/ChangeLog.backported b/gcc-4.8/ChangeLog.backported index f92f0f945..d93a35b82 100644 --- a/gcc-4.8/ChangeLog.backported +++ b/gcc-4.8/ChangeLog.backported @@ -19,14 +19,6 @@ libstdc++-v3/ Copy comment for this case from eh_personality.cc:__cxa_call_unexpected. * testsuite/18_support/bad_exception/59392.cc: New file. -http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=205720 -2013-12-05 Jason Merrill - - PR c++/59044 - PR c++/59052 - * pt.c (most_specialized_class): Use the partially instantiated - template for deduction. Drop the TMPL parameter. - http://gcc.gnu.org/viewcvs?rev=203874&root=gcc&view=rev 2013-10-20 Chris Jefferson Paolo Carlini diff --git a/gcc-4.8/INSTALL/binaries.html b/gcc-4.8/INSTALL/binaries.html index 9ffb75b38..ccd8b3d43 100644 --- a/gcc-4.8/INSTALL/binaries.html +++ b/gcc-4.8/INSTALL/binaries.html @@ -3,7 +3,7 @@ Installing GCC: Binaries - + recommended to use the GNU assembler instead. There is no bundled @@ -564,9 +564,9 @@ later.

None of the following versions of GCC has an ABI that is compatible with any of the other versions in this list, with the exception that Red Hat 2.96 and Trillian 000171 are compatible with each other: -3.1, 3.0.2, 3.0.1, 3.0, Red Hat 2.96, and Trillian 000717. -This primarily affects C++ programs and programs that create shared libraries. -GCC 3.1 or later is recommended for compiling linux, the kernel. +3.1, 3.0.2, 3.0.1, 3.0, Red Hat 2.96, and Trillian 000717. +This primarily affects C++ programs and programs that create shared libraries. +GCC 3.1 or later is recommended for compiling linux, the kernel. As of version 3.1 GCC is believed to be fully ABI compliant, and hence no more major ABI changes are expected. @@ -580,7 +580,7 @@ the option --with-gnu-as may be necessa

The GCC libunwind library has not been ported to HPUX. This means that for GCC versions 3.2.3 and earlier, --enable-libunwind-exceptions -is required to build GCC. For GCC 3.3 and later, this is the default. +is required to build GCC. For GCC 3.3 and later, this is the default. For gcc 3.4.3 and later, --enable-libunwind-exceptions is removed and the system libunwind library will always be used. @@ -589,7 +589,7 @@ removed and the system libunwind library will always be used.

*-ibm-aix*

-

Support for AIX version 3 and older was discontinued in GCC 3.4. +

Support for AIX version 3 and older was discontinued in GCC 3.4. Support for AIX version 4.2 and older was discontinued in GCC 4.5.

“out of memory” bootstrap failures may indicate a problem with @@ -686,7 +686,7 @@ executable.

AIX 4.3 utilizes a “large format” archive to support both 32-bit and 64-bit object modules. The routines provided in AIX 4.3.0 and AIX 4.3.1 -to parse archive libraries did not handle the new format correctly. +to parse archive libraries did not handle the new format correctly. These routines are used by GCC and result in error messages during linking such as “not a COFF file”. The version of the routines shipped with AIX 4.3.1 should work for a 32-bit environment. The -g @@ -736,28 +736,28 @@ applications. There are no standard Unix configurations.

lm32-*-elf

-

Lattice Mico32 processor. +

Lattice Mico32 processor. This configuration is intended for embedded systems.

lm32-*-uclinux

-

Lattice Mico32 processor. +

Lattice Mico32 processor. This configuration is intended for embedded systems running uClinux.

m32c-*-elf

-

Renesas M32C processor. +

Renesas M32C processor. This configuration is intended for embedded systems.

m32r-*-elf

-

Renesas M32R processor. +

Renesas M32R processor. This configuration is intended for embedded systems.

@@ -801,14 +801,14 @@ both of which were ABI changes.

mep-*-elf

-

Toshiba Media embedded Processor. +

Toshiba Media embedded Processor. This configuration is intended for embedded systems.

microblaze-*-elf

-

Xilinx MicroBlaze processor. +

Xilinx MicroBlaze processor. This configuration is intended for embedded systems.

@@ -963,7 +963,7 @@ the PSIM simulator.

rl78-*-elf

-

The Renesas RL78 processor. +

The Renesas RL78 processor. This configuration is intended for embedded systems.

@@ -1051,7 +1051,7 @@ are known to work as well. Note that your mileage may vary if you use a combination of the GNU tools and the Sun tools: while the combination GNU as + Sun ld should reasonably work, the reverse combination Sun as + GNU ld may fail to -build or cause memory corruption at runtime in some cases for C++ programs. +build or cause memory corruption at runtime in some cases for C++ programs. GNU ld usually works as well, although the version included in Solaris 10 cannot be used due to several bugs. Again, the current @@ -1148,13 +1148,13 @@ compiler. This is Sun bug 4974440. This is fixed with patch 112760-07.

GCC 3.4 changed the default debugging format from Stabs to DWARF-2 for 32-bit code on Solaris 7 and later. If you use the Sun assembler, this change apparently runs afoul of Sun bug 4910101 (which is referenced as -an x86-only problem by Sun, probably because they do not use DWARF-2). +an x86-only problem by Sun, probably because they do not use DWARF-2). A symptom of the problem is that you cannot compile C++ programs like groff 1.19.1 without getting messages similar to the following: 

     ld: warning: relocation error: R_SPARC_UA32: ...
-       external symbolic relocation against non-allocatable section
-       .debug_info cannot be processed at runtime: relocation ignored.
+  external symbolic relocation against non-allocatable section
+  .debug_info cannot be processed at runtime: relocation ignored.

To work around this problem, compile with -gstabs+ instead of plain -g. @@ -1175,7 +1175,7 @@ not that of GMP or MPFR or MPC). For example on a Solaris 9 system: thread-local storage (TLS). A typical error message is 

     ld: fatal: relocation error: R_SPARC_TLS_LE_HIX22: file /var/tmp//ccamPA1v.o:
-       symbol <unknown>: bad symbol type SECT: symbol type must be TLS
+  symbol <unknown>: bad symbol type SECT: symbol type must be TLS

This bug is fixed in Sun patch 118683-03 or later. @@ -1237,8 +1237,8 @@ binutils-2.22 or newer.

*-*-vxworks*

Support for VxWorks is in flux. At present GCC supports only the -very recent VxWorks 5.5 (aka Tornado 2.2) release, and only on PowerPC. -We welcome patches for other architectures supported by VxWorks 5.5. +very recent VxWorks 5.5 (aka Tornado 2.2) release, and only on PowerPC. +We welcome patches for other architectures supported by VxWorks 5.5. Support for VxWorks AE would also be welcome; we believe this is merely a matter of writing an appropriate “configlette” (see below). We are not interested in supporting older, a.out or COFF-based, versions of @@ -1246,7 +1246,7 @@ VxWorks in GCC 3.

VxWorks comes with an older version of GCC installed in $WIND_BASE/host; we recommend you do not overwrite it. -Choose an installation prefix entirely outside $WIND_BASE. +Choose an installation prefix entirely outside $WIND_BASE. Before running configure, create the directories prefix and prefix/bin. Link or copy the appropriate assembler, linker, etc. into prefix/bin, and set your PATH to @@ -1272,7 +1272,7 @@ VxWorks will incorporate this module.)

x86_64-*-*, amd64-*-*

GCC supports the x86-64 architecture implemented by the AMD64 processor -(amd64-*-* is an alias for x86_64-*-*) on GNU/Linux, FreeBSD and NetBSD. +(amd64-*-* is an alias for x86_64-*-*) on GNU/Linux, FreeBSD and NetBSD. On GNU/Linux the default is a bi-arch compiler which is able to generate both 64-bit x86-64 and 32-bit x86 code (via the -m32 switch). @@ -1340,19 +1340,19 @@ and which C libraries are used.

  • Cygwin *-*-cygwin: Cygwin provides a user-space -Linux API emulation layer in the Win32 subsystem. +Linux API emulation layer in the Win32 subsystem.
  • Interix *-*-interix: The Interix subsystem -provides native support for POSIX. +provides native support for POSIX.
  • MinGW *-*-mingw32: MinGW is a native GCC port for -the Win32 subsystem that provides a subset of POSIX. +the Win32 subsystem that provides a subset of POSIX.
  • MKS i386-pc-mks: NuTCracker from MKS. See -http://www.mkssoftware.com/ for more information. +http://www.mkssoftware.com/ for more information.

Intel 64-bit versions

GCC contains support for x86-64 using the mingw-w64 -runtime library, available from http://mingw-w64.sourceforge.net/. +runtime library, available from http://mingw-w64.sourceforge.net/. This library should be used with the target triple x86_64-pc-mingw32.

Presently Windows for Itanium is not supported. @@ -1405,7 +1405,7 @@ the Win32 subsystem. This target was last known to work in GCC 3.3.

*-*-mingw32

-

GCC will build with and support only MinGW runtime 3.12 and later. +

GCC will build with and support only MinGW runtime 3.12 and later. Earlier versions of headers are incompatible with the new default semantics of extern inline in -std=c99 and -std=gnu99 modes. diff --git a/gcc-4.8/INSTALL/test.html b/gcc-4.8/INSTALL/test.html index 1a104438e..8bc6b29a2 100644 --- a/gcc-4.8/INSTALL/test.html +++ b/gcc-4.8/INSTALL/test.html @@ -3,7 +3,7 @@ Installing GCC: Testing - + +---------------------------------------+ + | Back chain to caller | 0 + +---------------------------------------+ + | Save area for CR | 8 + +---------------------------------------+ + | Saved LR | 16 + +---------------------------------------+ + | Saved TOC pointer | 24 + +---------------------------------------+ + | Parameter save area (P) | 32 + +---------------------------------------+ + | Alloca space (A) | 32+P + +---------------------------------------+ + | Local variable space (L) | 32+P+A + +---------------------------------------+ + | Save area for AltiVec registers (W) | 32+P+A+L + +---------------------------------------+ + | AltiVec alignment padding (Y) | 32+P+A+L+W + +---------------------------------------+ + | Save area for GP registers (G) | 32+P+A+L+W+Y + +---------------------------------------+ + | Save area for FP registers (F) | 32+P+A+L+W+Y+G + +---------------------------------------+ + old SP->| back chain to caller's caller | 32+P+A+L+W+Y+G+F + +---------------------------------------+ + V.4 stack frames look like: @@ -17897,6 +21010,7 @@ rs6000_stack_info (void) rs6000_stack_t *info_ptr = &stack_info; int reg_size = TARGET_32BIT ? 4 : 8; int ehrd_size; + int ehcr_size; int save_align; int first_gp; HOST_WIDE_INT non_fixed_size; @@ -17990,6 +21104,18 @@ rs6000_stack_info (void) else ehrd_size = 0; + /* In the ELFv2 ABI, we also need to allocate space for separate + CR field save areas if the function calls __builtin_eh_return. */ + if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return) + { + /* This hard-codes that we have three call-saved CR fields. */ + ehcr_size = 3 * reg_size; + /* We do *not* use the regular CR save mechanism. */ + info_ptr->cr_save_p = 0; + } + else + ehcr_size = 0; + /* Determine various sizes. */ info_ptr->reg_size = reg_size; info_ptr->fixed_size = RS6000_SAVE_AREA; @@ -18029,6 +21155,7 @@ rs6000_stack_info (void) gcc_unreachable (); case ABI_AIX: + case ABI_ELFv2: case ABI_DARWIN: info_ptr->fp_save_offset = - info_ptr->fp_size; info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; @@ -18058,6 +21185,8 @@ rs6000_stack_info (void) } else info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size; + + info_ptr->ehcr_offset = info_ptr->ehrd_offset - ehcr_size; info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */ info_ptr->lr_save_offset = 2*reg_size; break; @@ -18120,6 +21249,7 @@ rs6000_stack_info (void) + info_ptr->spe_gp_size + info_ptr->spe_padding_size + ehrd_size + + ehcr_size + info_ptr->cr_size + info_ptr->vrsave_size, save_align); @@ -18133,7 +21263,7 @@ rs6000_stack_info (void) /* Determine if we need to save the link register. */ if (info_ptr->calls_p - || (DEFAULT_ABI == ABI_AIX + || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && crtl->profile && !TARGET_PROFILE_KERNEL) || (DEFAULT_ABI == ABI_V4 && cfun->calls_alloca) @@ -18279,6 +21409,7 @@ debug_stack_info (rs6000_stack_t *info) default: abi_string = "Unknown"; break; case ABI_NONE: abi_string = "NONE"; break; case ABI_AIX: abi_string = "AIX"; break; + case ABI_ELFv2: abi_string = "ELFv2"; break; case ABI_DARWIN: abi_string = "Darwin"; break; case ABI_V4: abi_string = "V.4"; break; } @@ -18400,7 +21531,8 @@ rs6000_return_addr (int count, rtx frame) /* Currently we don't optimize very well between prolog and body code and for PIC code the code can be actually quite bad, so don't try to be too clever here. */ - if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic)) + if (count != 0 + || ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN) && flag_pic)) { cfun->machine->ra_needs_full_frame = 1; @@ -18459,13 +21591,13 @@ rs6000_function_ok_for_sibcall (tree decl, tree exp) return false; } - /* Under the AIX ABI we can't allow calls to non-local functions, - because the callee may have a different TOC pointer to the - caller and there's no way to ensure we restore the TOC when we - return. With the secure-plt SYSV ABI we can't make non-local + /* Under the AIX or ELFv2 ABIs we can't allow calls to non-local + functions, because the callee may have a different TOC pointer to + the caller and there's no way to ensure we restore the TOC when + we return. With the secure-plt SYSV ABI we can't make non-local calls when -fpic/PIC because the plt call stubs use r30. */ if (DEFAULT_ABI == ABI_DARWIN - || (DEFAULT_ABI == ABI_AIX + || ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && decl && !DECL_EXTERNAL (decl) && (*targetm.binds_local_p) (decl)) @@ -18566,7 +21698,7 @@ rs6000_emit_load_toc_table (int fromprolog) rtx dest; dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); - if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic) + if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic) { char buf[30]; rtx lab, tmp1, tmp2, got; @@ -18594,7 +21726,7 @@ rs6000_emit_load_toc_table (int fromprolog) emit_insn (gen_load_toc_v4_pic_si ()); emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO)); } - else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) + else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2) { char buf[30]; rtx temp0 = (fromprolog @@ -18642,7 +21774,7 @@ rs6000_emit_load_toc_table (int fromprolog) } else { - gcc_assert (DEFAULT_ABI == ABI_AIX); + gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2); if (TARGET_32BIT) emit_insn (gen_load_toc_aix_si (dest)); @@ -19047,7 +22179,7 @@ output_probe_stack_range (rtx reg1, rtx reg2) static rtx rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, - rtx reg2, rtx rreg) + rtx reg2, rtx rreg, rtx split_reg) { rtx real, temp; @@ -19138,6 +22270,11 @@ rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val, } } + /* If a store insn has been split into multiple insns, the + true source register is given by split_reg. */ + if (split_reg != NULL_RTX) + real = gen_rtx_SET (VOIDmode, SET_DEST (real), split_reg); + RTX_FRAME_RELATED_P (insn) = 1; add_reg_note (insn, REG_FRAME_RELATED_EXPR, real); @@ -19245,7 +22382,7 @@ emit_frame_save (rtx frame_reg, enum machine_mode mode, reg = gen_rtx_REG (mode, regno); insn = emit_insn (gen_frame_store (reg, frame_reg, offset)); return rs6000_frame_related (insn, frame_reg, frame_reg_to_sp, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); } /* Emit an offset memory reference suitable for a frame store, while @@ -19361,7 +22498,7 @@ rs6000_savres_routine_name (rs6000_stack_t *info, int regno, int sel) if ((sel & SAVRES_LR)) suffix = "_x"; } - else if (DEFAULT_ABI == ABI_AIX) + else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) { #if !defined (POWERPC_LINUX) && !defined (POWERPC_FREEBSD) /* No out-of-line save/restore routines for GPRs on AIX. */ @@ -19502,7 +22639,7 @@ rs6000_emit_stack_reset (rs6000_stack_t *info, static inline unsigned ptr_regno_for_savres (int sel) { - if (DEFAULT_ABI == ABI_AIX) + if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) return (sel & SAVRES_REG) == SAVRES_FPR || (sel & SAVRES_LR) ? 1 : 12; return DEFAULT_ABI == ABI_DARWIN && (sel & SAVRES_REG) == SAVRES_FPR ? 1 : 11; } @@ -19587,6 +22724,43 @@ rs6000_emit_savres_rtx (rs6000_stack_t *info, return insn; } +/* Emit code to store CR fields that need to be saved into REG. */ + +static void +rs6000_emit_move_from_cr (rtx reg) +{ + /* Only the ELFv2 ABI allows storing only selected fields. */ + if (DEFAULT_ABI == ABI_ELFv2 && TARGET_MFCRF) + { + int i, cr_reg[8], count = 0; + + /* Collect CR fields that must be saved. */ + for (i = 0; i < 8; i++) + if (save_reg_p (CR0_REGNO + i)) + cr_reg[count++] = i; + + /* If it's just a single one, use mfcrf. */ + if (count == 1) + { + rtvec p = rtvec_alloc (1); + rtvec r = rtvec_alloc (2); + RTVEC_ELT (r, 0) = gen_rtx_REG (CCmode, CR0_REGNO + cr_reg[0]); + RTVEC_ELT (r, 1) = GEN_INT (1 << (7 - cr_reg[0])); + RTVEC_ELT (p, 0) + = gen_rtx_SET (VOIDmode, reg, + gen_rtx_UNSPEC (SImode, r, UNSPEC_MOVESI_FROM_CR)); + + emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); + return; + } + + /* ??? It might be better to handle count == 2 / 3 cases here + as well, using logical operations to combine the values. */ + } + + emit_insn (gen_movesi_from_cr (reg)); +} + /* Determine whether the gp REG is really used. */ static bool @@ -19652,6 +22826,17 @@ rs6000_emit_prologue (void) #define NOT_INUSE(R) do {} while (0) #endif + if (DEFAULT_ABI == ABI_ELFv2) + { + cfun->machine->r2_setup_needed = df_regs_ever_live_p (TOC_REGNUM); + + /* With -mminimal-toc we may generate an extra use of r2 below. */ + if (!TARGET_SINGLE_PIC_BASE + && TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0) + cfun->machine->r2_setup_needed = true; + } + + if (flag_stack_usage_info) current_function_static_stack_size = info->total_size; @@ -19766,7 +22951,7 @@ rs6000_emit_prologue (void) insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, - treg, GEN_INT (-info->total_size)); + treg, GEN_INT (-info->total_size), NULL_RTX); sp_off = frame_off = info->total_size; } @@ -19851,14 +23036,14 @@ rs6000_emit_prologue (void) insn = emit_move_insn (mem, reg); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); END_USE (0); } } /* If we need to save CR, put it into r12 or r11. Choose r12 except when r12 will be needed by out-of-line gpr restore. */ - cr_save_regno = (DEFAULT_ABI == ABI_AIX + cr_save_regno = ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && !(strategy & (SAVE_INLINE_GPRS | SAVE_NOINLINE_GPRS_SAVES_LR)) ? 11 : 12); @@ -19867,21 +23052,9 @@ rs6000_emit_prologue (void) && REGNO (frame_reg_rtx) != cr_save_regno && !(using_static_chain_p && cr_save_regno == 11)) { - rtx set; - cr_save_rtx = gen_rtx_REG (SImode, cr_save_regno); START_USE (cr_save_regno); - insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); - RTX_FRAME_RELATED_P (insn) = 1; - /* Now, there's no way that dwarf2out_frame_debug_expr is going - to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'. - But that's OK. All we have to do is specify that _one_ condition - code register is saved in this stack slot. The thrower's epilogue - will then restore all the call-saved registers. - We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */ - set = gen_rtx_SET (VOIDmode, cr_save_rtx, - gen_rtx_REG (SImode, CR2_REGNO)); - add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); + rs6000_emit_move_from_cr (cr_save_rtx); } /* Do any required saving of fpr's. If only one or two to save, do @@ -19919,7 +23092,7 @@ rs6000_emit_prologue (void) info->lr_save_offset, DFmode, sel); rs6000_frame_related (insn, ptr_reg, sp_off, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); if (lr) END_USE (0); } @@ -19998,7 +23171,7 @@ rs6000_emit_prologue (void) SAVRES_SAVE | SAVRES_GPR); rs6000_frame_related (insn, spe_save_area_ptr, sp_off - save_off, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); } /* Move the static chain pointer back. */ @@ -20048,7 +23221,7 @@ rs6000_emit_prologue (void) info->lr_save_offset + ptr_off, reg_mode, sel); rs6000_frame_related (insn, ptr_reg, sp_off - ptr_off, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); if (lr) END_USE (0); } @@ -20064,7 +23237,7 @@ rs6000_emit_prologue (void) info->gp_save_offset + frame_off + reg_size * i); insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); } else if (!WORLD_SAVE_P (info)) { @@ -20133,7 +23306,8 @@ rs6000_emit_prologue (void) be updated if we arrived at this function via a plt call or toc adjusting stub. */ emit_move_insn (tmp_reg_si, gen_rtx_MEM (SImode, tmp_reg)); - toc_restore_insn = TARGET_32BIT ? 0x80410014 : 0xE8410028; + toc_restore_insn = ((TARGET_32BIT ? 0x80410000 : 0xE8410000) + + RS6000_TOC_SAVE_SLOT); hi = gen_int_mode (toc_restore_insn & ~0xffff, SImode); emit_insn (gen_xorsi3 (tmp_reg_si, tmp_reg_si, hi)); compare_result = gen_rtx_REG (CCUNSmode, CR0_REGNO); @@ -20152,7 +23326,7 @@ rs6000_emit_prologue (void) LABEL_NUSES (toc_save_done) += 1; save_insn = emit_frame_save (frame_reg_rtx, reg_mode, - TOC_REGNUM, frame_off + 5 * reg_size, + TOC_REGNUM, frame_off + RS6000_TOC_SAVE_SLOT, sp_off - frame_off); emit_label (toc_save_done); @@ -20192,26 +23366,121 @@ rs6000_emit_prologue (void) rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (info->cr_save_offset + frame_off)); rtx mem = gen_frame_mem (SImode, addr); - /* See the large comment above about why CR2_REGNO is used. */ - rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO); /* If we didn't copy cr before, do so now using r0. */ if (cr_save_rtx == NULL_RTX) { - rtx set; - START_USE (0); cr_save_rtx = gen_rtx_REG (SImode, 0); - insn = emit_insn (gen_movesi_from_cr (cr_save_rtx)); + rs6000_emit_move_from_cr (cr_save_rtx); + } + + /* Saving CR requires a two-instruction sequence: one instruction + to move the CR to a general-purpose register, and a second + instruction that stores the GPR to memory. + + We do not emit any DWARF CFI records for the first of these, + because we cannot properly represent the fact that CR is saved in + a register. One reason is that we cannot express that multiple + CR fields are saved; another reason is that on 64-bit, the size + of the CR register in DWARF (4 bytes) differs from the size of + a general-purpose register. + + This means if any intervening instruction were to clobber one of + the call-saved CR fields, we'd have incorrect CFI. To prevent + this from happening, we mark the store to memory as a use of + those CR fields, which prevents any such instruction from being + scheduled in between the two instructions. */ + rtx crsave_v[9]; + int n_crsave = 0; + int i; + + crsave_v[n_crsave++] = gen_rtx_SET (VOIDmode, mem, cr_save_rtx); + for (i = 0; i < 8; i++) + if (save_reg_p (CR0_REGNO + i)) + crsave_v[n_crsave++] + = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i)); + + insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec_v (n_crsave, crsave_v))); + END_USE (REGNO (cr_save_rtx)); + + /* Now, there's no way that dwarf2out_frame_debug_expr is going to + understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)', + so we need to construct a frame expression manually. */ RTX_FRAME_RELATED_P (insn) = 1; - set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg); + + /* Update address to be stack-pointer relative, like + rs6000_frame_related would do. */ + addr = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM), + GEN_INT (info->cr_save_offset + sp_off)); + mem = gen_frame_mem (SImode, addr); + + if (DEFAULT_ABI == ABI_ELFv2) + { + /* In the ELFv2 ABI we generate separate CFI records for each + CR field that was actually saved. They all point to the + same 32-bit stack slot. */ + rtx crframe[8]; + int n_crframe = 0; + + for (i = 0; i < 8; i++) + if (save_reg_p (CR0_REGNO + i)) + { + crframe[n_crframe] + = gen_rtx_SET (VOIDmode, mem, + gen_rtx_REG (SImode, CR0_REGNO + i)); + + RTX_FRAME_RELATED_P (crframe[n_crframe]) = 1; + n_crframe++; + } + + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_rtx_PARALLEL (VOIDmode, + gen_rtvec_v (n_crframe, crframe))); + } + else + { + /* In other ABIs, by convention, we use a single CR regnum to + represent the fact that all call-saved CR fields are saved. + We use CR2_REGNO to be compatible with gcc-2.95 on Linux. */ + rtx set = gen_rtx_SET (VOIDmode, mem, + gen_rtx_REG (SImode, CR2_REGNO)); add_reg_note (insn, REG_FRAME_RELATED_EXPR, set); } - insn = emit_move_insn (mem, cr_save_rtx); - END_USE (REGNO (cr_save_rtx)); + } - rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, - NULL_RTX, NULL_RTX); + /* In the ELFv2 ABI we need to save all call-saved CR fields into + *separate* slots if the routine calls __builtin_eh_return, so + that they can be independently restored by the unwinder. */ + if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return) + { + int i, cr_off = info->ehcr_offset; + rtx crsave; + + /* ??? We might get better performance by using multiple mfocrf + instructions. */ + crsave = gen_rtx_REG (SImode, 0); + emit_insn (gen_movesi_from_cr (crsave)); + + for (i = 0; i < 8; i++) + if (!call_used_regs[CR0_REGNO + i]) + { + rtvec p = rtvec_alloc (2); + RTVEC_ELT (p, 0) + = gen_frame_store (crsave, frame_reg_rtx, cr_off + frame_off); + RTVEC_ELT (p, 1) + = gen_rtx_USE (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO + i)); + + insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); + + RTX_FRAME_RELATED_P (insn) = 1; + add_reg_note (insn, REG_FRAME_RELATED_EXPR, + gen_frame_store (gen_rtx_REG (SImode, CR0_REGNO + i), + sp_reg_rtx, cr_off + sp_off)); + + cr_off += reg_size; + } } /* Update stack and set back pointer unless this is V.4, @@ -20291,7 +23560,7 @@ rs6000_emit_prologue (void) info->altivec_save_offset + ptr_off, 0, V4SImode, SAVRES_SAVE | SAVRES_VR); rs6000_frame_related (insn, scratch_reg, sp_off - ptr_off, - NULL_RTX, NULL_RTX); + NULL_RTX, NULL_RTX, NULL_RTX); if (REGNO (frame_reg_rtx) == REGNO (scratch_reg)) { /* The oddity mentioned above clobbered our frame reg. */ @@ -20307,7 +23576,7 @@ rs6000_emit_prologue (void) for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i) if (info->vrsave_mask & ALTIVEC_REG_BIT (i)) { - rtx areg, savereg, mem; + rtx areg, savereg, mem, split_reg; int offset; offset = (info->altivec_save_offset + frame_off @@ -20325,8 +23594,18 @@ rs6000_emit_prologue (void) insn = emit_move_insn (mem, savereg); + /* When we split a VSX store into two insns, we need to make + sure the DWARF info knows which register we are storing. + Pass it in to be used on the appropriate note. */ + if (!BYTES_BIG_ENDIAN + && GET_CODE (PATTERN (insn)) == SET + && GET_CODE (SET_SRC (PATTERN (insn))) == VEC_SELECT) + split_reg = savereg; + else + split_reg = NULL_RTX; + rs6000_frame_related (insn, frame_reg_rtx, sp_off - frame_off, - areg, GEN_INT (offset)); + areg, GEN_INT (offset), split_reg); } } @@ -20350,7 +23629,8 @@ rs6000_emit_prologue (void) be using r12 as frame_reg_rtx and r11 as the static chain pointer for nested functions. */ save_regno = 12; - if (DEFAULT_ABI == ABI_AIX && !using_static_chain_p) + if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + && !using_static_chain_p) save_regno = 11; else if (REGNO (frame_reg_rtx) == 12) { @@ -20389,7 +23669,7 @@ rs6000_emit_prologue (void) can use register 0. This allows us to use a plain 'blr' to return from the procedure more often. */ int save_LR_around_toc_setup = (TARGET_ELF - && DEFAULT_ABI != ABI_AIX + && DEFAULT_ABI == ABI_V4 && flag_pic && ! info->lr_save_p && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0); @@ -20451,7 +23731,7 @@ rs6000_emit_prologue (void) if (rs6000_save_toc_in_prologue_p ()) { rtx reg = gen_rtx_REG (reg_mode, TOC_REGNUM); - emit_insn (gen_frame_store (reg, sp_reg_rtx, 5 * reg_size)); + emit_insn (gen_frame_store (reg, sp_reg_rtx, RS6000_TOC_SAVE_SLOT)); } } @@ -20492,6 +23772,49 @@ rs6000_output_function_prologue (FILE *file, } } + /* ELFv2 ABI r2 setup code and local entry point. This must follow + immediately after the global entry point label. */ + if (DEFAULT_ABI == ABI_ELFv2 && cfun->machine->r2_setup_needed) + { + const char *name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + + fprintf (file, "0:\taddis 2,12,.TOC.-0b@ha\n"); + fprintf (file, "\taddi 2,2,.TOC.-0b@l\n"); + + fputs ("\t.localentry\t", file); + assemble_name (file, name); + fputs (",.-", file); + assemble_name (file, name); + fputs ("\n", file); + } + + /* Output -mprofile-kernel code. This needs to be done here instead of + in output_function_profile since it must go after the ELFv2 ABI + local entry point. */ + if (TARGET_PROFILE_KERNEL) + { + gcc_assert (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2); + gcc_assert (!TARGET_32BIT); + + asm_fprintf (file, "\tmflr %s\n", reg_names[0]); + asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); + + /* In the ELFv2 ABI we have no compiler stack word. It must be + the resposibility of _mcount to preserve the static chain + register if required. */ + if (DEFAULT_ABI != ABI_ELFv2 + && cfun->static_chain_decl != NULL) + { + asm_fprintf (file, "\tstd %s,24(%s)\n", + reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); + fprintf (file, "\tbl %s\n", RS6000_MCOUNT); + asm_fprintf (file, "\tld %s,24(%s)\n", + reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); + } + else + fprintf (file, "\tbl %s\n", RS6000_MCOUNT); + } + rs6000_pic_labelno++; } @@ -20544,6 +23867,7 @@ restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func) if (using_mfcr_multiple && count > 1) { + rtx insn; rtvec p; int ndx; @@ -20561,16 +23885,43 @@ restore_saved_cr (rtx reg, int using_mfcr_multiple, bool exit_func) gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR)); ndx++; } - emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); + insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); gcc_assert (ndx == count); + + /* For the ELFv2 ABI we generate a CFA_RESTORE for each + CR field separately. */ + if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap) + { + for (i = 0; i < 8; i++) + if (save_reg_p (CR0_REGNO + i)) + add_reg_note (insn, REG_CFA_RESTORE, + gen_rtx_REG (SImode, CR0_REGNO + i)); + + RTX_FRAME_RELATED_P (insn) = 1; + } } else for (i = 0; i < 8; i++) if (save_reg_p (CR0_REGNO + i)) - emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode, CR0_REGNO + i), - reg)); + { + rtx insn = emit_insn (gen_movsi_to_cr_one + (gen_rtx_REG (CCmode, CR0_REGNO + i), reg)); - if (!exit_func && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)) + /* For the ELFv2 ABI we generate a CFA_RESTORE for each + CR field separately, attached to the insn that in fact + restores this particular CR field. */ + if (!exit_func && DEFAULT_ABI == ABI_ELFv2 && flag_shrink_wrap) + { + add_reg_note (insn, REG_CFA_RESTORE, + gen_rtx_REG (SImode, CR0_REGNO + i)); + + RTX_FRAME_RELATED_P (insn) = 1; + } + } + + /* For other ABIs, we just generate a single CFA_RESTORE for CR2. */ + if (!exit_func && DEFAULT_ABI != ABI_ELFv2 + && (DEFAULT_ABI == ABI_V4 || flag_shrink_wrap)) { rtx insn = get_last_insn (); rtx cr = gen_rtx_REG (SImode, CR2_REGNO); @@ -20611,10 +23962,22 @@ restore_saved_lr (int regno, bool exit_func) static rtx add_crlr_cfa_restore (const rs6000_stack_t *info, rtx cfa_restores) { - if (info->cr_save_p) + if (DEFAULT_ABI == ABI_ELFv2) + { + int i; + for (i = 0; i < 8; i++) + if (save_reg_p (CR0_REGNO + i)) + { + rtx cr = gen_rtx_REG (SImode, CR0_REGNO + i); + cfa_restores = alloc_reg_note (REG_CFA_RESTORE, cr, + cfa_restores); + } + } + else if (info->cr_save_p) cfa_restores = alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (SImode, CR2_REGNO), cfa_restores); + if (info->lr_save_p) cfa_restores = alloc_reg_note (REG_CFA_RESTORE, gen_rtx_REG (Pmode, LR_REGNO), @@ -21112,6 +24475,35 @@ rs6000_emit_epilogue (int sibcall) || (!restoring_GPRs_inline && info->first_fp_reg_save == 64)); + /* In the ELFv2 ABI we need to restore all call-saved CR fields from + *separate* slots if the routine calls __builtin_eh_return, so + that they can be independently restored by the unwinder. */ + if (DEFAULT_ABI == ABI_ELFv2 && crtl->calls_eh_return) + { + int i, cr_off = info->ehcr_offset; + + for (i = 0; i < 8; i++) + if (!call_used_regs[CR0_REGNO + i]) + { + rtx reg = gen_rtx_REG (SImode, 0); + emit_insn (gen_frame_load (reg, frame_reg_rtx, + cr_off + frame_off)); + + insn = emit_insn (gen_movsi_to_cr_one + (gen_rtx_REG (CCmode, CR0_REGNO + i), reg)); + + if (!exit_func && flag_shrink_wrap) + { + add_reg_note (insn, REG_CFA_RESTORE, + gen_rtx_REG (SImode, CR0_REGNO + i)); + + RTX_FRAME_RELATED_P (insn) = 1; + } + + cr_off += reg_size; + } + } + /* Get the old lr if we saved it. If we are restoring registers out-of-line, then the out-of-line routines can do this for us. */ if (restore_lr && restoring_GPRs_inline) @@ -21155,7 +24547,7 @@ rs6000_emit_epilogue (int sibcall) { rtx reg = gen_rtx_REG (reg_mode, 2); emit_insn (gen_frame_load (reg, frame_reg_rtx, - frame_off + 5 * reg_size)); + frame_off + RS6000_TOC_SAVE_SLOT)); } for (i = 0; ; ++i) @@ -21441,6 +24833,7 @@ rs6000_emit_epilogue (int sibcall) if (! restoring_FPRs_inline) { int i; + int reg; rtx sym; if (flag_shrink_wrap) @@ -21449,10 +24842,9 @@ rs6000_emit_epilogue (int sibcall) sym = rs6000_savres_routine_sym (info, SAVRES_FPR | (lr ? SAVRES_LR : 0)); RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode, sym); - RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, - gen_rtx_REG (Pmode, - DEFAULT_ABI == ABI_AIX - ? 1 : 11)); + reg = (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)? 1 : 11; + RTVEC_ELT (p, 3) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, reg)); + for (i = 0; i < 64 - info->first_fp_reg_save; i++) { rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); @@ -21530,7 +24922,8 @@ rs6000_output_function_epilogue (FILE *file, System V.4 Powerpc's (and the embedded ABI derived from it) use a different traceback table. */ - if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive + if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + && ! flag_inhibit_size_directive && rs6000_traceback != traceback_none && !cfun->is_thunk) { const char *fname = NULL; @@ -21858,6 +25251,12 @@ rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, SIBLING_CALL_P (insn) = 1; emit_barrier (); + /* Ensure we have a global entry point for the thunk. ??? We could + avoid that if the target routine doesn't need a global entry point, + but we do not know whether this is the case at this point. */ + if (DEFAULT_ABI == ABI_ELFv2) + cfun->machine->r2_setup_needed = true; + /* Run just enough of rest_of_compilation to get the insns emitted. There's not really enough bulk here to make other passes such as instruction scheduling worth while. Note that use_thunk calls @@ -22554,7 +25953,7 @@ output_profile_hook (int labelno ATTRIBUTE_UNUSED) if (TARGET_PROFILE_KERNEL) return; - if (DEFAULT_ABI == ABI_AIX) + if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) { #ifndef NO_PROFILE_COUNTERS # define NO_PROFILE_COUNTERS 0 @@ -22698,29 +26097,9 @@ output_function_profiler (FILE *file, int labelno) break; case ABI_AIX: + case ABI_ELFv2: case ABI_DARWIN: - if (!TARGET_PROFILE_KERNEL) - { /* Don't do anything, done in output_profile_hook (). */ - } - else - { - gcc_assert (!TARGET_32BIT); - - asm_fprintf (file, "\tmflr %s\n", reg_names[0]); - asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]); - - if (cfun->static_chain_decl != NULL) - { - asm_fprintf (file, "\tstd %s,24(%s)\n", - reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); - fprintf (file, "\tbl %s\n", RS6000_MCOUNT); - asm_fprintf (file, "\tld %s,24(%s)\n", - reg_names[STATIC_CHAIN_REGNUM], reg_names[1]); - } - else - fprintf (file, "\tbl %s\n", RS6000_MCOUNT); - } break; } } @@ -22846,6 +26225,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) || rs6000_cpu_attr == CPU_POWER4 || rs6000_cpu_attr == CPU_POWER5 || rs6000_cpu_attr == CPU_POWER7 + || rs6000_cpu_attr == CPU_POWER8 || rs6000_cpu_attr == CPU_CELL) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0)) @@ -23128,7 +26508,8 @@ is_microcoded_insn (rtx insn) if (rs6000_cpu_attr == CPU_CELL) return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS; - if (rs6000_sched_groups) + if (rs6000_sched_groups + && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5)) { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_EXT_U @@ -23153,7 +26534,8 @@ is_cracked_insn (rtx insn) || GET_CODE (PATTERN (insn)) == CLOBBER) return false; - if (rs6000_sched_groups) + if (rs6000_sched_groups + && (rs6000_cpu == PROCESSOR_POWER4 || rs6000_cpu == PROCESSOR_POWER5)) { enum attr_type type = get_attr_type (insn); if (type == TYPE_LOAD_U || type == TYPE_STORE_U @@ -23432,6 +26814,8 @@ rs6000_issue_rate (void) case CPU_POWER6: case CPU_POWER7: return 5; + case CPU_POWER8: + return 7; default: return 1; } @@ -24059,6 +27443,39 @@ insn_must_be_first_in_group (rtx insn) break; } break; + case PROCESSOR_POWER8: + type = get_attr_type (insn); + + switch (type) + { + case TYPE_CR_LOGICAL: + case TYPE_DELAYED_CR: + case TYPE_MFCR: + case TYPE_MFCRF: + case TYPE_MTCR: + case TYPE_COMPARE: + case TYPE_DELAYED_COMPARE: + case TYPE_VAR_DELAYED_COMPARE: + case TYPE_IMUL_COMPARE: + case TYPE_LMUL_COMPARE: + case TYPE_SYNC: + case TYPE_ISYNC: + case TYPE_LOAD_L: + case TYPE_STORE_C: + case TYPE_LOAD_U: + case TYPE_LOAD_UX: + case TYPE_LOAD_EXT: + case TYPE_LOAD_EXT_U: + case TYPE_LOAD_EXT_UX: + case TYPE_STORE_UX: + case TYPE_VECSTORE: + case TYPE_MFJMPR: + case TYPE_MTJMPR: + return true; + default: + break; + } + break; default: break; } @@ -24137,6 +27554,25 @@ insn_must_be_last_in_group (rtx insn) break; } break; + case PROCESSOR_POWER8: + type = get_attr_type (insn); + + switch (type) + { + case TYPE_MFCR: + case TYPE_MTCR: + case TYPE_ISYNC: + case TYPE_SYNC: + case TYPE_LOAD_L: + case TYPE_STORE_C: + case TYPE_LOAD_EXT_U: + case TYPE_LOAD_EXT_UX: + case TYPE_STORE_UX: + return true; + default: + break; + } + break; default: break; } @@ -24226,8 +27662,9 @@ force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, if (can_issue_more && !is_branch_slot_insn (next_insn)) can_issue_more--; - /* Power6 and Power7 have special group ending nop. */ - if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7) + /* Do we have a special group ending nop? */ + if (rs6000_cpu_attr == CPU_POWER6 || rs6000_cpu_attr == CPU_POWER7 + || rs6000_cpu_attr == CPU_POWER8) { nop = gen_group_ending_nop (); emit_insn_before (nop, next_insn); @@ -24598,6 +28035,11 @@ rs6000_trampoline_size (void) ret = (TARGET_32BIT) ? 12 : 24; break; + case ABI_ELFv2: + gcc_assert (!TARGET_32BIT); + ret = 32; + break; + case ABI_DARWIN: case ABI_V4: ret = (TARGET_32BIT) ? 40 : 48; @@ -24653,6 +28095,7 @@ rs6000_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) break; /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */ + case ABI_ELFv2: case ABI_DARWIN: case ABI_V4: emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"), @@ -24743,6 +28186,9 @@ rs6000_handle_altivec_attribute (tree *node, unsigned_p = TYPE_UNSIGNED (type); switch (mode) { + case TImode: + result = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node); + break; case DImode: result = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); break; @@ -24947,7 +28393,7 @@ rs6000_ms_bitfield_layout_p (const_tree record_type) static void rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) { - if (DEFAULT_ABI == ABI_AIX + if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_MINIMAL_TOC && !TARGET_RELOCATABLE) { @@ -24968,7 +28414,8 @@ rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED) else fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP); } - else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE) + else if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + && !TARGET_RELOCATABLE) fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP); else { @@ -25518,7 +28965,7 @@ rs6000_elf_reloc_rw_mask (void) { if (flag_pic) return 3; - else if (DEFAULT_ABI == ABI_AIX) + else if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) return 2; else return 0; @@ -25594,7 +29041,7 @@ rs6000_elf_asm_out_destructor (rtx symbol, int priority) void rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) { - if (TARGET_64BIT) + if (TARGET_64BIT && DEFAULT_ABI != ABI_ELFv2) { fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file); ASM_OUTPUT_LABEL (file, name); @@ -25660,7 +29107,6 @@ rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl) fprintf (file, "%s:\n", desc_name); fprintf (file, "\t.long %s\n", orig_name); fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file); - if (DEFAULT_ABI == ABI_AIX) fputs ("\t.long 0\n", file); fprintf (file, "\t.previous\n"); } @@ -25690,7 +29136,7 @@ rs6000_elf_file_end (void) } #endif #if defined (POWERPC_LINUX) || defined (POWERPC_FREEBSD) - if (TARGET_32BIT) + if (TARGET_32BIT || DEFAULT_ABI == ABI_ELFv2) file_end_indicate_exec_stack (); #endif } @@ -25829,10 +29275,23 @@ rs6000_xcoff_asm_named_section (const char *name, unsigned int flags, name, suffix[smclass], flags & SECTION_ENTSIZE); } +#define IN_NAMED_SECTION(DECL) \ + ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \ + && DECL_SECTION_NAME (DECL) != NULL_TREE) + static section * rs6000_xcoff_select_section (tree decl, int reloc, - unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) + unsigned HOST_WIDE_INT align) { + /* Place variables with alignment stricter than BIGGEST_ALIGNMENT into + named section. */ + if (align > BIGGEST_ALIGNMENT) + { + resolve_unique_section (decl, reloc, true); + if (IN_NAMED_SECTION (decl)) + return get_named_section (decl, NULL, reloc); + } + if (decl_readonly_section (decl, reloc)) { if (TREE_PUBLIC (decl)) @@ -25870,10 +29329,12 @@ rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED) { const char *name; - /* Use select_section for private and uninitialized data. */ + /* Use select_section for private data and uninitialized data with + alignment <= BIGGEST_ALIGNMENT. */ if (!TREE_PUBLIC (decl) || DECL_COMMON (decl) - || DECL_INITIAL (decl) == NULL_TREE + || (DECL_INITIAL (decl) == NULL_TREE + && DECL_ALIGN (decl) <= BIGGEST_ALIGNMENT) || DECL_INITIAL (decl) == error_mark_node || (flag_zero_initialized_in_bss && initializer_zerop (DECL_INITIAL (decl)))) @@ -26430,7 +29891,8 @@ rs6000_register_move_cost (enum machine_mode mode, /* For those processors that have slow LR/CTR moves, make them more expensive than memory in order to bias spills to memory .*/ else if ((rs6000_cpu == PROCESSOR_POWER6 - || rs6000_cpu == PROCESSOR_POWER7) + || rs6000_cpu == PROCESSOR_POWER7 + || rs6000_cpu == PROCESSOR_POWER8) && reg_classes_intersect_p (rclass, LINK_OR_CTR_REGS)) ret = 6 * hard_regno_nregs[0][mode]; @@ -26440,7 +29902,7 @@ rs6000_register_move_cost (enum machine_mode mode, } /* If we have VSX, we can easily move between FPR or Altivec registers. */ - else if (VECTOR_UNIT_VSX_P (mode) + else if (VECTOR_MEM_VSX_P (mode) && reg_classes_intersect_p (to, VSX_REGS) && reg_classes_intersect_p (from, VSX_REGS)) ret = 2 * hard_regno_nregs[32][mode]; @@ -26481,7 +29943,8 @@ rs6000_memory_move_cost (enum machine_mode mode, reg_class_t rclass, if (reg_classes_intersect_p (rclass, GENERAL_REGS)) ret = 4 * hard_regno_nregs[0][mode]; - else if (reg_classes_intersect_p (rclass, FLOAT_REGS)) + else if ((reg_classes_intersect_p (rclass, FLOAT_REGS) + || reg_classes_intersect_p (rclass, VSX_REGS))) ret = 4 * hard_regno_nregs[32][mode]; else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) ret = 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode]; @@ -26643,54 +30106,26 @@ rs6000_emit_nmsub (rtx dst, rtx m1, rtx m2, rtx a) emit_insn (gen_rtx_SET (VOIDmode, dst, r)); } -/* Newton-Raphson approximation of floating point divide with just 2 passes - (either single precision floating point, or newer machines with higher - accuracy estimates). Support both scalar and vector divide. Assumes no - trapping math and finite arguments. */ +/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P, + add a reg_note saying that this was a division. Support both scalar and + vector divide. Assumes no trapping math and finite arguments. */ -static void -rs6000_emit_swdiv_high_precision (rtx dst, rtx n, rtx d) +void +rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p) { enum machine_mode mode = GET_MODE (dst); - rtx x0, e0, e1, y1, u0, v0; - enum insn_code code = optab_handler (smul_optab, mode); - insn_gen_fn gen_mul = GEN_FCN (code); - rtx one = rs6000_load_constant_and_splat (mode, dconst1); - - gcc_assert (code != CODE_FOR_nothing); - - /* x0 = 1./d estimate */ - x0 = gen_reg_rtx (mode); - emit_insn (gen_rtx_SET (VOIDmode, x0, - gen_rtx_UNSPEC (mode, gen_rtvec (1, d), - UNSPEC_FRES))); - - e0 = gen_reg_rtx (mode); - rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - (d * x0) */ - - e1 = gen_reg_rtx (mode); - rs6000_emit_madd (e1, e0, e0, e0); /* e1 = (e0 * e0) + e0 */ - - y1 = gen_reg_rtx (mode); - rs6000_emit_madd (y1, e1, x0, x0); /* y1 = (e1 * x0) + x0 */ - - u0 = gen_reg_rtx (mode); - emit_insn (gen_mul (u0, n, y1)); /* u0 = n * y1 */ - - v0 = gen_reg_rtx (mode); - rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - (d * u0) */ - - rs6000_emit_madd (dst, v0, y1, u0); /* dst = (v0 * y1) + u0 */ -} + rtx one, x0, e0, x1, xprev, eprev, xnext, enext, u, v; + int i; -/* Newton-Raphson approximation of floating point divide that has a low - precision estimate. Assumes no trapping math and finite arguments. */ + /* Low precision estimates guarantee 5 bits of accuracy. High + precision estimates guarantee 14 bits of accuracy. SFmode + requires 23 bits of accuracy. DFmode requires 52 bits of + accuracy. Each pass at least doubles the accuracy, leading + to the following. */ + int passes = (TARGET_RECIP_PRECISION) ? 1 : 3; + if (mode == DFmode || mode == V2DFmode) + passes++; -static void -rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d) -{ - enum machine_mode mode = GET_MODE (dst); - rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one; enum insn_code code = optab_handler (smul_optab, mode); insn_gen_fn gen_mul = GEN_FCN (code); @@ -26704,46 +30139,44 @@ rs6000_emit_swdiv_low_precision (rtx dst, rtx n, rtx d) gen_rtx_UNSPEC (mode, gen_rtvec (1, d), UNSPEC_FRES))); - e0 = gen_reg_rtx (mode); - rs6000_emit_nmsub (e0, d, x0, one); /* e0 = 1. - d * x0 */ - - y1 = gen_reg_rtx (mode); - rs6000_emit_madd (y1, e0, x0, x0); /* y1 = x0 + e0 * x0 */ + /* Each iteration but the last calculates x_(i+1) = x_i * (2 - d * x_i). */ + if (passes > 1) { - e1 = gen_reg_rtx (mode); - emit_insn (gen_mul (e1, e0, e0)); /* e1 = e0 * e0 */ + /* e0 = 1. - d * x0 */ + e0 = gen_reg_rtx (mode); + rs6000_emit_nmsub (e0, d, x0, one); - y2 = gen_reg_rtx (mode); - rs6000_emit_madd (y2, e1, y1, y1); /* y2 = y1 + e1 * y1 */ + /* x1 = x0 + e0 * x0 */ + x1 = gen_reg_rtx (mode); + rs6000_emit_madd (x1, e0, x0, x0); - e2 = gen_reg_rtx (mode); - emit_insn (gen_mul (e2, e1, e1)); /* e2 = e1 * e1 */ + for (i = 0, xprev = x1, eprev = e0; i < passes - 2; + ++i, xprev = xnext, eprev = enext) { - y3 = gen_reg_rtx (mode); - rs6000_emit_madd (y3, e2, y2, y2); /* y3 = y2 + e2 * y2 */ + /* enext = eprev * eprev */ + enext = gen_reg_rtx (mode); + emit_insn (gen_mul (enext, eprev, eprev)); - u0 = gen_reg_rtx (mode); - emit_insn (gen_mul (u0, n, y3)); /* u0 = n * y3 */ + /* xnext = xprev + enext * xprev */ + xnext = gen_reg_rtx (mode); + rs6000_emit_madd (xnext, enext, xprev, xprev); + } - v0 = gen_reg_rtx (mode); - rs6000_emit_nmsub (v0, d, u0, n); /* v0 = n - d * u0 */ + } else + xprev = x0; - rs6000_emit_madd (dst, v0, y3, u0); /* dst = u0 + v0 * y3 */ -} + /* The last iteration calculates x_(i+1) = n * x_i * (2 - d * x_i). */ -/* Newton-Raphson approximation of floating point divide DST = N/D. If NOTE_P, - add a reg_note saying that this was a division. Support both scalar and - vector divide. Assumes no trapping math and finite arguments. */ + /* u = n * xprev */ + u = gen_reg_rtx (mode); + emit_insn (gen_mul (u, n, xprev)); -void -rs6000_emit_swdiv (rtx dst, rtx n, rtx d, bool note_p) -{ - enum machine_mode mode = GET_MODE (dst); + /* v = n - (d * u) */ + v = gen_reg_rtx (mode); + rs6000_emit_nmsub (v, d, u, n); - if (RS6000_RECIP_HIGH_PRECISION_P (mode)) - rs6000_emit_swdiv_high_precision (dst, n, d); - else - rs6000_emit_swdiv_low_precision (dst, n, d); + /* dst = (v * xprev) + u */ + rs6000_emit_madd (dst, v, xprev, u); if (note_p) add_reg_note (get_last_insn (), REG_EQUAL, gen_rtx_DIV (mode, n, d)); @@ -26758,7 +30191,16 @@ rs6000_emit_swrsqrt (rtx dst, rtx src) enum machine_mode mode = GET_MODE (src); rtx x0 = gen_reg_rtx (mode); rtx y = gen_reg_rtx (mode); - int passes = (TARGET_RECIP_PRECISION) ? 2 : 3; + + /* Low precision estimates guarantee 5 bits of accuracy. High + precision estimates guarantee 14 bits of accuracy. SFmode + requires 23 bits of accuracy. DFmode requires 52 bits of + accuracy. Each pass at least doubles the accuracy, leading + to the following. */ + int passes = (TARGET_RECIP_PRECISION) ? 1 : 3; + if (mode == DFmode || mode == V2DFmode) + passes++; + REAL_VALUE_TYPE dconst3_2; int i; rtx halfthree; @@ -26920,6 +30362,136 @@ rs6000_emit_parity (rtx dst, rtx src) } } +/* Expand an Altivec constant permutation for little endian mode. + There are two issues: First, the two input operands must be + swapped so that together they form a double-wide array in LE + order. Second, the vperm instruction has surprising behavior + in LE mode: it interprets the elements of the source vectors + in BE mode ("left to right") and interprets the elements of + the destination vector in LE mode ("right to left"). To + correct for this, we must subtract each element of the permute + control vector from 31. + + For example, suppose we want to concatenate vr10 = {0, 1, 2, 3} + with vr11 = {4, 5, 6, 7} and extract {0, 2, 4, 6} using a vperm. + We place {0,1,2,3,8,9,10,11,16,17,18,19,24,25,26,27} in vr12 to + serve as the permute control vector. Then, in BE mode, + + vperm 9,10,11,12 + + places the desired result in vr9. However, in LE mode the + vector contents will be + + vr10 = 00000003 00000002 00000001 00000000 + vr11 = 00000007 00000006 00000005 00000004 + + The result of the vperm using the same permute control vector is + + vr9 = 05000000 07000000 01000000 03000000 + + That is, the leftmost 4 bytes of vr10 are interpreted as the + source for the rightmost 4 bytes of vr9, and so on. + + If we change the permute control vector to + + vr12 = {31,20,29,28,23,22,21,20,15,14,13,12,7,6,5,4} + + and issue + + vperm 9,11,10,12 + + we get the desired + + vr9 = 00000006 00000004 00000002 00000000. */ + +void +altivec_expand_vec_perm_const_le (rtx operands[4]) +{ + unsigned int i; + rtx perm[16]; + rtx constv, unspec; + rtx target = operands[0]; + rtx op0 = operands[1]; + rtx op1 = operands[2]; + rtx sel = operands[3]; + + /* Unpack and adjust the constant selector. */ + for (i = 0; i < 16; ++i) + { + rtx e = XVECEXP (sel, 0, i); + unsigned int elt = 31 - (INTVAL (e) & 31); + perm[i] = GEN_INT (elt); + } + + /* Expand to a permute, swapping the inputs and using the + adjusted selector. */ + if (!REG_P (op0)) + op0 = force_reg (V16QImode, op0); + if (!REG_P (op1)) + op1 = force_reg (V16QImode, op1); + + constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); + constv = force_reg (V16QImode, constv); + unspec = gen_rtx_UNSPEC (V16QImode, gen_rtvec (3, op1, op0, constv), + UNSPEC_VPERM); + if (!REG_P (target)) + { + rtx tmp = gen_reg_rtx (V16QImode); + emit_move_insn (tmp, unspec); + unspec = tmp; + } + + emit_move_insn (target, unspec); +} + +/* Similarly to altivec_expand_vec_perm_const_le, we must adjust the + permute control vector. But here it's not a constant, so we must + generate a vector NAND or NOR to do the adjustment. */ + +void +altivec_expand_vec_perm_le (rtx operands[4]) +{ + rtx notx, iorx, unspec; + rtx target = operands[0]; + rtx op0 = operands[1]; + rtx op1 = operands[2]; + rtx sel = operands[3]; + rtx tmp = target; + rtx norreg = gen_reg_rtx (V16QImode); + enum machine_mode mode = GET_MODE (target); + + /* Get everything in regs so the pattern matches. */ + if (!REG_P (op0)) + op0 = force_reg (mode, op0); + if (!REG_P (op1)) + op1 = force_reg (mode, op1); + if (!REG_P (sel)) + sel = force_reg (V16QImode, sel); + if (!REG_P (target)) + tmp = gen_reg_rtx (mode); + + /* Invert the selector with a VNAND if available, else a VNOR. + The VNAND is preferred for future fusion opportunities. */ + notx = gen_rtx_NOT (V16QImode, sel); + iorx = (TARGET_P8_VECTOR + ? gen_rtx_IOR (V16QImode, notx, notx) + : gen_rtx_AND (V16QImode, notx, notx)); + emit_insn (gen_rtx_SET (VOIDmode, norreg, iorx)); + + /* Permute with operands reversed and adjusted selector. */ + unspec = gen_rtx_UNSPEC (mode, gen_rtvec (3, op1, op0, norreg), + UNSPEC_VPERM); + + /* Copy into target, possibly by way of a register. */ + if (!REG_P (target)) + { + emit_move_insn (tmp, unspec); + unspec = tmp; + } + + emit_move_insn (target, unspec); +} + /* Expand an Altivec constant permutation. Return true if we match an efficient implementation; false to fall back to VPERM. */ @@ -26927,26 +30499,43 @@ bool altivec_expand_vec_perm_const (rtx operands[4]) { struct altivec_perm_insn { + HOST_WIDE_INT mask; enum insn_code impl; unsigned char perm[16]; }; static const struct altivec_perm_insn patterns[] = { - { CODE_FOR_altivec_vpkuhum, + { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum_direct, { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } }, - { CODE_FOR_altivec_vpkuwum, + { OPTION_MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum_direct, { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } }, - { CODE_FOR_altivec_vmrghb, + { OPTION_MASK_ALTIVEC, + (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghb_direct + : CODE_FOR_altivec_vmrglb_direct), { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } }, - { CODE_FOR_altivec_vmrghh, + { OPTION_MASK_ALTIVEC, + (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghh_direct + : CODE_FOR_altivec_vmrglh_direct), { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } }, - { CODE_FOR_altivec_vmrghw, + { OPTION_MASK_ALTIVEC, + (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrghw_direct + : CODE_FOR_altivec_vmrglw_direct), { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } }, - { CODE_FOR_altivec_vmrglb, + { OPTION_MASK_ALTIVEC, + (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglb_direct + : CODE_FOR_altivec_vmrghb_direct), { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } }, - { CODE_FOR_altivec_vmrglh, + { OPTION_MASK_ALTIVEC, + (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglh_direct + : CODE_FOR_altivec_vmrghh_direct), { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } }, - { CODE_FOR_altivec_vmrglw, - { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } } + { OPTION_MASK_ALTIVEC, + (BYTES_BIG_ENDIAN ? CODE_FOR_altivec_vmrglw_direct + : CODE_FOR_altivec_vmrghw_direct), + { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } }, + { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgew, + { 0, 1, 2, 3, 16, 17, 18, 19, 8, 9, 10, 11, 24, 25, 26, 27 } }, + { OPTION_MASK_P8_VECTOR, CODE_FOR_p8_vmrgow, + { 4, 5, 6, 7, 20, 21, 22, 23, 12, 13, 14, 15, 28, 29, 30, 31 } } }; unsigned int i, j, elt, which; @@ -27003,7 +30592,9 @@ altivec_expand_vec_perm_const (rtx operands[4]) break; if (i == 16) { - emit_insn (gen_altivec_vspltb (target, op0, GEN_INT (elt))); + if (!BYTES_BIG_ENDIAN) + elt = 15 - elt; + emit_insn (gen_altivec_vspltb_direct (target, op0, GEN_INT (elt))); return true; } @@ -27014,9 +30605,10 @@ altivec_expand_vec_perm_const (rtx operands[4]) break; if (i == 16) { + int field = BYTES_BIG_ENDIAN ? elt / 2 : 7 - elt / 2; x = gen_reg_rtx (V8HImode); - emit_insn (gen_altivec_vsplth (x, gen_lowpart (V8HImode, op0), - GEN_INT (elt / 2))); + emit_insn (gen_altivec_vsplth_direct (x, gen_lowpart (V8HImode, op0), + GEN_INT (field))); emit_move_insn (target, gen_lowpart (V16QImode, x)); return true; } @@ -27032,9 +30624,10 @@ altivec_expand_vec_perm_const (rtx operands[4]) break; if (i == 16) { + int field = BYTES_BIG_ENDIAN ? elt / 4 : 3 - elt / 4; x = gen_reg_rtx (V4SImode); - emit_insn (gen_altivec_vspltw (x, gen_lowpart (V4SImode, op0), - GEN_INT (elt / 4))); + emit_insn (gen_altivec_vspltw_direct (x, gen_lowpart (V4SImode, op0), + GEN_INT (field))); emit_move_insn (target, gen_lowpart (V16QImode, x)); return true; } @@ -27046,6 +30639,9 @@ altivec_expand_vec_perm_const (rtx operands[4]) { bool swapped; + if ((patterns[j].mask & rs6000_isa_flags) == 0) + continue; + elt = patterns[j].perm[0]; if (perm[0] == elt) swapped = false; @@ -27069,7 +30665,30 @@ altivec_expand_vec_perm_const (rtx operands[4]) enum machine_mode omode = insn_data[icode].operand[0].mode; enum machine_mode imode = insn_data[icode].operand[1].mode; - if (swapped) + /* For little-endian, don't use vpkuwum and vpkuhum if the + underlying vector type is not V4SI and V8HI, respectively. + For example, using vpkuwum with a V8HI picks up the even + halfwords (BE numbering) when the even halfwords (LE + numbering) are what we need. */ + if (!BYTES_BIG_ENDIAN + && icode == CODE_FOR_altivec_vpkuwum_direct + && ((GET_CODE (op0) == REG + && GET_MODE (op0) != V4SImode) + || (GET_CODE (op0) == SUBREG + && GET_MODE (XEXP (op0, 0)) != V4SImode))) + continue; + if (!BYTES_BIG_ENDIAN + && icode == CODE_FOR_altivec_vpkuhum_direct + && ((GET_CODE (op0) == REG + && GET_MODE (op0) != V8HImode) + || (GET_CODE (op0) == SUBREG + && GET_MODE (XEXP (op0, 0)) != V8HImode))) + continue; + + /* For little-endian, the two input operands must be swapped + (or swapped back) to ensure proper right-to-left numbering + from 0 to 2N-1. */ + if (swapped ^ !BYTES_BIG_ENDIAN) x = op0, op0 = op1, op1 = x; if (imode != V16QImode) { @@ -27087,6 +30706,12 @@ altivec_expand_vec_perm_const (rtx operands[4]) } } + if (!BYTES_BIG_ENDIAN) + { + altivec_expand_vec_perm_const_le (operands); + return true; + } + return false; } @@ -27135,7 +30760,6 @@ rs6000_expand_vec_perm_const_1 (rtx target, rtx op0, rtx op1, vmode = GET_MODE (target); gcc_assert (GET_MODE_NUNITS (vmode) == 2); dmode = mode_for_vector (GET_MODE_INNER (vmode), 4); - x = gen_rtx_VEC_CONCAT (dmode, op0, op1); v = gen_rtvec (2, GEN_INT (perm0), GEN_INT (perm1)); x = gen_rtx_VEC_SELECT (vmode, x, gen_rtx_PARALLEL (VOIDmode, v)); @@ -27231,7 +30855,7 @@ rs6000_expand_interleave (rtx target, rtx op0, rtx op1, bool highp) unsigned i, high, nelt = GET_MODE_NUNITS (vmode); rtx perm[16]; - high = (highp == BYTES_BIG_ENDIAN ? 0 : nelt / 2); + high = (highp ? 0 : nelt / 2); for (i = 0; i < nelt / 2; i++) { perm[i * 2] = GEN_INT (i + high); @@ -27286,6 +30910,8 @@ rs6000_function_value (const_tree valtype, { enum machine_mode mode; unsigned int regno; + enum machine_mode elt_mode; + int n_elts; /* Special handling for structs in darwin64. */ if (TARGET_MACHO @@ -27305,6 +30931,36 @@ rs6000_function_value (const_tree valtype, /* Otherwise fall through to standard ABI rules. */ } + /* The ELFv2 ABI returns homogeneous VFP aggregates in registers. */ + if (rs6000_discover_homogeneous_aggregate (TYPE_MODE (valtype), valtype, + &elt_mode, &n_elts)) + { + int first_reg, n_regs, i; + rtx par; + + if (SCALAR_FLOAT_MODE_P (elt_mode)) + { + /* _Decimal128 must use even/odd register pairs. */ + first_reg = (elt_mode == TDmode) ? FP_ARG_RETURN + 1 : FP_ARG_RETURN; + n_regs = (GET_MODE_SIZE (elt_mode) + 7) >> 3; + } + else + { + first_reg = ALTIVEC_ARG_RETURN; + n_regs = 1; + } + + par = gen_rtx_PARALLEL (TYPE_MODE (valtype), rtvec_alloc (n_elts)); + for (i = 0; i < n_elts; i++) + { + rtx r = gen_rtx_REG (elt_mode, first_reg + i * n_regs); + rtx off = GEN_INT (i * GET_MODE_SIZE (elt_mode)); + XVECEXP (par, 0, i) = gen_rtx_EXPR_LIST (VOIDmode, r, off); + } + + return par; + } + if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode) { /* Long long return value need be split in -mpowerpc64, 32bit ABI. */ @@ -27417,6 +31073,13 @@ rs6000_libcall_value (enum machine_mode mode) } +/* Return true if we use LRA instead of reload pass. */ +static bool +rs6000_lra_p (void) +{ + return rs6000_lra_flag; +} + /* Given FROM and TO register numbers, say whether this elimination is allowed. Frame pointer elimination is automatically handled. @@ -27679,22 +31342,33 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { { "altivec", OPTION_MASK_ALTIVEC, false, true }, { "cmpb", OPTION_MASK_CMPB, false, true }, + { "crypto", OPTION_MASK_CRYPTO, false, true }, + { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true }, { "dlmzb", OPTION_MASK_DLMZB, false, true }, { "fprnd", OPTION_MASK_FPRND, false, true }, { "hard-dfp", OPTION_MASK_DFP, false, true }, + { "htm", OPTION_MASK_HTM, false, true }, { "isel", OPTION_MASK_ISEL, false, true }, { "mfcrf", OPTION_MASK_MFCRF, false, true }, { "mfpgpr", OPTION_MASK_MFPGPR, false, true }, { "mulhw", OPTION_MASK_MULHW, false, true }, { "multiple", OPTION_MASK_MULTIPLE, false, true }, - { "update", OPTION_MASK_NO_UPDATE, true , true }, { "popcntb", OPTION_MASK_POPCNTB, false, true }, { "popcntd", OPTION_MASK_POPCNTD, false, true }, + { "power8-fusion", OPTION_MASK_P8_FUSION, false, true }, + { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true }, + { "power8-vector", OPTION_MASK_P8_VECTOR, false, true }, { "powerpc-gfxopt", OPTION_MASK_PPC_GFXOPT, false, true }, { "powerpc-gpopt", OPTION_MASK_PPC_GPOPT, false, true }, + { "quad-memory", OPTION_MASK_QUAD_MEMORY, false, true }, + { "quad-memory-atomic", OPTION_MASK_QUAD_MEMORY_ATOMIC, false, true }, { "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true }, { "string", OPTION_MASK_STRING, false, true }, + { "update", OPTION_MASK_NO_UPDATE, true , true }, + { "upper-regs-df", OPTION_MASK_UPPER_REGS_DF, false, false }, + { "upper-regs-sf", OPTION_MASK_UPPER_REGS_SF, false, false }, { "vsx", OPTION_MASK_VSX, false, true }, + { "vsx-timode", OPTION_MASK_VSX_TIMODE, false, true }, #ifdef OPTION_MASK_64BIT #if TARGET_AIX_OS { "aix64", OPTION_MASK_64BIT, false, false }, @@ -27734,6 +31408,11 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] = { "frsqrtes", RS6000_BTM_FRSQRTES, false, false }, { "popcntd", RS6000_BTM_POPCNTD, false, false }, { "cell", RS6000_BTM_CELL, false, false }, + { "power8-vector", RS6000_BTM_P8_VECTOR, false, false }, + { "crypto", RS6000_BTM_CRYPTO, false, false }, + { "htm", RS6000_BTM_HTM, false, false }, + { "hard-dfp", RS6000_BTM_DFP, false, false }, + { "hard-float", RS6000_BTM_HARD_FLOAT, false, false }, }; /* Option variables that we want to support inside attribute((target)) and @@ -28250,7 +31929,6 @@ rs6000_print_options_internal (FILE *file, size_t cur_column; size_t max_column = 76; const char *comma = ""; - const char *nl = "\n"; if (indent) start_column += fprintf (file, "%*s", indent, ""); @@ -28281,7 +31959,6 @@ rs6000_print_options_internal (FILE *file, fprintf (stderr, ", \\\n%*s", (int)start_column, ""); cur_column = start_column + len; comma = ""; - nl = "\n\n"; } fprintf (file, "%s%s%s%s", comma, prefix, no_str, @@ -28291,7 +31968,7 @@ rs6000_print_options_internal (FILE *file, } } - fputs (nl, file); + fputs ("\n", file); } /* Helper function to print the current isa options on a line. */ @@ -28467,118 +32144,149 @@ rs6000_legitimate_constant_p (enum machine_mode mode, rtx x) } -/* A function pointer under AIX is a pointer to a data area whose first word - contains the actual address of the function, whose second word contains a - pointer to its TOC, and whose third word contains a value to place in the - static chain register (r11). Note that if we load the static chain, our - "trampoline" need not have any executable code. */ + +/* Expand code to perform a call under the AIX or ELFv2 ABI. */ void -rs6000_call_indirect_aix (rtx value, rtx func_desc, rtx flag) +rs6000_call_aix (rtx value, rtx func_desc, rtx flag, rtx cookie) { + rtx toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM); + rtx toc_load = NULL_RTX; + rtx toc_restore = NULL_RTX; rtx func_addr; - rtx toc_reg; - rtx sc_reg; - rtx stack_ptr; - rtx stack_toc_offset; - rtx stack_toc_mem; - rtx func_toc_offset; - rtx func_toc_mem; - rtx func_sc_offset; - rtx func_sc_mem; + rtx abi_reg = NULL_RTX; + rtx call[4]; + int n_call; rtx insn; - rtx (*call_func) (rtx, rtx, rtx, rtx); - rtx (*call_value_func) (rtx, rtx, rtx, rtx, rtx); - stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); - toc_reg = gen_rtx_REG (Pmode, TOC_REGNUM); + /* Handle longcall attributes. */ + if (INTVAL (cookie) & CALL_LONG) + func_desc = rs6000_longcall_ref (func_desc); + + /* Handle indirect calls. */ + if (GET_CODE (func_desc) != SYMBOL_REF + || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (func_desc))) + { + /* Save the TOC into its reserved slot before the call, + and prepare to restore it after the call. */ + rtx stack_ptr = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); + rtx stack_toc_offset = GEN_INT (RS6000_TOC_SAVE_SLOT); + rtx stack_toc_mem = gen_frame_mem (Pmode, + gen_rtx_PLUS (Pmode, stack_ptr, + stack_toc_offset)); + toc_restore = gen_rtx_SET (VOIDmode, toc_reg, stack_toc_mem); + + /* Can we optimize saving the TOC in the prologue or + do we need to do it at every call? */ + if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca) + cfun->machine->save_toc_in_prologue = true; + else + { + MEM_VOLATILE_P (stack_toc_mem) = 1; + emit_move_insn (stack_toc_mem, toc_reg); + } + + if (DEFAULT_ABI == ABI_ELFv2) + { + /* A function pointer in the ELFv2 ABI is just a plain address, but + the ABI requires it to be loaded into r12 before the call. */ + func_addr = gen_rtx_REG (Pmode, 12); + emit_move_insn (func_addr, func_desc); + abi_reg = func_addr; + } + else + { + /* A function pointer under AIX is a pointer to a data area whose + first word contains the actual address of the function, whose + second word contains a pointer to its TOC, and whose third word + contains a value to place in the static chain register (r11). + Note that if we load the static chain, our "trampoline" need + not have any executable code. */ /* Load up address of the actual function. */ func_desc = force_reg (Pmode, func_desc); func_addr = gen_reg_rtx (Pmode); emit_move_insn (func_addr, gen_rtx_MEM (Pmode, func_desc)); - if (TARGET_32BIT) - { - - stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_32BIT); - func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_32BIT); - func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_32BIT); + /* Prepare to load the TOC of the called function. Note that the + TOC load must happen immediately before the actual call so + that unwinding the TOC registers works correctly. See the + comment in frob_update_context. */ + rtx func_toc_offset = GEN_INT (GET_MODE_SIZE (Pmode)); + rtx func_toc_mem = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, func_desc, + func_toc_offset)); + toc_load = gen_rtx_USE (VOIDmode, func_toc_mem); + + /* If we have a static chain, load it up. */ if (TARGET_POINTERS_TO_NESTED_FUNCTIONS) { - call_func = gen_call_indirect_aix32bit; - call_value_func = gen_call_value_indirect_aix32bit; - } - else - { - call_func = gen_call_indirect_aix32bit_nor11; - call_value_func = gen_call_value_indirect_aix32bit_nor11; + rtx sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); + rtx func_sc_offset = GEN_INT (2 * GET_MODE_SIZE (Pmode)); + rtx func_sc_mem = gen_rtx_MEM (Pmode, + gen_rtx_PLUS (Pmode, func_desc, + func_sc_offset)); + emit_move_insn (sc_reg, func_sc_mem); + abi_reg = sc_reg; } } - else - { - stack_toc_offset = GEN_INT (TOC_SAVE_OFFSET_64BIT); - func_toc_offset = GEN_INT (AIX_FUNC_DESC_TOC_64BIT); - func_sc_offset = GEN_INT (AIX_FUNC_DESC_SC_64BIT); - if (TARGET_POINTERS_TO_NESTED_FUNCTIONS) - { - call_func = gen_call_indirect_aix64bit; - call_value_func = gen_call_value_indirect_aix64bit; } else { - call_func = gen_call_indirect_aix64bit_nor11; - call_value_func = gen_call_value_indirect_aix64bit_nor11; - } + /* Direct calls use the TOC: for local calls, the callee will + assume the TOC register is set; for non-local calls, the + PLT stub needs the TOC register. */ + abi_reg = toc_reg; + func_addr = func_desc; } - /* Reserved spot to store the TOC. */ - stack_toc_mem = gen_frame_mem (Pmode, - gen_rtx_PLUS (Pmode, - stack_ptr, - stack_toc_offset)); + /* Create the call. */ + call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_addr), flag); + if (value != NULL_RTX) + call[0] = gen_rtx_SET (VOIDmode, value, call[0]); + n_call = 1; - gcc_assert (cfun); - gcc_assert (cfun->machine); + if (toc_load) + call[n_call++] = toc_load; + if (toc_restore) + call[n_call++] = toc_restore; - /* Can we optimize saving the TOC in the prologue or do we need to do it at - every call? */ - if (TARGET_SAVE_TOC_INDIRECT && !cfun->calls_alloca) - cfun->machine->save_toc_in_prologue = true; + call[n_call++] = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, LR_REGNO)); - else - { - MEM_VOLATILE_P (stack_toc_mem) = 1; - emit_move_insn (stack_toc_mem, toc_reg); - } + insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (n_call, call)); + insn = emit_call_insn (insn); - /* Calculate the address to load the TOC of the called function. We don't - actually load this until the split after reload. */ - func_toc_mem = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, - func_desc, - func_toc_offset)); + /* Mention all registers defined by the ABI to hold information + as uses in CALL_INSN_FUNCTION_USAGE. */ + if (abi_reg) + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), abi_reg); +} - /* If we have a static chain, load it up. */ - if (TARGET_POINTERS_TO_NESTED_FUNCTIONS) - { - func_sc_mem = gen_rtx_MEM (Pmode, - gen_rtx_PLUS (Pmode, - func_desc, - func_sc_offset)); +/* Expand code to perform a sibling call under the AIX or ELFv2 ABI. */ - sc_reg = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); - emit_move_insn (sc_reg, func_sc_mem); - } +void +rs6000_sibcall_aix (rtx value, rtx func_desc, rtx flag, rtx cookie) +{ + rtx call[2]; + rtx insn; + + gcc_assert (INTVAL (cookie) == 0); /* Create the call. */ - if (value) - insn = call_value_func (value, func_addr, flag, func_toc_mem, - stack_toc_mem); - else - insn = call_func (func_addr, flag, func_toc_mem, stack_toc_mem); + call[0] = gen_rtx_CALL (VOIDmode, gen_rtx_MEM (SImode, func_desc), flag); + if (value != NULL_RTX) + call[0] = gen_rtx_SET (VOIDmode, value, call[0]); - emit_call_insn (insn); + call[1] = simple_return_rtx; + + insn = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (2, call)); + insn = emit_call_insn (insn); + + /* Note use of the TOC register. */ + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, TOC_REGNUM)); + /* We need to also mark a use of the link register since the function we + sibling-call to will use it to return to our caller. */ + use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, LR_REGNO)); } /* Return whether we need to always update the saved TOC pointer when we update @@ -28679,6 +32387,661 @@ rs6000_set_up_by_prologue (struct hard_reg_set_container *set) add_to_hard_reg_set (&set->set, Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); } + +/* Helper function for rs6000_split_logical to emit a logical instruction after + spliting the operation to single GPR registers. + + DEST is the destination register. + OP1 and OP2 are the input source registers. + CODE is the base operation (AND, IOR, XOR, NOT). + MODE is the machine mode. + If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT. + If COMPLEMENT_OP1_P is true, wrap operand1 with NOT. + If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. + CLOBBER_REG is either NULL or a scratch register of type CC to allow + formation of the AND instructions. */ + +static void +rs6000_split_logical_inner (rtx dest, + rtx op1, + rtx op2, + enum rtx_code code, + enum machine_mode mode, + bool complement_final_p, + bool complement_op1_p, + bool complement_op2_p, + rtx clobber_reg) +{ + rtx bool_rtx; + rtx set_rtx; + + /* Optimize AND of 0/0xffffffff and IOR/XOR of 0. */ + if (op2 && GET_CODE (op2) == CONST_INT + && (mode == SImode || (mode == DImode && TARGET_POWERPC64)) + && !complement_final_p && !complement_op1_p && !complement_op2_p) + { + HOST_WIDE_INT mask = GET_MODE_MASK (mode); + HOST_WIDE_INT value = INTVAL (op2) & mask; + + /* Optimize AND of 0 to just set 0. Optimize AND of -1 to be a move. */ + if (code == AND) + { + if (value == 0) + { + emit_insn (gen_rtx_SET (VOIDmode, dest, const0_rtx)); + return; + } + + else if (value == mask) + { + if (!rtx_equal_p (dest, op1)) + emit_insn (gen_rtx_SET (VOIDmode, dest, op1)); + return; + } + } + + /* Optimize IOR/XOR of 0 to be a simple move. Split large operations + into separate ORI/ORIS or XORI/XORIS instrucitons. */ + else if (code == IOR || code == XOR) + { + if (value == 0) + { + if (!rtx_equal_p (dest, op1)) + emit_insn (gen_rtx_SET (VOIDmode, dest, op1)); + return; + } + } + } + + if (complement_op1_p) + op1 = gen_rtx_NOT (mode, op1); + + if (complement_op2_p) + op2 = gen_rtx_NOT (mode, op2); + + bool_rtx = ((code == NOT) + ? gen_rtx_NOT (mode, op1) + : gen_rtx_fmt_ee (code, mode, op1, op2)); + + if (complement_final_p) + bool_rtx = gen_rtx_NOT (mode, bool_rtx); + + set_rtx = gen_rtx_SET (VOIDmode, dest, bool_rtx); + + /* Is this AND with an explicit clobber? */ + if (clobber_reg) + { + rtx clobber = gen_rtx_CLOBBER (VOIDmode, clobber_reg); + set_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set_rtx, clobber)); + } + + emit_insn (set_rtx); + return; +} + +/* Split a DImode AND/IOR/XOR with a constant on a 32-bit system. These + operations are split immediately during RTL generation to allow for more + optimizations of the AND/IOR/XOR. + + OPERANDS is an array containing the destination and two input operands. + CODE is the base operation (AND, IOR, XOR, NOT). + MODE is the machine mode. + If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT. + If COMPLEMENT_OP1_P is true, wrap operand1 with NOT. + If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. + CLOBBER_REG is either NULL or a scratch register of type CC to allow + formation of the AND instructions. */ + +static void +rs6000_split_logical_di (rtx operands[3], + enum rtx_code code, + bool complement_final_p, + bool complement_op1_p, + bool complement_op2_p, + rtx clobber_reg) +{ + const HOST_WIDE_INT lower_32bits = HOST_WIDE_INT_C(0xffffffff); + const HOST_WIDE_INT upper_32bits = ~ lower_32bits; + const HOST_WIDE_INT sign_bit = HOST_WIDE_INT_C(0x80000000); + enum hi_lo { hi = 0, lo = 1 }; + rtx op0_hi_lo[2], op1_hi_lo[2], op2_hi_lo[2]; + size_t i; + + op0_hi_lo[hi] = gen_highpart (SImode, operands[0]); + op1_hi_lo[hi] = gen_highpart (SImode, operands[1]); + op0_hi_lo[lo] = gen_lowpart (SImode, operands[0]); + op1_hi_lo[lo] = gen_lowpart (SImode, operands[1]); + + if (code == NOT) + op2_hi_lo[hi] = op2_hi_lo[lo] = NULL_RTX; + else + { + if (GET_CODE (operands[2]) != CONST_INT) + { + op2_hi_lo[hi] = gen_highpart_mode (SImode, DImode, operands[2]); + op2_hi_lo[lo] = gen_lowpart (SImode, operands[2]); + } + else + { + HOST_WIDE_INT value = INTVAL (operands[2]); + HOST_WIDE_INT value_hi_lo[2]; + + gcc_assert (!complement_final_p); + gcc_assert (!complement_op1_p); + gcc_assert (!complement_op2_p); + + value_hi_lo[hi] = value >> 32; + value_hi_lo[lo] = value & lower_32bits; + + for (i = 0; i < 2; i++) + { + HOST_WIDE_INT sub_value = value_hi_lo[i]; + + if (sub_value & sign_bit) + sub_value |= upper_32bits; + + op2_hi_lo[i] = GEN_INT (sub_value); + + /* If this is an AND instruction, check to see if we need to load + the value in a register. */ + if (code == AND && sub_value != -1 && sub_value != 0 + && !and_operand (op2_hi_lo[i], SImode)) + op2_hi_lo[i] = force_reg (SImode, op2_hi_lo[i]); + } + } + } + + for (i = 0; i < 2; i++) + { + /* Split large IOR/XOR operations. */ + if ((code == IOR || code == XOR) + && GET_CODE (op2_hi_lo[i]) == CONST_INT + && !complement_final_p + && !complement_op1_p + && !complement_op2_p + && clobber_reg == NULL_RTX + && !logical_const_operand (op2_hi_lo[i], SImode)) + { + HOST_WIDE_INT value = INTVAL (op2_hi_lo[i]); + HOST_WIDE_INT hi_16bits = value & HOST_WIDE_INT_C(0xffff0000); + HOST_WIDE_INT lo_16bits = value & HOST_WIDE_INT_C(0x0000ffff); + rtx tmp = gen_reg_rtx (SImode); + + /* Make sure the constant is sign extended. */ + if ((hi_16bits & sign_bit) != 0) + hi_16bits |= upper_32bits; + + rs6000_split_logical_inner (tmp, op1_hi_lo[i], GEN_INT (hi_16bits), + code, SImode, false, false, false, + NULL_RTX); + + rs6000_split_logical_inner (op0_hi_lo[i], tmp, GEN_INT (lo_16bits), + code, SImode, false, false, false, + NULL_RTX); + } + else + rs6000_split_logical_inner (op0_hi_lo[i], op1_hi_lo[i], op2_hi_lo[i], + code, SImode, complement_final_p, + complement_op1_p, complement_op2_p, + clobber_reg); + } + + return; +} + +/* Split the insns that make up boolean operations operating on multiple GPR + registers. The boolean MD patterns ensure that the inputs either are + exactly the same as the output registers, or there is no overlap. + + OPERANDS is an array containing the destination and two input operands. + CODE is the base operation (AND, IOR, XOR, NOT). + MODE is the machine mode. + If COMPLEMENT_FINAL_P is true, wrap the whole operation with NOT. + If COMPLEMENT_OP1_P is true, wrap operand1 with NOT. + If COMPLEMENT_OP2_P is true, wrap operand2 with NOT. + CLOBBER_REG is either NULL or a scratch register of type CC to allow + formation of the AND instructions. */ + +void +rs6000_split_logical (rtx operands[3], + enum rtx_code code, + bool complement_final_p, + bool complement_op1_p, + bool complement_op2_p, + rtx clobber_reg) +{ + enum machine_mode mode = GET_MODE (operands[0]); + enum machine_mode sub_mode; + rtx op0, op1, op2; + int sub_size, regno0, regno1, nregs, i; + + /* If this is DImode, use the specialized version that can run before + register allocation. */ + if (mode == DImode && !TARGET_POWERPC64) + { + rs6000_split_logical_di (operands, code, complement_final_p, + complement_op1_p, complement_op2_p, + clobber_reg); + return; + } + + op0 = operands[0]; + op1 = operands[1]; + op2 = (code == NOT) ? NULL_RTX : operands[2]; + sub_mode = (TARGET_POWERPC64) ? DImode : SImode; + sub_size = GET_MODE_SIZE (sub_mode); + regno0 = REGNO (op0); + regno1 = REGNO (op1); + + gcc_assert (reload_completed); + gcc_assert (IN_RANGE (regno0, FIRST_GPR_REGNO, LAST_GPR_REGNO)); + gcc_assert (IN_RANGE (regno1, FIRST_GPR_REGNO, LAST_GPR_REGNO)); + + nregs = rs6000_hard_regno_nregs[(int)mode][regno0]; + gcc_assert (nregs > 1); + + if (op2 && REG_P (op2)) + gcc_assert (IN_RANGE (REGNO (op2), FIRST_GPR_REGNO, LAST_GPR_REGNO)); + + for (i = 0; i < nregs; i++) + { + int offset = i * sub_size; + rtx sub_op0 = simplify_subreg (sub_mode, op0, mode, offset); + rtx sub_op1 = simplify_subreg (sub_mode, op1, mode, offset); + rtx sub_op2 = ((code == NOT) + ? NULL_RTX + : simplify_subreg (sub_mode, op2, mode, offset)); + + rs6000_split_logical_inner (sub_op0, sub_op1, sub_op2, code, sub_mode, + complement_final_p, complement_op1_p, + complement_op2_p, clobber_reg); + } + + return; +} + + +/* Return true if the peephole2 can combine a load involving a combination of + an addis instruction and a load with an offset that can be fused together on + a power8. + + The operands are: + operands[0] register set with addis + operands[1] value set via addis + operands[2] target register being loaded + operands[3] D-form memory reference using operands[0]. + + In addition, we are passed a boolean that is true if this is a peephole2, + and we can use see if the addis_reg is dead after the insn and can be + replaced by the target register. */ + +bool +fusion_gpr_load_p (rtx *operands, bool peep2_p) +{ + rtx addis_reg = operands[0]; + rtx addis_value = operands[1]; + rtx target = operands[2]; + rtx mem = operands[3]; + rtx addr; + rtx base_reg; + + /* Validate arguments. */ + if (!base_reg_operand (addis_reg, GET_MODE (addis_reg))) + return false; + + if (!base_reg_operand (target, GET_MODE (target))) + return false; + + if (!fusion_gpr_addis (addis_value, GET_MODE (addis_value))) + return false; + + if (!fusion_gpr_mem_load (mem, GET_MODE (mem))) + return false; + + /* Allow sign/zero extension. */ + if (GET_CODE (mem) == ZERO_EXTEND + || (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN)) + mem = XEXP (mem, 0); + + if (!MEM_P (mem)) + return false; + + addr = XEXP (mem, 0); /* either PLUS or LO_SUM. */ + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + return false; + + /* Validate that the register used to load the high value is either the + register being loaded, or we can safely replace its use in a peephole2. + + If this is a peephole2, we assume that there are 2 instructions in the + peephole (addis and load), so we want to check if the target register was + not used in the memory address and the register to hold the addis result + is dead after the peephole. */ + if (REGNO (addis_reg) != REGNO (target)) + { + if (!peep2_p) + return false; + + if (reg_mentioned_p (target, mem)) + return false; + + if (!peep2_reg_dead_p (2, addis_reg)) + return false; + + /* If the target register being loaded is the stack pointer, we must + avoid loading any other value into it, even temporarily. */ + if (REG_P (target) && REGNO (target) == STACK_POINTER_REGNUM) + return false; + } + + base_reg = XEXP (addr, 0); + return REGNO (addis_reg) == REGNO (base_reg); +} + +/* During the peephole2 pass, adjust and expand the insns for a load fusion + sequence. We adjust the addis register to use the target register. If the + load sign extends, we adjust the code to do the zero extending load, and an + explicit sign extension later since the fusion only covers zero extending + loads. + + The operands are: + operands[0] register set with addis (to be replaced with target) + operands[1] value set via addis + operands[2] target register being loaded + operands[3] D-form memory reference using operands[0]. */ + +void +expand_fusion_gpr_load (rtx *operands) +{ + rtx addis_value = operands[1]; + rtx target = operands[2]; + rtx orig_mem = operands[3]; + rtx new_addr, new_mem, orig_addr, offset; + enum rtx_code plus_or_lo_sum; + enum machine_mode target_mode = GET_MODE (target); + enum machine_mode extend_mode = target_mode; + enum machine_mode ptr_mode = Pmode; + enum rtx_code extend = UNKNOWN; + rtx addis_reg = ((ptr_mode == target_mode) + ? target + : simplify_subreg (ptr_mode, target, target_mode, 0)); + + if (GET_CODE (orig_mem) == ZERO_EXTEND + || (TARGET_P8_FUSION_SIGN && GET_CODE (orig_mem) == SIGN_EXTEND)) + { + extend = GET_CODE (orig_mem); + orig_mem = XEXP (orig_mem, 0); + target_mode = GET_MODE (orig_mem); + } + + gcc_assert (MEM_P (orig_mem)); + + orig_addr = XEXP (orig_mem, 0); + plus_or_lo_sum = GET_CODE (orig_addr); + gcc_assert (plus_or_lo_sum == PLUS || plus_or_lo_sum == LO_SUM); + + offset = XEXP (orig_addr, 1); + new_addr = gen_rtx_fmt_ee (plus_or_lo_sum, ptr_mode, addis_reg, offset); + new_mem = change_address (orig_mem, target_mode, new_addr); + + if (extend != UNKNOWN) + new_mem = gen_rtx_fmt_e (ZERO_EXTEND, extend_mode, new_mem); + + emit_insn (gen_rtx_SET (VOIDmode, addis_reg, addis_value)); + emit_insn (gen_rtx_SET (VOIDmode, target, new_mem)); + + if (extend == SIGN_EXTEND) + { + int sub_off = ((BYTES_BIG_ENDIAN) + ? GET_MODE_SIZE (extend_mode) - GET_MODE_SIZE (target_mode) + : 0); + rtx sign_reg + = simplify_subreg (target_mode, target, extend_mode, sub_off); + + emit_insn (gen_rtx_SET (VOIDmode, target, + gen_rtx_SIGN_EXTEND (extend_mode, sign_reg))); + } + + return; +} + +/* Return a string to fuse an addis instruction with a gpr load to the same + register that we loaded up the addis instruction. The code is complicated, + so we call output_asm_insn directly, and just return "". + + The operands are: + operands[0] register set with addis (must be same reg as target). + operands[1] value set via addis + operands[2] target register being loaded + operands[3] D-form memory reference using operands[0]. */ + +const char * +emit_fusion_gpr_load (rtx *operands) +{ + rtx addis_reg = operands[0]; + rtx addis_value = operands[1]; + rtx target = operands[2]; + rtx mem = operands[3]; + rtx fuse_ops[10]; + rtx addr; + rtx load_offset; + const char *addis_str = NULL; + const char *load_str = NULL; + const char *extend_insn = NULL; + const char *mode_name = NULL; + char insn_template[80]; + enum machine_mode mode; + const char *comment_str = ASM_COMMENT_START; + bool sign_p = false; + + gcc_assert (REG_P (addis_reg) && REG_P (target)); + gcc_assert (REGNO (addis_reg) == REGNO (target)); + + if (*comment_str == ' ') + comment_str++; + + /* Allow sign/zero extension. */ + if (GET_CODE (mem) == ZERO_EXTEND) + mem = XEXP (mem, 0); + + else if (GET_CODE (mem) == SIGN_EXTEND && TARGET_P8_FUSION_SIGN) + { + sign_p = true; + mem = XEXP (mem, 0); + } + + gcc_assert (MEM_P (mem)); + addr = XEXP (mem, 0); + if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM) + gcc_unreachable (); + + load_offset = XEXP (addr, 1); + + /* Now emit the load instruction to the same register. */ + mode = GET_MODE (mem); + switch (mode) + { + case QImode: + mode_name = "char"; + load_str = "lbz"; + extend_insn = "extsb %0,%0"; + break; + + case HImode: + mode_name = "short"; + load_str = "lhz"; + extend_insn = "extsh %0,%0"; + break; + + case SImode: + mode_name = "int"; + load_str = "lwz"; + extend_insn = "extsw %0,%0"; + break; + + case DImode: + if (TARGET_POWERPC64) + { + mode_name = "long"; + load_str = "ld"; + } + else + gcc_unreachable (); + break; + + default: + gcc_unreachable (); + } + + /* Emit the addis instruction. */ + fuse_ops[0] = target; + if (satisfies_constraint_L (addis_value)) + { + fuse_ops[1] = addis_value; + addis_str = "lis %0,%v1"; + } + + else if (GET_CODE (addis_value) == PLUS) + { + rtx op0 = XEXP (addis_value, 0); + rtx op1 = XEXP (addis_value, 1); + + if (REG_P (op0) && CONST_INT_P (op1) + && satisfies_constraint_L (op1)) + { + fuse_ops[1] = op0; + fuse_ops[2] = op1; + addis_str = "addis %0,%1,%v2"; + } + } + + else if (GET_CODE (addis_value) == HIGH) + { + rtx value = XEXP (addis_value, 0); + if (GET_CODE (value) == UNSPEC && XINT (value, 1) == UNSPEC_TOCREL) + { + fuse_ops[1] = XVECEXP (value, 0, 0); /* symbol ref. */ + fuse_ops[2] = XVECEXP (value, 0, 1); /* TOC register. */ + if (TARGET_ELF) + addis_str = "addis %0,%2,%1@toc@ha"; + + else if (TARGET_XCOFF) + addis_str = "addis %0,%1@u(%2)"; + + else + gcc_unreachable (); + } + + else if (GET_CODE (value) == PLUS) + { + rtx op0 = XEXP (value, 0); + rtx op1 = XEXP (value, 1); + + if (GET_CODE (op0) == UNSPEC + && XINT (op0, 1) == UNSPEC_TOCREL + && CONST_INT_P (op1)) + { + fuse_ops[1] = XVECEXP (op0, 0, 0); /* symbol ref. */ + fuse_ops[2] = XVECEXP (op0, 0, 1); /* TOC register. */ + fuse_ops[3] = op1; + if (TARGET_ELF) + addis_str = "addis %0,%2,%1+%3@toc@ha"; + + else if (TARGET_XCOFF) + addis_str = "addis %0,%1+%3@u(%2)"; + + else + gcc_unreachable (); + } + } + + else if (satisfies_constraint_L (value)) + { + fuse_ops[1] = value; + addis_str = "lis %0,%v1"; + } + + else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (value)) + { + fuse_ops[1] = value; + addis_str = "lis %0,%1@ha"; + } + } + + if (!addis_str) + fatal_insn ("Could not generate addis value for fusion", addis_value); + + sprintf (insn_template, "%s\t\t%s gpr load fusion, type %s", addis_str, + comment_str, mode_name); + output_asm_insn (insn_template, fuse_ops); + + /* Emit the D-form load instruction. */ + if (CONST_INT_P (load_offset) && satisfies_constraint_I (load_offset)) + { + sprintf (insn_template, "%s %%0,%%1(%%0)", load_str); + fuse_ops[1] = load_offset; + output_asm_insn (insn_template, fuse_ops); + } + + else if (GET_CODE (load_offset) == UNSPEC + && XINT (load_offset, 1) == UNSPEC_TOCREL) + { + if (TARGET_ELF) + sprintf (insn_template, "%s %%0,%%1@toc@l(%%0)", load_str); + + else if (TARGET_XCOFF) + sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str); + + else + gcc_unreachable (); + + fuse_ops[1] = XVECEXP (load_offset, 0, 0); + output_asm_insn (insn_template, fuse_ops); + } + + else if (GET_CODE (load_offset) == PLUS + && GET_CODE (XEXP (load_offset, 0)) == UNSPEC + && XINT (XEXP (load_offset, 0), 1) == UNSPEC_TOCREL + && CONST_INT_P (XEXP (load_offset, 1))) + { + rtx tocrel_unspec = XEXP (load_offset, 0); + if (TARGET_ELF) + sprintf (insn_template, "%s %%0,%%1+%%2@toc@l(%%0)", load_str); + + else if (TARGET_XCOFF) + sprintf (insn_template, "%s %%0,%%1+%%2@l(%%0)", load_str); + + else + gcc_unreachable (); + + fuse_ops[1] = XVECEXP (tocrel_unspec, 0, 0); + fuse_ops[2] = XEXP (load_offset, 1); + output_asm_insn (insn_template, fuse_ops); + } + + else if (TARGET_ELF && !TARGET_POWERPC64 && CONSTANT_P (load_offset)) + { + sprintf (insn_template, "%s %%0,%%1@l(%%0)", load_str); + + fuse_ops[1] = load_offset; + output_asm_insn (insn_template, fuse_ops); + } + + else + fatal_insn ("Unable to generate load offset for fusion", load_offset); + + /* Handle sign extension. The peephole2 pass generates this as a separate + insn, but we handle it just in case it got reattached. */ + if (sign_p) + { + gcc_assert (extend_insn != NULL); + output_asm_insn (extend_insn, fuse_ops); + } + + return ""; +} + + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" diff --git a/gcc-4.8/gcc/config/rs6000/rs6000.h b/gcc-4.8/gcc/config/rs6000/rs6000.h index 8a3608410..1dc71f6db 100644 --- a/gcc-4.8/gcc/config/rs6000/rs6000.h +++ b/gcc-4.8/gcc/config/rs6000/rs6000.h @@ -92,7 +92,7 @@ #ifdef HAVE_AS_POWER8 #define ASM_CPU_POWER8_SPEC "-mpower8" #else -#define ASM_CPU_POWER8_SPEC "-mpower4 -maltivec" +#define ASM_CPU_POWER8_SPEC ASM_CPU_POWER7_SPEC #endif #ifdef HAVE_AS_DCI @@ -164,6 +164,7 @@ %{mcpu=e6500: -me6500} \ %{maltivec: -maltivec} \ %{mvsx: -mvsx %{!maltivec: -maltivec} %{!mcpu*: %(asm_cpu_power7)}} \ +%{mpower8-vector|mcrypto|mdirect-move|mhtm: %{!mcpu*: %(asm_cpu_power8)}} \ -many" #define CPP_DEFAULT_SPEC "" @@ -277,6 +278,21 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define TARGET_POPCNTD 0 #endif +/* Define the ISA 2.07 flags as 0 if the target assembler does not support the + waitasecond instruction. Allow -mpower8-fusion, since it does not add new + instructions. */ + +#ifndef HAVE_AS_POWER8 +#undef TARGET_DIRECT_MOVE +#undef TARGET_CRYPTO +#undef TARGET_HTM +#undef TARGET_P8_VECTOR +#define TARGET_DIRECT_MOVE 0 +#define TARGET_CRYPTO 0 +#define TARGET_HTM 0 +#define TARGET_P8_VECTOR 0 +#endif + /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If not, generate the lwsync code as an integer constant. */ #ifdef HAVE_AS_LWSYNC @@ -386,6 +402,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define TARGET_DEBUG_TARGET (rs6000_debug & MASK_DEBUG_TARGET) #define TARGET_DEBUG_BUILTIN (rs6000_debug & MASK_DEBUG_BUILTIN) +/* Describe the vector unit used for arithmetic operations. */ extern enum rs6000_vector rs6000_vector_unit[]; #define VECTOR_UNIT_NONE_P(MODE) \ @@ -394,12 +411,25 @@ extern enum rs6000_vector rs6000_vector_unit[]; #define VECTOR_UNIT_VSX_P(MODE) \ (rs6000_vector_unit[(MODE)] == VECTOR_VSX) +#define VECTOR_UNIT_P8_VECTOR_P(MODE) \ + (rs6000_vector_unit[(MODE)] == VECTOR_P8_VECTOR) + #define VECTOR_UNIT_ALTIVEC_P(MODE) \ (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) +#define VECTOR_UNIT_VSX_OR_P8_VECTOR_P(MODE) \ + (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ + (int)VECTOR_VSX, \ + (int)VECTOR_P8_VECTOR)) + +/* VECTOR_UNIT_ALTIVEC_OR_VSX_P is used in places where we are using either + altivec (VMX) or VSX vector instructions. P8 vector support is upwards + compatible, so allow it as well, rather than changing all of the uses of the + macro. */ #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ - (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \ - || rs6000_vector_unit[(MODE)] == VECTOR_VSX) + (IN_RANGE ((int)rs6000_vector_unit[(MODE)], \ + (int)VECTOR_ALTIVEC, \ + (int)VECTOR_P8_VECTOR)) /* Describe whether to use VSX loads or Altivec loads. For now, just use the same unit as the vector unit we are using, but we may want to migrate to @@ -412,12 +442,21 @@ extern enum rs6000_vector rs6000_vector_mem[]; #define VECTOR_MEM_VSX_P(MODE) \ (rs6000_vector_mem[(MODE)] == VECTOR_VSX) +#define VECTOR_MEM_P8_VECTOR_P(MODE) \ + (rs6000_vector_mem[(MODE)] == VECTOR_VSX) + #define VECTOR_MEM_ALTIVEC_P(MODE) \ (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) +#define VECTOR_MEM_VSX_OR_P8_VECTOR_P(MODE) \ + (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ + (int)VECTOR_VSX, \ + (int)VECTOR_P8_VECTOR)) + #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ - (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \ - || rs6000_vector_mem[(MODE)] == VECTOR_VSX) + (IN_RANGE ((int)rs6000_vector_mem[(MODE)], \ + (int)VECTOR_ALTIVEC, \ + (int)VECTOR_P8_VECTOR)) /* Return the alignment of a given vector type, which is set based on the vector unit use. VSX for instance can load 32 or 64 bit aligned words @@ -429,6 +468,15 @@ extern int rs6000_vector_align[]; ? rs6000_vector_align[(MODE)] \ : (int)GET_MODE_BITSIZE ((MODE))) +/* Determine the element order to use for vector instructions. By + default we use big-endian element order when targeting big-endian, + and little-endian element order when targeting little-endian. For + programs being ported from BE Power to LE Power, it can sometimes + be useful to use big-endian element order when targeting little-endian. + This is set via -maltivec=be, for example. */ +#define VECTOR_ELT_ORDER_BIG \ + (BYTES_BIG_ENDIAN || (rs6000_altivec_element_order == 2)) + /* Alignment options for fields in structures for sub-targets following AIX-like ABI. ALIGN_POWER word-aligns FP doubles (default AIX ABI). @@ -479,22 +527,45 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIDUZ TARGET_POPCNTD #define TARGET_FCTIWUZ TARGET_POPCNTD +#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) +#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) +#define TARGET_VADDUQM (TARGET_P8_VECTOR && TARGET_POWERPC64) + +/* Byte/char syncs were added as phased in for ISA 2.06B, but are not present + in power7, so conditionalize them on p8 features. TImode syncs need quad + memory support. */ +#define TARGET_SYNC_HI_QI (TARGET_QUAD_MEMORY \ + || TARGET_QUAD_MEMORY_ATOMIC \ + || TARGET_DIRECT_MOVE) + +#define TARGET_SYNC_TI TARGET_QUAD_MEMORY_ATOMIC + +/* Power7 has both 32-bit load and store integer for the FPRs, so we don't need + to allocate the SDmode stack slot to get the value into the proper location + in the register. */ +#define TARGET_NO_SDMODE_STACK (TARGET_LFIWZX && TARGET_STFIWX && TARGET_DFP) + /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_ instead of MASK_. For now map OPTION_MASK_ back into MASK_. */ #define MASK_ALTIVEC OPTION_MASK_ALTIVEC #define MASK_CMPB OPTION_MASK_CMPB +#define MASK_CRYPTO OPTION_MASK_CRYPTO #define MASK_DFP OPTION_MASK_DFP +#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE #define MASK_DLMZB OPTION_MASK_DLMZB #define MASK_EABI OPTION_MASK_EABI #define MASK_FPRND OPTION_MASK_FPRND +#define MASK_P8_FUSION OPTION_MASK_P8_FUSION #define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT +#define MASK_HTM OPTION_MASK_HTM #define MASK_ISEL OPTION_MASK_ISEL #define MASK_MFCRF OPTION_MASK_MFCRF #define MASK_MFPGPR OPTION_MASK_MFPGPR #define MASK_MULHW OPTION_MASK_MULHW #define MASK_MULTIPLE OPTION_MASK_MULTIPLE #define MASK_NO_UPDATE OPTION_MASK_NO_UPDATE +#define MASK_P8_VECTOR OPTION_MASK_P8_VECTOR #define MASK_POPCNTB OPTION_MASK_POPCNTB #define MASK_POPCNTD OPTION_MASK_POPCNTD #define MASK_PPC_GFXOPT OPTION_MASK_PPC_GFXOPT @@ -505,6 +576,7 @@ extern int rs6000_vector_align[]; #define MASK_STRING OPTION_MASK_STRING #define MASK_UPDATE OPTION_MASK_UPDATE #define MASK_VSX OPTION_MASK_VSX +#define MASK_VSX_TIMODE OPTION_MASK_VSX_TIMODE #ifndef IN_LIBGCC2 #define MASK_POWERPC64 OPTION_MASK_POWERPC64 @@ -551,13 +623,33 @@ extern int rs6000_vector_align[]; || TARGET_CMPB /* ISA 2.05 */ \ || TARGET_POPCNTD /* ISA 2.06 */ \ || TARGET_ALTIVEC \ - || TARGET_VSX))) + || TARGET_VSX \ + || TARGET_HARD_FLOAT))) /* E500 cores only support plain "sync", not lwsync. */ #define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \ || rs6000_cpu == PROCESSOR_PPC8548) +/* Whether SF/DF operations are supported on the E500. */ +#define TARGET_SF_SPE (TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT \ + && !TARGET_FPRS) + +#define TARGET_DF_SPE (TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT \ + && !TARGET_FPRS && TARGET_E500_DOUBLE) + +/* Whether SF/DF operations are supported by by the normal floating point unit + (or the vector/scalar unit). */ +#define TARGET_SF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ + && TARGET_SINGLE_FLOAT) + +#define TARGET_DF_FPR (TARGET_HARD_FLOAT && TARGET_FPRS \ + && TARGET_DOUBLE_FLOAT) + +/* Whether SF/DF operations are supported by any hardware. */ +#define TARGET_SF_INSN (TARGET_SF_FPR || TARGET_SF_SPE) +#define TARGET_DF_INSN (TARGET_DF_FPR || TARGET_DF_SPE) + /* Which machine supports the various reciprocal estimate instructions. */ #define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \ && TARGET_FPRS && TARGET_SINGLE_FLOAT) @@ -595,9 +687,6 @@ extern unsigned char rs6000_recip_bits[]; #define RS6000_RECIP_AUTO_RSQRTE_P(MODE) \ (rs6000_recip_bits[(int)(MODE)] & RS6000_RECIP_MASK_AUTO_RSQRTE) -#define RS6000_RECIP_HIGH_PRECISION_P(MODE) \ - ((MODE) == SFmode || (MODE) == V4SFmode || TARGET_RECIP_PRECISION) - /* The default CPU for TARGET_OPTION_OVERRIDE. */ #define OPTION_TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT @@ -760,12 +849,6 @@ extern unsigned rs6000_pointer_size; /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 128 -/* A C expression to compute the alignment for a variables in the - local store. TYPE is the data type, and ALIGN is the alignment - that the object would ordinarily have. */ -#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ - DATA_ALIGNMENT (TYPE, ALIGN) - /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 @@ -775,8 +858,15 @@ extern unsigned rs6000_pointer_size; /* A bit-field declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 -/* Make strings word-aligned so strcpy from constants will be faster. - Make vector constants quadword aligned. */ +enum data_align { align_abi, align_opt, align_both }; + +/* A C expression to compute the alignment for a variables in the + local store. TYPE is the data type, and ALIGN is the alignment + that the object would ordinarily have. */ +#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ + rs6000_data_alignment (TYPE, ALIGN, align_both) + +/* Make strings word-aligned so strcpy from constants will be faster. */ #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ (TREE_CODE (EXP) == STRING_CST \ && (STRICT_ALIGNMENT || !optimize_size) \ @@ -784,21 +874,14 @@ extern unsigned rs6000_pointer_size; ? BITS_PER_WORD \ : (ALIGN)) -/* Make arrays of chars word-aligned for the same reasons. - Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to - 64 bits. */ +/* Make arrays of chars word-aligned for the same reasons. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ - (TREE_CODE (TYPE) == VECTOR_TYPE \ - ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \ - || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \ - ? 64 : 128) \ - : ((TARGET_E500_DOUBLE \ - && TREE_CODE (TYPE) == REAL_TYPE \ - && TYPE_MODE (TYPE) == DFmode) \ - ? 64 \ - : (TREE_CODE (TYPE) == ARRAY_TYPE \ - && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ - && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) + rs6000_data_alignment (TYPE, ALIGN, align_opt) + +/* Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to + 64 bits. */ +#define DATA_ABI_ALIGNMENT(TYPE, ALIGN) \ + rs6000_data_alignment (TYPE, ALIGN, align_abi) /* Nonzero if move instructions will actually fail to work when given unaligned data. */ @@ -842,15 +925,17 @@ extern unsigned rs6000_pointer_size; in inline functions. Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame - pointer, which is eventually eliminated in favor of SP or FP. */ + pointer, which is eventually eliminated in favor of SP or FP. -#define FIRST_PSEUDO_REGISTER 114 + The 3 HTM registers aren't also included in DWARF_FRAME_REGISTERS. */ + +#define FIRST_PSEUDO_REGISTER 117 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 /* Add 32 dwarf columns for synthetic SPE registers. */ -#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) +#define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 4) + 32) /* The SPE has an additional 32 synthetic registers, with DWARF debug info numbering for these registers starting at 1200. While eh_frame @@ -866,7 +951,7 @@ extern unsigned rs6000_pointer_size; We must map them here to avoid huge unwinder tables mostly consisting of unused space. */ #define DWARF_REG_TO_UNWIND_COLUMN(r) \ - ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) + ((r) > 1200 ? ((r) - 1200 + (DWARF_FRAME_REGISTERS - 32)) : (r)) /* Use standard DWARF numbering for DWARF debugging information. */ #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) @@ -906,7 +991,7 @@ extern unsigned rs6000_pointer_size; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1 \ } /* 1 for registers not available across function calls. @@ -926,7 +1011,7 @@ extern unsigned rs6000_pointer_size; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 1, 1 \ - , 1, 1, 1 \ + , 1, 1, 1, 1, 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -945,7 +1030,7 @@ extern unsigned rs6000_pointer_size; 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 \ - , 0, 0, 0 \ + , 0, 0, 0, 0, 0, 0 \ } #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) @@ -984,6 +1069,9 @@ extern unsigned rs6000_pointer_size; vrsave, vscr (fixed) spe_acc, spefscr (fixed) sfp (fixed) + tfhar (fixed) + tfiar (fixed) + texasr (fixed) */ #if FIXED_R2 == 1 @@ -1004,7 +1092,9 @@ extern unsigned rs6000_pointer_size; #define REG_ALLOC_ORDER \ {32, \ - 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ + /* move fr13 (ie 45) later, so if we need TFmode, it does */ \ + /* not use fr14 which is a saved register. */ \ + 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, 45, \ 33, \ 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 50, 49, 48, 47, 46, \ @@ -1023,7 +1113,7 @@ extern unsigned rs6000_pointer_size; 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 109, 110, \ - 111, 112, 113 \ + 111, 112, 113, 114, 115, 116 \ } /* True if register is floating-point. */ @@ -1064,8 +1154,11 @@ extern unsigned rs6000_pointer_size; #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) /* Alternate name for any vector register supporting logical operations, no - matter which instruction set(s) are available. */ -#define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N) + matter which instruction set(s) are available. Allow GPRs as well as the + vector registers. */ +#define VLOGICAL_REGNO_P(N) \ + (INT_REGNO_P (N) || ALTIVEC_REGNO_P (N) \ + || (TARGET_VSX && FP_REGNO_P (N))) \ /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. */ @@ -1106,7 +1199,7 @@ extern unsigned rs6000_pointer_size; #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ - || (MODE) == V2DImode) + || (MODE) == V2DImode || (MODE) == V1TImode) #define SPE_VECTOR_MODE(MODE) \ ((MODE) == V4HImode \ @@ -1125,28 +1218,32 @@ extern unsigned rs6000_pointer_size; /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, - for any hard reg, then this must be 0 for correct output. */ + for any hard reg, then this must be 0 for correct output. + + PTImode cannot tie with other modes because PTImode is restricted to even + GPR registers, and TImode can go in any GPR as well as VSX registers (PR + 57744). */ #define MODES_TIEABLE_P(MODE1, MODE2) \ - (SCALAR_FLOAT_MODE_P (MODE1) \ + ((MODE1) == PTImode \ + ? (MODE2) == PTImode \ + : (MODE2) == PTImode \ + ? 0 \ + : SCALAR_FLOAT_MODE_P (MODE1) \ ? SCALAR_FLOAT_MODE_P (MODE2) \ : SCALAR_FLOAT_MODE_P (MODE2) \ - ? SCALAR_FLOAT_MODE_P (MODE1) \ + ? 0 \ : GET_MODE_CLASS (MODE1) == MODE_CC \ ? GET_MODE_CLASS (MODE2) == MODE_CC \ : GET_MODE_CLASS (MODE2) == MODE_CC \ - ? GET_MODE_CLASS (MODE1) == MODE_CC \ + ? 0 \ : SPE_VECTOR_MODE (MODE1) \ ? SPE_VECTOR_MODE (MODE2) \ : SPE_VECTOR_MODE (MODE2) \ - ? SPE_VECTOR_MODE (MODE1) \ - : ALTIVEC_VECTOR_MODE (MODE1) \ - ? ALTIVEC_VECTOR_MODE (MODE2) \ - : ALTIVEC_VECTOR_MODE (MODE2) \ - ? ALTIVEC_VECTOR_MODE (MODE1) \ + ? 0 \ : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ - ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ + ? 0 \ : 1) /* Post-reload, we can't use any new AltiVec registers, as we already @@ -1240,6 +1337,7 @@ enum reg_class VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, + SPR_REGS, NON_SPECIAL_REGS, LINK_REGS, CTR_REGS, @@ -1270,6 +1368,7 @@ enum reg_class "VSCR_REGS", \ "SPE_ACC_REGS", \ "SPEFSCR_REGS", \ + "SPR_REGS", \ "NON_SPECIAL_REGS", \ "LINK_REGS", \ "CTR_REGS", \ @@ -1299,6 +1398,7 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, /* SPR_REGS */ \ { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ @@ -1309,7 +1409,7 @@ enum reg_class { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ { 0xffffffff, 0x00000000, 0x00000ffe, 0x00020000 }, /* NON_FLOAT_REGS */ \ { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* CA_REGS */ \ - { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0003ffff } /* ALL_REGS */ \ + { 0xffffffff, 0xffffffff, 0xfffffffe, 0x0007ffff } /* ALL_REGS */ \ } /* The same information, inverted: @@ -1337,7 +1437,18 @@ enum r6000_reg_class_enum { RS6000_CONSTRAINT_wa, /* Any VSX register */ RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ + RS6000_CONSTRAINT_wg, /* FPR register for -mmfpgpr */ + RS6000_CONSTRAINT_wl, /* FPR register for LFIWAX */ + RS6000_CONSTRAINT_wm, /* VSX register for direct move */ + RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */ RS6000_CONSTRAINT_ws, /* VSX register for DF */ + RS6000_CONSTRAINT_wt, /* VSX register for TImode */ + RS6000_CONSTRAINT_wu, /* Altivec register for float load/stores. */ + RS6000_CONSTRAINT_wv, /* Altivec register for double load/stores. */ + RS6000_CONSTRAINT_ww, /* FP or VSX register for vsx float ops. */ + RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ + RS6000_CONSTRAINT_wy, /* VSX register for SF */ + RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ RS6000_CONSTRAINT_MAX }; @@ -1425,21 +1536,14 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; arguments. */ #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0 || flag_asan != 0) -/* Size of the outgoing register save area */ -#define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ - || DEFAULT_ABI == ABI_DARWIN) \ - ? (TARGET_64BIT ? 64 : 32) \ - : 0) - /* Size of the fixed area on the stack */ #define RS6000_SAVE_AREA \ - (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ + ((DEFAULT_ABI == ABI_V4 ? 8 : DEFAULT_ABI == ABI_ELFv2 ? 16 : 24) \ << (TARGET_64BIT ? 1 : 0)) -/* MEM representing address to save the TOC register */ -#define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ - plus_constant (Pmode, stack_pointer_rtx, \ - (TARGET_32BIT ? 20 : 40))) +/* Stack offset for toc save slot. */ +#define RS6000_TOC_SAVE_SLOT \ + ((DEFAULT_ABI == ABI_ELFv2 ? 12 : 20) << (TARGET_64BIT ? 1 : 0)) /* Align an address */ #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) @@ -1489,7 +1593,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; /* Define this if stack space is still allocated for a parameter passed in a register. The value is the number of bytes allocated to this area. */ -#define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE +#define REG_PARM_STACK_SPACE(FNDECL) rs6000_reg_parm_stack_space((FNDECL)) /* Define this if the above stack space is to be considered part of the space allocated by the caller. */ @@ -1522,7 +1626,7 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; NONLOCAL needs twice Pmode to maintain both backchain and SP. */ #define STACK_SAVEAREA_MODE(LEVEL) \ (LEVEL == SAVE_FUNCTION ? VOIDmode \ - : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) + : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : PTImode) : Pmode) /* Minimum and maximum general purpose registers used to hold arguments. */ #define GP_ARG_MIN_REG 3 @@ -1533,9 +1637,8 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; #define FP_ARG_MIN_REG 33 #define FP_ARG_AIX_MAX_REG 45 #define FP_ARG_V4_MAX_REG 40 -#define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ - || DEFAULT_ABI == ABI_DARWIN) \ - ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) +#define FP_ARG_MAX_REG (DEFAULT_ABI == ABI_V4 \ + ? FP_ARG_V4_MAX_REG : FP_ARG_AIX_MAX_REG) #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) /* Minimum and maximum AltiVec registers used to hold arguments. */ @@ -1543,10 +1646,17 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) +/* Maximum number of registers per ELFv2 homogeneous aggregate argument. */ +#define AGGR_ARG_NUM_REG 8 + /* Return registers */ #define GP_ARG_RETURN GP_ARG_MIN_REG #define FP_ARG_RETURN FP_ARG_MIN_REG #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) +#define FP_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? FP_ARG_RETURN \ + : (FP_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) +#define ALTIVEC_ARG_MAX_RETURN (DEFAULT_ABI != ABI_ELFv2 ? ALTIVEC_ARG_RETURN \ + : (ALTIVEC_ARG_RETURN + AGGR_ARG_NUM_REG - 1)) /* Flags for the call/call_value rtl operations set up by function_arg */ #define CALL_NORMAL 0x00000000 /* no special processing */ @@ -1566,8 +1676,10 @@ extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ #define FUNCTION_VALUE_REGNO_P(N) \ ((N) == GP_ARG_RETURN \ - || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ - || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) + || ((N) >= FP_ARG_RETURN && (N) <= FP_ARG_MAX_RETURN \ + && TARGET_HARD_FLOAT && TARGET_FPRS) \ + || ((N) >= ALTIVEC_ARG_RETURN && (N) <= ALTIVEC_ARG_MAX_RETURN \ + && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) /* 1 if N is a possible register number for function argument passing. On RS/6000, these are r3-r10 and fp1-fp13. @@ -1692,10 +1804,7 @@ typedef struct rs6000_args rs6000_stack_info in rs6000.c for more information on how the different abi's store the return address. */ #define RETURN_ADDRESS_OFFSET \ - ((DEFAULT_ABI == ABI_AIX \ - || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ - (DEFAULT_ABI == ABI_V4) ? 4 : \ - (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) + ((DEFAULT_ABI == ABI_V4 ? 4 : 8) << (TARGET_64BIT ? 1 : 0)) /* The current return address is in link register (65). The return address of anything farther back is accessed normally at an offset of 8 from the @@ -2215,6 +2324,9 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ &rs6000_reg_names[111][0], /* spe_acc */ \ &rs6000_reg_names[112][0], /* spefscr */ \ &rs6000_reg_names[113][0], /* sfp */ \ + &rs6000_reg_names[114][0], /* tfhar */ \ + &rs6000_reg_names[115][0], /* tfiar */ \ + &rs6000_reg_names[116][0], /* texasr */ \ } /* Table of additional register names to use in user input. */ @@ -2268,7 +2380,9 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ - {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} } + {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108}, \ + /* Transactional Memory Facility (HTM) Registers. */ \ + {"tfhar", 114}, {"tfiar", 115}, {"texasr", 116} } /* This is how to output an element of a case-vector that is relative. */ @@ -2357,7 +2471,12 @@ extern int frame_pointer_needed; #define RS6000_BTC_ATTR_MASK 0x00000700 /* Mask of the attributes. */ /* Miscellaneous information. */ -#define RS6000_BTC_OVERLOADED 0x4000000 /* function is overloaded. */ +#define RS6000_BTC_SPR 0x01000000 /* function references SPRs. */ +#define RS6000_BTC_VOID 0x02000000 /* function has no return value. */ +#define RS6000_BTC_OVERLOADED 0x04000000 /* function is overloaded. */ +#define RS6000_BTC_32BIT 0x08000000 /* function references SPRs. */ +#define RS6000_BTC_64BIT 0x10000000 /* function references SPRs. */ +#define RS6000_BTC_MISC_MASK 0x1f000000 /* Mask of the misc info. */ /* Convenience macros to document the instruction type. */ #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches mem. */ @@ -2369,6 +2488,9 @@ extern int frame_pointer_needed; #define RS6000_BTM_ALWAYS 0 /* Always enabled. */ #define RS6000_BTM_ALTIVEC MASK_ALTIVEC /* VMX/altivec vectors. */ #define RS6000_BTM_VSX MASK_VSX /* VSX (vector/scalar). */ +#define RS6000_BTM_P8_VECTOR MASK_P8_VECTOR /* ISA 2.07 vector. */ +#define RS6000_BTM_CRYPTO MASK_CRYPTO /* crypto funcs. */ +#define RS6000_BTM_HTM MASK_HTM /* hardware TM funcs. */ #define RS6000_BTM_SPE MASK_STRING /* E500 */ #define RS6000_BTM_PAIRED MASK_MULHW /* 750CL paired insns. */ #define RS6000_BTM_FRE MASK_POPCNTB /* FRE instruction. */ @@ -2377,15 +2499,22 @@ extern int frame_pointer_needed; #define RS6000_BTM_FRSQRTES MASK_POPCNTB /* FRSQRTES instruction. */ #define RS6000_BTM_POPCNTD MASK_POPCNTD /* Target supports ISA 2.06. */ #define RS6000_BTM_CELL MASK_FPRND /* Target is cell powerpc. */ +#define RS6000_BTM_DFP MASK_DFP /* Decimal floating point. */ +#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */ #define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \ | RS6000_BTM_VSX \ + | RS6000_BTM_P8_VECTOR \ + | RS6000_BTM_CRYPTO \ | RS6000_BTM_FRE \ | RS6000_BTM_FRES \ | RS6000_BTM_FRSQRTE \ | RS6000_BTM_FRSQRTES \ + | RS6000_BTM_HTM \ | RS6000_BTM_POPCNTD \ - | RS6000_BTM_CELL) + | RS6000_BTM_CELL \ + | RS6000_BTM_DFP \ + | RS6000_BTM_HARD_FLOAT) /* Define builtin enum index. */ @@ -2395,6 +2524,7 @@ extern int frame_pointer_needed; #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E +#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S @@ -2406,6 +2536,7 @@ extern int frame_pointer_needed; #define RS6000_BUILTIN_A(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_D(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_E(ENUM, NAME, MASK, ATTR, ICODE) ENUM, +#define RS6000_BUILTIN_H(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_P(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_Q(ENUM, NAME, MASK, ATTR, ICODE) ENUM, #define RS6000_BUILTIN_S(ENUM, NAME, MASK, ATTR, ICODE) ENUM, @@ -2424,6 +2555,7 @@ enum rs6000_builtins #undef RS6000_BUILTIN_A #undef RS6000_BUILTIN_D #undef RS6000_BUILTIN_E +#undef RS6000_BUILTIN_H #undef RS6000_BUILTIN_P #undef RS6000_BUILTIN_Q #undef RS6000_BUILTIN_S @@ -2437,6 +2569,7 @@ enum rs6000_builtin_type_index RS6000_BTI_opaque_p_V2SI, RS6000_BTI_opaque_V4SI, RS6000_BTI_V16QI, + RS6000_BTI_V1TI, RS6000_BTI_V2SI, RS6000_BTI_V2SF, RS6000_BTI_V2DI, @@ -2446,6 +2579,7 @@ enum rs6000_builtin_type_index RS6000_BTI_V4SF, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, + RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, @@ -2471,8 +2605,13 @@ enum rs6000_builtin_type_index RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ RS6000_BTI_INTDI, /* intDI_type_node */ RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ + RS6000_BTI_INTTI, /* intTI_type_node */ + RS6000_BTI_UINTTI, /* unsigned_intTI_type_node */ RS6000_BTI_float, /* float_type_node */ RS6000_BTI_double, /* double_type_node */ + RS6000_BTI_long_double, /* long_double_type_node */ + RS6000_BTI_dfloat64, /* dfloat64_type_node */ + RS6000_BTI_dfloat128, /* dfloat128_type_node */ RS6000_BTI_void, /* void_type_node */ RS6000_BTI_MAX }; @@ -2483,6 +2622,7 @@ enum rs6000_builtin_type_index #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) +#define V1TI_type_node (rs6000_builtin_types[RS6000_BTI_V1TI]) #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) @@ -2492,6 +2632,7 @@ enum rs6000_builtin_type_index #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) +#define unsigned_V1TI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V1TI]) #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) @@ -2518,8 +2659,13 @@ enum rs6000_builtin_type_index #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) +#define intTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTTI]) +#define uintTI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTTI]) #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) +#define long_double_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_double]) +#define dfloat64_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat64]) +#define dfloat128_type_internal_node (rs6000_builtin_types[RS6000_BTI_dfloat128]) #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; diff --git a/gcc-4.8/gcc/config/rs6000/rs6000.md b/gcc-4.8/gcc/config/rs6000/rs6000.md index ade39ea5f..8f1fd769b 100644 --- a/gcc-4.8/gcc/config/rs6000/rs6000.md +++ b/gcc-4.8/gcc/config/rs6000/rs6000.md @@ -25,10 +25,14 @@ ;; (define_constants - [(STACK_POINTER_REGNUM 1) + [(FIRST_GPR_REGNO 0) + (STACK_POINTER_REGNUM 1) (TOC_REGNUM 2) (STATIC_CHAIN_REGNUM 11) (HARD_FRAME_POINTER_REGNUM 31) + (LAST_GPR_REGNO 31) + (FIRST_FPR_REGNO 32) + (LAST_FPR_REGNO 63) (LR_REGNO 65) (CTR_REGNO 66) (ARG_POINTER_REGNUM 67) @@ -49,18 +53,9 @@ (SPE_ACC_REGNO 111) (SPEFSCR_REGNO 112) (FRAME_POINTER_REGNUM 113) - - ; ABI defined stack offsets for storing the TOC pointer with AIX calls. - (TOC_SAVE_OFFSET_32BIT 20) - (TOC_SAVE_OFFSET_64BIT 40) - - ; Function TOC offset in the AIX function descriptor. - (AIX_FUNC_DESC_TOC_32BIT 4) - (AIX_FUNC_DESC_TOC_64BIT 8) - - ; Static chain offset in the AIX function descriptor. - (AIX_FUNC_DESC_SC_32BIT 8) - (AIX_FUNC_DESC_SC_64BIT 16) + (TFHAR_REGNO 114) + (TFIAR_REGNO 115) + (TEXASR_REGNO 116) ]) ;; @@ -123,6 +118,22 @@ UNSPEC_LFIWZX UNSPEC_FCTIWUZ UNSPEC_GRP_END_NOP + UNSPEC_P8V_FMRGOW + UNSPEC_P8V_MTVSRWZ + UNSPEC_P8V_RELOAD_FROM_GPR + UNSPEC_P8V_MTVSRD + UNSPEC_P8V_XXPERMDI + UNSPEC_P8V_RELOAD_FROM_VSX + UNSPEC_ADDG6S + UNSPEC_CDTBCD + UNSPEC_CBCDTD + UNSPEC_DIVE + UNSPEC_DIVEO + UNSPEC_DIVEU + UNSPEC_DIVEUO + UNSPEC_UNPACK_128BIT + UNSPEC_PACK_128BIT + UNSPEC_LSQ ]) ;; @@ -142,7 +153,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt" +(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm" (const_string "integer")) ;; Define floating point instruction sub-types for use with Xfpu.md @@ -164,7 +175,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan" +(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan,power8" (const (symbol_ref "rs6000_cpu_attr"))) @@ -197,6 +208,7 @@ (include "power5.md") (include "power6.md") (include "power7.md") +(include "power8.md") (include "cell.md") (include "xfpu.md") (include "a2.md") @@ -215,7 +227,7 @@ (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")]) ; Any supported integer mode. -(define_mode_iterator INT [QI HI SI DI TI]) +(define_mode_iterator INT [QI HI SI DI TI PTI]) ; Any supported integer mode that fits in one register. (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")]) @@ -223,6 +235,12 @@ ; extend modes for DImode (define_mode_iterator QHSI [QI HI SI]) +; QImode or HImode for small atomic ops +(define_mode_iterator QHI [QI HI]) + +; HImode or SImode for sign extended fusion ops +(define_mode_iterator HSI [HI SI]) + ; SImode or DImode, even if DImode doesn't fit in GPRs. (define_mode_iterator SDI [SI DI]) @@ -230,6 +248,10 @@ ; (one with a '.') will compare; and the size used for arithmetic carries. (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) +; Iterator to add PTImode along with TImode (TImode can go in VSX registers, +; PTImode is GPR only) +(define_mode_iterator TI2 [TI PTI]) + ; Any hardware-supported floating-point mode (define_mode_iterator FP [ (SF "TARGET_HARD_FLOAT @@ -253,6 +275,50 @@ (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)") ]) +; Floating point move iterators to combine binary and decimal moves +(define_mode_iterator FMOVE32 [SF SD]) +(define_mode_iterator FMOVE64 [DF DD]) +(define_mode_iterator FMOVE64X [DI DF DD]) +(define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128") + (TD "TARGET_HARD_FLOAT && TARGET_FPRS")]) + +; Iterators for 128 bit types for direct move +(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE") + (V16QI "") + (V8HI "") + (V4SI "") + (V4SF "") + (V2DI "") + (V2DF "") + (V1TI "")]) + +; Whether a floating point move is ok, don't allow SD without hardware FP +(define_mode_attr fmove_ok [(SF "") + (DF "") + (SD "TARGET_HARD_FLOAT && TARGET_FPRS") + (DD "")]) + +; Convert REAL_VALUE to the appropriate bits +(define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE") + (DF "REAL_VALUE_TO_TARGET_DOUBLE") + (SD "REAL_VALUE_TO_TARGET_DECIMAL32") + (DD "REAL_VALUE_TO_TARGET_DECIMAL64")]) + +; Definitions for load to 32-bit fpr register +(define_mode_attr f32_lr [(SF "f") (SD "wz")]) +(define_mode_attr f32_lm [(SF "m") (SD "Z")]) +(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")]) +(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")]) + +; Definitions for store from 32-bit fpr register +(define_mode_attr f32_sr [(SF "f") (SD "wx")]) +(define_mode_attr f32_sm [(SF "m") (SD "Z")]) +(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")]) +(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")]) + +; Definitions for 32-bit fpr direct move +(define_mode_attr f32_dm [(SF "wn") (SD "wm")]) + ; These modes do not fit in integer registers in 32-bit mode. ; but on e500v2, the gpr are 64 bit registers (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD]) @@ -263,6 +329,25 @@ ; Iterator for just SF/DF (define_mode_iterator SFDF [SF DF]) +; SF/DF suffix for traditional floating instructions +(define_mode_attr Ftrad [(SF "s") (DF "")]) + +; SF/DF suffix for VSX instructions +(define_mode_attr Fvsx [(SF "sp") (DF "dp")]) + +; SF/DF constraint for arithmetic on traditional floating point registers +(define_mode_attr Ff [(SF "f") (DF "d")]) + +; SF/DF constraint for arithmetic on VSX registers +(define_mode_attr Fv [(SF "wy") (DF "ws")]) + +; s/d suffix for things like fp_addsub_s/fp_addsub_d +(define_mode_attr Fs [(SF "s") (DF "d")]) + +; FRE/FRES support +(define_mode_attr Ffre [(SF "fres") (DF "fre")]) +(define_mode_attr FFRE [(SF "FRES") (DF "FRE")]) + ; Conditional returns. (define_code_iterator any_return [return simple_return]) (define_code_attr return_pred [(return "direct_return ()") @@ -271,7 +356,14 @@ ; Various instructions that come in SI and DI forms. ; A generic w/d attribute, for things like cmpw/cmpd. -(define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")]) +(define_mode_attr wd [(QI "b") + (HI "h") + (SI "w") + (DI "d") + (V16QI "b") + (V8HI "h") + (V4SI "w") + (V2DI "d")]) ; DImode bits (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) @@ -297,6 +389,8 @@ (define_mode_attr rreg [(SF "f") (DF "ws") + (TF "f") + (TD "f") (V4SF "wf") (V2DF "wd")]) @@ -312,6 +406,87 @@ (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT") (DF "TARGET_DOUBLE_FLOAT")]) +;; Mode iterator for logical operations on 128-bit types +(define_mode_iterator BOOL_128 [TI + PTI + (V16QI "TARGET_ALTIVEC") + (V8HI "TARGET_ALTIVEC") + (V4SI "TARGET_ALTIVEC") + (V4SF "TARGET_ALTIVEC") + (V2DI "TARGET_ALTIVEC") + (V2DF "TARGET_ALTIVEC") + (V1TI "TARGET_ALTIVEC")]) + +;; For the GPRs we use 3 constraints for register outputs, two that are the +;; same as the output register, and a third where the output register is an +;; early clobber, so we don't have to deal with register overlaps. For the +;; vector types, we prefer to use the vector registers. For TI mode, allow +;; either. + +;; Mode attribute for boolean operation register constraints for output +(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wa,v") + (PTI "&r,r,r") + (V16QI "wa,v,&?r,?r,?r") + (V8HI "wa,v,&?r,?r,?r") + (V4SI "wa,v,&?r,?r,?r") + (V4SF "wa,v,&?r,?r,?r") + (V2DI "wa,v,&?r,?r,?r") + (V2DF "wa,v,&?r,?r,?r") + (V1TI "wa,v,&?r,?r,?r")]) + +;; Mode attribute for boolean operation register constraints for operand1 +(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wa,v") + (PTI "r,0,r") + (V16QI "wa,v,r,0,r") + (V8HI "wa,v,r,0,r") + (V4SI "wa,v,r,0,r") + (V4SF "wa,v,r,0,r") + (V2DI "wa,v,r,0,r") + (V2DF "wa,v,r,0,r") + (V1TI "wa,v,r,0,r")]) + +;; Mode attribute for boolean operation register constraints for operand2 +(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wa,v") + (PTI "r,r,0") + (V16QI "wa,v,r,r,0") + (V8HI "wa,v,r,r,0") + (V4SI "wa,v,r,r,0") + (V4SF "wa,v,r,r,0") + (V2DI "wa,v,r,r,0") + (V2DF "wa,v,r,r,0") + (V1TI "wa,v,r,r,0")]) + +;; Mode attribute for boolean operation register constraints for operand1 +;; for one_cmpl. To simplify things, we repeat the constraint where 0 +;; is used for operand1 or operand2 +(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wa,v") + (PTI "r,0,0") + (V16QI "wa,v,r,0,0") + (V8HI "wa,v,r,0,0") + (V4SI "wa,v,r,0,0") + (V4SF "wa,v,r,0,0") + (V2DI "wa,v,r,0,0") + (V2DF "wa,v,r,0,0") + (V1TI "wa,v,r,0,0")]) + +;; Mode attribute for the clobber of CC0 for AND expansion. +;; For the 128-bit types, we never do AND immediate, but we need to +;; get the correct number of X's for the number of operands. +(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X") + (PTI "X,X,X") + (V16QI "X,X,X,X,X") + (V8HI "X,X,X,X,X") + (V4SI "X,X,X,X,X") + (V4SF "X,X,X,X,X") + (V2DI "X,X,X,X,X") + (V2DF "X,X,X,X,X") + (V1TI "X,X,X,X,X")]) + +;; Mode attribute to give the correct type for integer divides +(define_mode_attr idiv_ldiv [(SI "idiv") + (DI "ldiv")]) + + ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. @@ -324,11 +499,19 @@ (define_insn "*zero_extenddi2_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && (mode != SImode || !TARGET_LFIWZX)" "@ lz%U1%X1 %0,%1 rldicl %0,%1,0," - [(set_attr "type" "load,*")]) + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*")])]) (define_insn "*zero_extenddi2_internal2" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -382,6 +565,29 @@ (const_int 0)))] "") +(define_insn "*zero_extendsidi2_lfiwzx" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wz,!wu") + (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] + "TARGET_POWERPC64 && TARGET_LFIWZX" + "@ + lwz%U1%X1 %0,%1 + rldicl %0,%1,0,32 + mtvsrwz %x0,%1 + lfiwzx %0,%y1 + lxsiwzx %x0,%y1" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*") + (const_string "mffgpr") + (const_string "fpload") + (const_string "fpload")])]) + (define_insn "extendqidi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] @@ -454,7 +660,15 @@ "@ lha%U1%X1 %0,%1 extsh %0,%1" - [(set_attr "type" "load_ext,exts")]) + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_u") + (const_string "load_ext"))) + (const_string "exts")])]) (define_insn "" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -521,16 +735,47 @@ "TARGET_POWERPC64" "") -(define_insn "" +(define_insn "*extendsidi2_lfiwax" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wm,!wl,!wu") + (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r,r,Z,Z")))] + "TARGET_POWERPC64 && TARGET_LFIWAX" + "@ + lwa%U1%X1 %0,%1 + extsw %0,%1 + mtvsrwa %x0,%1 + lfiwax %0,%y1 + lxsiwax %x0,%y1" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_u") + (const_string "load_ext"))) + (const_string "exts") + (const_string "mffgpr") + (const_string "fpload") + (const_string "fpload")])]) + +(define_insn "*extendsidi2_nocell" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] - "TARGET_POWERPC64 && rs6000_gen_cell_microcode" + "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX" "@ lwa%U1%X1 %0,%1 extsw %0,%1" - [(set_attr "type" "load_ext,exts")]) - -(define_insn "" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_u") + (const_string "load_ext"))) + (const_string "exts")])]) + +(define_insn "*extendsidi2_nocell" [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))] "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" @@ -602,7 +847,15 @@ "@ lbz%U1%X1 %0,%1 rlwinm %0,%1,0,0xff" - [(set_attr "type" "load,*")]) + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*")])]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -722,7 +975,15 @@ "@ lbz%U1%X1 %0,%1 rlwinm %0,%1,0,0xff" - [(set_attr "type" "load,*")]) + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*")])]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -848,7 +1109,15 @@ "@ lhz%U1%X1 %0,%1 rlwinm %0,%1,0,0xffff" - [(set_attr "type" "load,*")]) + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*")])]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -915,7 +1184,15 @@ "@ lha%U1%X1 %0,%1 extsh %0,%1" - [(set_attr "type" "load_ext,exts")]) + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_ext_u") + (const_string "load_ext"))) + (const_string "exts")])]) (define_insn "" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") @@ -1658,7 +1935,19 @@ FAIL; }) -(define_insn "one_cmpl2" +(define_expand "one_cmpl2" + [(set (match_operand:SDI 0 "gpc_reg_operand" "") + (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] + "" +{ + if (mode == DImode && !TARGET_POWERPC64) + { + rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX); + DONE; + } +}) + +(define_insn "*one_cmpl2" [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] "" @@ -1935,7 +2224,9 @@ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))] "TARGET_CMPB && TARGET_POPCNTB" - "prty %0,%1") + "prty %0,%1" + [(set_attr "length" "4") + (set_attr "type" "popcnt")]) (define_expand "parity2" [(set (match_operand:GPR 0 "gpc_reg_operand" "") @@ -2412,7 +2703,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "" + "TARGET_32BIT" "@ mullw. %3,%1,%2 #" @@ -2425,7 +2716,7 @@ (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) @@ -2440,7 +2731,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (mult:SI (match_dup 1) (match_dup 2)))] - "" + "TARGET_32BIT" "@ mullw. %0,%1,%2 #" @@ -2454,7 +2745,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (mult:SI (match_dup 1) (match_dup 2)))] - "reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (mult:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) @@ -2469,10 +2760,7 @@ (match_operand:GPR 2 "gpc_reg_operand" "r")))] "" "divu %0,%1,%2" - [(set (attr "type") - (cond [(match_operand:SI 0 "" "") - (const_string "idiv")] - (const_string "ldiv")))]) + [(set_attr "type" "")]) ;; For powers of two we can do srai/aze for divide and then adjust for @@ -2496,10 +2784,7 @@ (match_operand:GPR 2 "gpc_reg_operand" "r")))] "" "div %0,%1,%2" - [(set (attr "type") - (cond [(match_operand:SI 0 "" "") - (const_string "idiv")] - (const_string "ldiv")))]) + [(set_attr "type" "")]) (define_expand "mod3" [(use (match_operand:GPR 0 "gpc_reg_operand" "")) @@ -3698,20 +3983,33 @@ (const_int 0)))] "") -(define_insn "*rotlsi3_internal7" +(define_insn "*rotlsi3_internal7le" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] - "" + "!BYTES_BIG_ENDIAN" + "rlw%I2nm %0,%1,%h2,0xff" + [(set (attr "cell_micro") + (if_then_else (match_operand:SI 2 "const_int_operand" "") + (const_string "not") + (const_string "always")))]) + +(define_insn "*rotlsi3_internal7be" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (zero_extend:SI + (subreg:QI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))] + "BYTES_BIG_ENDIAN" "rlw%I2nm %0,%1,%h2,0xff" [(set (attr "cell_micro") (if_then_else (match_operand:SI 2 "const_int_operand" "") (const_string "not") (const_string "always")))]) -(define_insn "*rotlsi3_internal8" +(define_insn "*rotlsi3_internal8le" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:QI @@ -3719,7 +4017,24 @@ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" + "!BYTES_BIG_ENDIAN" + "@ + rlwnm. %3,%1,%2,0xff + rlwinm. %3,%1,%h2,0xff + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotlsi3_internal8be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:SI + (subreg:QI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) + (const_int 0))) + (clobber (match_scratch:SI 3 "=r,r,r,r"))] + "BYTES_BIG_ENDIAN" "@ rlwnm. %3,%1,%2,0xff rlwinm. %3,%1,%h2,0xff @@ -3736,7 +4051,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "reload_completed" + "!BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 3) (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) @@ -3746,7 +4061,25 @@ (const_int 0)))] "") -(define_insn "*rotlsi3_internal9" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:SI + (subreg:QI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")) 3)) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 3) + (zero_extend:SI (subreg:QI + (rotate:SI (match_dup 1) + (match_dup 2)) 3))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*rotlsi3_internal9le" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:QI @@ -3755,7 +4088,25 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] - "" + "!BYTES_BIG_ENDIAN" + "@ + rlwnm. %0,%1,%2,0xff + rlwinm. %0,%1,%h2,0xff + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotlsi3_internal9be" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:SI + (subreg:QI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))] + "BYTES_BIG_ENDIAN" "@ rlwnm. %0,%1,%2,0xff rlwinm. %0,%1,%h2,0xff @@ -3773,7 +4124,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] - "reload_completed" + "!BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 0) (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -3781,20 +4132,48 @@ (const_int 0)))] "") -(define_insn "*rotlsi3_internal10" +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:SI + (subreg:QI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")) 3)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))] + "BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 0) + (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*rotlsi3_internal10le" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))] - "" + "!BYTES_BIG_ENDIAN" "@ rlwnm %0,%1,%2,0xffff rlwinm %0,%1,%h2,0xffff" [(set_attr "type" "var_shift_rotate,integer")]) +(define_insn "*rotlsi3_internal10be" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (zero_extend:SI + (subreg:HI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))] + "BYTES_BIG_ENDIAN" + "@ + rlwnm %0,%1,%2,0xffff + rlwinm %0,%1,%h2,0xffff" + [(set_attr "type" "var_shift_rotate,integer")]) -(define_insn "*rotlsi3_internal11" +(define_insn "*rotlsi3_internal11le" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:HI @@ -3802,7 +4181,24 @@ (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] - "" + "!BYTES_BIG_ENDIAN" + "@ + rlwnm. %3,%1,%2,0xffff + rlwinm. %3,%1,%h2,0xffff + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotlsi3_internal11be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:SI + (subreg:HI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) + (const_int 0))) + (clobber (match_scratch:SI 3 "=r,r,r,r"))] + "BYTES_BIG_ENDIAN" "@ rlwnm. %3,%1,%2,0xffff rlwinm. %3,%1,%h2,0xffff @@ -3819,7 +4215,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "reload_completed" + "!BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 3) (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) @@ -3829,7 +4225,25 @@ (const_int 0)))] "") -(define_insn "*rotlsi3_internal12" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:SI + (subreg:HI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")) 2)) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 3) + (zero_extend:SI (subreg:HI + (rotate:SI (match_dup 1) + (match_dup 2)) 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*rotlsi3_internal12le" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:SI (subreg:HI @@ -3838,7 +4252,25 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] - "" + "!BYTES_BIG_ENDIAN" + "@ + rlwnm. %0,%1,%2,0xffff + rlwinm. %0,%1,%h2,0xffff + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotlsi3_internal12be" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:SI + (subreg:HI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))] + "BYTES_BIG_ENDIAN" "@ rlwnm. %0,%1,%2,0xffff rlwinm. %0,%1,%h2,0xffff @@ -3856,7 +4288,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] - "reload_completed" + "!BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 0) (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -3864,6 +4296,23 @@ (const_int 0)))] "") +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:SI + (subreg:HI + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_cint_operand" "")) 2)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))] + "BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 0) + (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + (define_insn "ashlsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") @@ -4054,7 +4503,7 @@ # # #" - [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,4,8,8,8")]) (define_split @@ -4086,7 +4535,7 @@ # # #" - [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") (set_attr "length" "4,4,4,8,8,8")]) (define_split @@ -4177,16 +4626,25 @@ (const_int 0)))] "") -(define_insn "" +(define_insn "*lshiftrt_internal1le" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] - "includes_rshift_p (operands[2], GEN_INT (255))" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" "rlwinm %0,%1,%s2,0xff") -(define_insn "" +(define_insn "*lshiftrt_internal1be" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (zero_extend:SI + (subreg:QI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) 3)))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" + "rlwinm %0,%1,%s2,0xff") + +(define_insn "*lshiftrt_internal2le" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI @@ -4195,7 +4653,23 @@ (match_operand:SI 2 "const_int_operand" "i,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "includes_rshift_p (operands[2], GEN_INT (255))" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" + "@ + rlwinm. %3,%1,%s2,0xff + #" + [(set_attr "type" "delayed_compare") + (set_attr "length" "4,8")]) + +(define_insn "*lshiftrt_internal2be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC + (zero_extend:SI + (subreg:QI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) 3)) + (const_int 0))) + (clobber (match_scratch:SI 3 "=r,r"))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" "@ rlwinm. %3,%1,%s2,0xff #" @@ -4211,7 +4685,7 @@ (match_operand:SI 2 "const_int_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" [(set (match_dup 3) (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) @@ -4221,7 +4695,26 @@ (const_int 0)))] "") -(define_insn "" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC + (zero_extend:SI + (subreg:QI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) 3)) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" + [(set (match_dup 3) + (zero_extend:SI (subreg:QI + (lshiftrt:SI (match_dup 1) + (match_dup 2)) 3))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*lshiftrt_internal3le" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI @@ -4231,7 +4724,24 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] - "includes_rshift_p (operands[2], GEN_INT (255))" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" + "@ + rlwinm. %0,%1,%s2,0xff + #" + [(set_attr "type" "delayed_compare") + (set_attr "length" "4,8")]) + +(define_insn "*lshiftrt_internal3be" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (zero_extend:SI + (subreg:QI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) 3)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" "@ rlwinm. %0,%1,%s2,0xff #" @@ -4248,7 +4758,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] - "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" [(set (match_dup 0) (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -4256,25 +4766,68 @@ (const_int 0)))] "") -(define_insn "" +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC + (zero_extend:SI + (subreg:QI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) 3)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" + [(set (match_dup 0) + (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*lshiftrt_internal4le" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] - "includes_rshift_p (operands[2], GEN_INT (65535))" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" "rlwinm %0,%1,%s2,0xffff") -(define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") - (compare:CC +(define_insn "*lshiftrt_internal4be" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "const_int_operand" "i")) 2)))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" + "rlwinm %0,%1,%s2,0xffff") + +(define_insn "*lshiftrt_internal5le" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC + (zero_extend:SI + (subreg:HI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "includes_rshift_p (operands[2], GEN_INT (65535))" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" + "@ + rlwinm. %3,%1,%s2,0xffff + #" + [(set_attr "type" "delayed_compare") + (set_attr "length" "4,8")]) + +(define_insn "*lshiftrt_internal5be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") + (compare:CC + (zero_extend:SI + (subreg:HI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) 2)) + (const_int 0))) + (clobber (match_scratch:SI 3 "=r,r"))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" "@ rlwinm. %3,%1,%s2,0xffff #" @@ -4290,7 +4843,7 @@ (match_operand:SI 2 "const_int_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" [(set (match_dup 3) (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) @@ -4300,7 +4853,26 @@ (const_int 0)))] "") -(define_insn "" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC + (zero_extend:SI + (subreg:HI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) 2)) + (const_int 0))) + (clobber (match_scratch:SI 3 ""))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" + [(set (match_dup 3) + (zero_extend:SI (subreg:HI + (lshiftrt:SI (match_dup 1) + (match_dup 2)) 2))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*lshiftrt_internal5le" [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") (compare:CC (zero_extend:SI @@ -4310,7 +4882,24 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] - "includes_rshift_p (operands[2], GEN_INT (65535))" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" + "@ + rlwinm. %0,%1,%s2,0xffff + #" + [(set_attr "type" "delayed_compare") + (set_attr "length" "4,8")]) + +(define_insn "*lshiftrt_internal5be" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") + (compare:CC + (zero_extend:SI + (subreg:HI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "i,i")) 2)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" "@ rlwinm. %0,%1,%s2,0xffff #" @@ -4327,7 +4916,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] - "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" + "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" [(set (match_dup 0) (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -4335,6 +4924,24 @@ (const_int 0)))] "") +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC + (zero_extend:SI + (subreg:HI + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "const_int_operand" "")) 2)) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))] + "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" + [(set (match_dup 0) + (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + (define_insn "ashrsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") @@ -4455,224 +5062,226 @@ (const_int 0)))] "") -;; Floating-point insns, excluding normal data motion. -;; -;; PowerPC has a full set of single-precision floating point instructions. -;; -;; For the POWER architecture, we pretend that we have both SFmode and -;; DFmode insns, while, in fact, all fp insns are actually done in double. -;; The only conversions we will do will be when storing to memory. In that -;; case, we will use the "frsp" instruction before storing. -;; -;; Note that when we store into a single-precision memory location, we need to -;; use the frsp insn first. If the register being stored isn't dead, we -;; need a scratch register for the frsp. But this is difficult when the store -;; is done by reload. It is not incorrect to do the frsp on the register in -;; this case, we just lose precision that we would have otherwise gotten but -;; is not guaranteed. Perhaps this should be tightened up at some point. -(define_expand "extendsfdf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") +;; Floating-point insns, excluding normal data motion. We combine the SF/DF +;; modes here, and also add in conditional vsx/power8-vector support to access +;; values in the traditional Altivec registers if the appropriate +;; -mupper-regs-{df,sf} option is enabled. -(define_insn_and_split "*extendsfdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d") - (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" - "@ - # - fmr %0,%1 - lfs%U1%X1 %0,%1" - "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" - [(const_int 0)] -{ - emit_note (NOTE_INSN_DELETED); - DONE; -} - [(set_attr "type" "fp,fp,fpload")]) - -(define_expand "truncdfsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") - -(define_insn "*truncdfsf2_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" - "frsp %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "negsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" - "") - -(define_insn "*negsf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fneg %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "abssf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "abs2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + "TARGET__INSN" "") -(define_insn "*abssf2" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fabs %0,%1" - [(set_attr "type" "fp")]) +(define_insn "*abs2_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + "TARGET__FPR" + "@ + fabs %0,%1 + xsabsdp %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fnabs %0,%1" - [(set_attr "type" "fp")]) +(define_insn "*nabs2_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (neg:SFDF + (abs:SFDF + (match_operand:SFDF 1 "gpc_reg_operand" ","))))] + "TARGET__FPR" + "@ + fnabs %0,%1 + xsnabsdp %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) -(define_expand "addsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "neg2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] + "TARGET__INSN" "") -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fadds %0,%1,%2" +(define_insn "*neg2_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + "TARGET__FPR" + "@ + fneg %0,%1 + xsnegdp %x0,%x1" [(set_attr "type" "fp") - (set_attr "fp_type" "fp_addsub_s")]) + (set_attr "fp_type" "fp_addsub_")]) -(define_expand "subsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "add3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")))] + "TARGET__INSN" "") -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fsubs %0,%1,%2" +(define_insn "*add3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR" + "@ + fadd %0,%1,%2 + xsadd %x0,%x1,%x2" [(set_attr "type" "fp") - (set_attr "fp_type" "fp_addsub_s")]) + (set_attr "fp_type" "fp_addsub_")]) -(define_expand "mulsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT" +(define_expand "sub3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")))] + "TARGET__INSN" "") -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fmuls %0,%1,%2" +(define_insn "*sub3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR" + "@ + fsub %0,%1,%2 + xssub %x0,%x1,%x2" [(set_attr "type" "fp") - (set_attr "fp_type" "fp_mul_s")]) + (set_attr "fp_type" "fp_addsub_")]) -(define_expand "divsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (div:SF (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" +(define_expand "mul3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")))] + "TARGET__INSN" "") -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS - && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" - "fdivs %0,%1,%2" - [(set_attr "type" "sdiv")]) - -(define_insn "fres" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] - "TARGET_FRES" - "fres %0,%1" +(define_insn "*mul3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR" + "@ + fmul %0,%1,%2 + xsmul %x0,%x1,%x2" + [(set_attr "type" "dmul") + (set_attr "fp_type" "fp_mul_")]) + +(define_expand "div3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")))] + "TARGET__INSN && !TARGET_SIMPLE_FPU" + "") + +(define_insn "*div3_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR && !TARGET_SIMPLE_FPU" + "@ + fdiv %0,%1,%2 + xsdiv %x0,%x1,%x2" + [(set_attr "type" "div") + (set_attr "fp_type" "fp_div_")]) + +(define_insn "sqrt2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ",")))] + "TARGET__FPR && !TARGET_SIMPLE_FPU + && (TARGET_PPC_GPOPT || (mode == SFmode && TARGET_XILINX_FPU))" + "@ + fsqrt %0,%1 + xssqrt %x0,%x1" + [(set_attr "type" "sqrt") + (set_attr "fp_type" "fp_sqrt_")]) + +;; Floating point reciprocal approximation +(define_insn "fre" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + UNSPEC_FRES))] + "TARGET_" + "@ + fre %0,%1 + xsre %x0,%x1" [(set_attr "type" "fp")]) -; builtin fmaf support -(define_insn "*fmasf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f") - (match_operand:SF 3 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fmadds %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +(define_insn "*rsqrt2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] + UNSPEC_RSQRT))] + "RS6000_RECIP_HAVE_RSQRTE_P (mode)" + "@ + frsqrte %0,%1 + xsrsqrte %x0,%x1" + [(set_attr "type" "fp")]) -(define_insn "*fmssf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f") - (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fmsubs %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +;; Floating point comparisons +(define_insn "*cmp_fpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") + (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR" + "@ + fcmpu %0,%1,%2 + xscmpudp %0,%x1,%x2" + [(set_attr "type" "fpcompare")]) -(define_insn "*nfmasf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f") - (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fnmadds %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +;; Floating point conversions +(define_expand "extendsfdf2" + [(set (match_operand:DF 0 "gpc_reg_operand" "") + (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] + "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" + "") -(define_insn "*nfmssf4_fpr" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f") - (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fnmsubs %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_s")]) +(define_insn_and_split "*extendsfdf2_fpr" + [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv") + (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "@ + # + fmr %0,%1 + lfs%U1%X1 %0,%1 + # + xxlor %x0,%x1,%x1 + lxsspx %x0,%y1" + "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" + [(const_int 0)] +{ + emit_note (NOTE_INSN_DELETED); + DONE; +} + [(set_attr_alternative "type" + [(const_string "fp") + (const_string "fp") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (const_string "fp") + (const_string "vecsimple") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload")))])]) -(define_expand "sqrtsf2" +(define_expand "truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") - (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] - "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT - && !TARGET_SIMPLE_FPU" + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" "") -(define_insn "" - [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT - && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU" - "fsqrts %0,%1" - [(set_attr "type" "ssqrt")]) - -(define_insn "*rsqrtsf_internal1" +(define_insn "*truncdfsf2_fpr" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] - UNSPEC_RSQRT))] - "TARGET_FRSQRTES" - "frsqrtes %0,%1" + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" + "frsp %0,%1" [(set_attr "type" "fp")]) ;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in @@ -4742,37 +5351,82 @@ ;; Use an unspec rather providing an if-then-else in RTL, to prevent the ;; compiler from optimizing -0.0 (define_insn "copysign3_fcpsgn" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "") - (match_operand:SFDF 2 "gpc_reg_operand" "")] + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",") + (match_operand:SFDF 2 "gpc_reg_operand" ",")] UNSPEC_COPYSIGN))] - "TARGET_CMPB && !VECTOR_UNIT_VSX_P (mode)" - "fcpsgn %0,%2,%1" + "TARGET__FPR && TARGET_CMPB" + "@ + fcpsgn %0,%2,%1 + xscpsgn %x0,%x2,%x1" [(set_attr "type" "fp")]) ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a ;; fsel instruction and some auxiliary computations. Then we just have a ;; single DEFINE_INSN for fsel and the define_splits to make them if made by ;; combine. -(define_expand "smaxsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")) +;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we +;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary +;; computations. Then we just have a single DEFINE_INSN for fsel and the +;; define_splits to make them if made by combine. On VSX machines we have the +;; min/max instructions. +;; +;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector +;; to allow either DF/SF to use only traditional registers. + +(define_expand "smax3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")) (match_dup 1) (match_dup 2)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS - && TARGET_SINGLE_FLOAT && !flag_trapping_math" - "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") + "TARGET__FPR && TARGET_PPC_GFXOPT && !flag_trapping_math" +{ + rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); + DONE; +}) -(define_expand "sminsf3" - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") - (match_operand:SF 2 "gpc_reg_operand" "")) +(define_insn "*smax3_vsx" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR && TARGET_VSX" + "xsmaxdp %x0,%x1,%x2" + [(set_attr "type" "fp")]) + +(define_expand "smin3" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")) (match_dup 2) (match_dup 1)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS - && TARGET_SINGLE_FLOAT && !flag_trapping_math" - "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") + "TARGET__FPR && TARGET_PPC_GFXOPT && !flag_trapping_math" +{ + rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); + DONE; +}) + +(define_insn "*smin3_vsx" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%,") + (match_operand:SFDF 2 "gpc_reg_operand" ",")))] + "TARGET__FPR && TARGET_VSX" + "xsmindp %x0,%x1,%x2" + [(set_attr "type" "fp")]) + +(define_split + [(set (match_operand:SFDF 0 "gpc_reg_operand" "") + (match_operator:SFDF 3 "min_max_operator" + [(match_operand:SFDF 1 "gpc_reg_operand" "") + (match_operand:SFDF 2 "gpc_reg_operand" "")]))] + "TARGET__FPR && TARGET_PPC_GFXOPT && !flag_trapping_math + && !TARGET_VSX" + [(const_int 0)] +{ + rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1], + operands[2]); + DONE; +}) (define_split [(set (match_operand:SF 0 "gpc_reg_operand" "") @@ -4904,208 +5558,9 @@ "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) -(define_expand "negdf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") - -(define_insn "*negdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fneg %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "absdf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") - -(define_insn "*absdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fabs %0,%1" - [(set_attr "type" "fp")]) - -(define_insn "*nabsdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fnabs %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "adddf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") - (match_operand:DF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") - -(define_insn "*adddf3_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d") - (match_operand:DF 2 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fadd %0,%1,%2" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_addsub_d")]) - -(define_expand "subdf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") - (match_operand:DF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") - -(define_insn "*subdf3_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d") - (match_operand:DF 2 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fsub %0,%1,%2" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_addsub_d")]) - -(define_expand "muldf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") - (match_operand:DF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" - "") - -(define_insn "*muldf3_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d") - (match_operand:DF 2 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fmul %0,%1,%2" - [(set_attr "type" "dmul") - (set_attr "fp_type" "fp_mul_d")]) - -(define_expand "divdf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (div:DF (match_operand:DF 1 "gpc_reg_operand" "") - (match_operand:DF 2 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT - && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE) - && !TARGET_SIMPLE_FPU" - "") - -(define_insn "*divdf3_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (div:DF (match_operand:DF 1 "gpc_reg_operand" "d") - (match_operand:DF 2 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU - && !VECTOR_UNIT_VSX_P (DFmode)" - "fdiv %0,%1,%2" - [(set_attr "type" "ddiv")]) - -(define_insn "*fred_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=f") - (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] - "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)" - "fre %0,%1" - [(set_attr "type" "fp")]) - -(define_insn "*rsqrtdf_internal1" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] - UNSPEC_RSQRT))] - "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)" - "frsqrte %0,%1" - [(set_attr "type" "fp")]) - -; builtin fma support -(define_insn "*fmadf4_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=f") - (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f") - (match_operand:DF 2 "gpc_reg_operand" "f") - (match_operand:DF 3 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && VECTOR_UNIT_NONE_P (DFmode)" - "fmadd %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - -(define_insn "*fmsdf4_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=f") - (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f") - (match_operand:DF 2 "gpc_reg_operand" "f") - (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && VECTOR_UNIT_NONE_P (DFmode)" - "fmsub %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - -(define_insn "*nfmadf4_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=f") - (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f") - (match_operand:DF 2 "gpc_reg_operand" "f") - (match_operand:DF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && VECTOR_UNIT_NONE_P (DFmode)" - "fnmadd %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - -(define_insn "*nfmsdf4_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=f") - (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f") - (match_operand:DF 2 "gpc_reg_operand" "f") - (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && VECTOR_UNIT_NONE_P (DFmode)" - "fnmsub %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - -(define_expand "sqrtdf2" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" - "") - -(define_insn "*sqrtdf2_fpr" - [(set (match_operand:DF 0 "gpc_reg_operand" "=d") - (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))] - "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fsqrt %0,%1" - [(set_attr "type" "dsqrt")]) - ;; The conditional move instructions allow us to perform max and min ;; operations even when -(define_expand "smaxdf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") - (match_operand:DF 2 "gpc_reg_operand" "")) - (match_dup 1) - (match_dup 2)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !flag_trapping_math" - "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") - -(define_expand "smindf3" - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") - (match_operand:DF 2 "gpc_reg_operand" "")) - (match_dup 2) - (match_dup 1)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !flag_trapping_math" - "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") - (define_split [(set (match_operand:DF 0 "gpc_reg_operand" "") (match_operator:DF 3 "min_max_operator" @@ -5159,12 +5614,15 @@ ; We don't define lfiwax/lfiwzx with the normal definition, because we ; don't want to support putting SImode in FPR registers. (define_insn "lfiwax" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") - (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") + (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] UNSPEC_LFIWAX))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" - "lfiwax %0,%y1" - [(set_attr "type" "fpload")]) + "@ + lfiwax %0,%y1 + lxsiwax %x0,%y1 + mtvsrwa %x0,%1" + [(set_attr "type" "fpload,fpload,mffgpr")]) ; This split must be run before register allocation because it allocates the ; memory slot that is needed to move values to/from the FPR. We don't allocate @@ -5186,7 +5644,8 @@ rtx src = operands[1]; rtx tmp; - if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64) + if (!MEM_P (src) && TARGET_POWERPC64 + && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) tmp = convert_to_mode (DImode, src, false); else { @@ -5235,12 +5694,15 @@ (set_attr "type" "fpload")]) (define_insn "lfiwzx" - [(set (match_operand:DI 0 "gpc_reg_operand" "=d") - (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")] + [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wm,!wm") + (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] UNSPEC_LFIWZX))] "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX" - "lfiwzx %0,%y1" - [(set_attr "type" "fpload")]) + "@ + lfiwzx %0,%y1 + lxsiwzx %x0,%y1 + mtvsrwz %x0,%1" + [(set_attr "type" "fpload,fpload,mftgpr")]) (define_insn_and_split "floatunssi2_lfiwzx" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") @@ -5257,7 +5719,8 @@ rtx src = operands[1]; rtx tmp; - if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64) + if (!MEM_P (src) && TARGET_POWERPC64 + && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) tmp = convert_to_mode (DImode, src, true); else { @@ -5548,7 +6011,7 @@ emit_insn (gen_stfiwx (dest, tmp)); DONE; } - else if (TARGET_MFPGPR && TARGET_POWERPC64) + else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) { dest = gen_lowpart (DImode, dest); emit_move_insn (dest, tmp); @@ -5642,7 +6105,7 @@ emit_insn (gen_stfiwx (dest, tmp)); DONE; } - else if (TARGET_MFPGPR && TARGET_POWERPC64) + else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) { dest = gen_lowpart (DImode, dest); emit_move_insn (dest, tmp); @@ -5781,66 +6244,52 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=d") (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FCTID))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && " + "TARGET__FPR && TARGET_FPRND" "fctid %0,%1" [(set_attr "type" "fp")]) -(define_expand "btrunc2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] - UNSPEC_FRIZ))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && " - "") - -(define_insn "*btrunc2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] +(define_insn "btrunc2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRIZ))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && - && !VECTOR_UNIT_VSX_P (mode)" - "friz %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "ceil2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] - UNSPEC_FRIP))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && " - "") + "TARGET__FPR && TARGET_FPRND" + "@ + friz %0,%1 + xsrdpiz %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) -(define_insn "*ceil2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] +(define_insn "ceil2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRIP))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && - && !VECTOR_UNIT_VSX_P (mode)" - "frip %0,%1" - [(set_attr "type" "fp")]) - -(define_expand "floor2" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] - UNSPEC_FRIM))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && " - "") + "TARGET__FPR && TARGET_FPRND" + "@ + frip %0,%1 + xsrdpip %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) -(define_insn "*floor2_fpr" - [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") - (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] +(define_insn "floor2" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,") + (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" ",")] UNSPEC_FRIM))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && - && !VECTOR_UNIT_VSX_P (mode)" - "frim %0,%1" - [(set_attr "type" "fp")]) + "TARGET__FPR && TARGET_FPRND" + "@ + frim %0,%1 + xsrdpim %x0,%x1" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) ;; No VSX equivalent to frin (define_insn "round2" [(set (match_operand:SFDF 0 "gpc_reg_operand" "=") (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")] UNSPEC_FRIN))] - "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && " + "TARGET__FPR && TARGET_FPRND" "frin %0,%1" - [(set_attr "type" "fp")]) + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_addsub_")]) ; An UNSPEC is used so we don't have to support SImode in FP registers. (define_insn "stfiwx" @@ -6084,6 +6533,49 @@ [(set_attr "length" "8") (set_attr "type" "fpload")]) +;; Define the TImode operations that can be done in a small number +;; of instructions. The & constraints are to prevent the register +;; allocator from allocating registers that overlap with the inputs +;; (for example, having an input in 7,8 and an output in 6,7). We +;; also allow for the output being the same as one of the inputs. + +(define_insn "addti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") + (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") + (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] + "TARGET_64BIT" +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[2])) != CONST_INT + ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" + : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; + else + return (GET_CODE (operands[2])) != CONST_INT + ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" + : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + +(define_insn "subti3" + [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r") + (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I") + (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))] + "TARGET_64BIT" +{ + if (WORDS_BIG_ENDIAN) + return (GET_CODE (operands[1]) != CONST_INT) + ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" + : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; + else + return (GET_CODE (operands[1]) != CONST_INT) + ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" + : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; +} + [(set_attr "type" "two") + (set_attr "length" "8")]) + + ;; Define the DImode operations that can be done in a small number ;; of instructions. The & constraints are to prevent the register ;; allocator from allocating registers that overlap with the inputs @@ -6260,11 +6752,11 @@ [(set_attr "type" "two,three") (set_attr "length" "8,12")]) -(define_insn "*ashrdisi3_noppc64" +(define_insn "*ashrdisi3_noppc64be" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") (const_int 32)) 4))] - "TARGET_32BIT && !TARGET_POWERPC64" + "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN" "* { if (REGNO (operands[0]) == REGNO (operands[1])) @@ -6551,19 +7043,31 @@ (const_int 0)))] "") -(define_insn "*rotldi3_internal7" +(define_insn "*rotldi3_internal7le" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" + "@ + rldcl %0,%1,%2,56 + rldicl %0,%1,%H2,56" + [(set_attr "type" "var_shift_rotate,integer")]) + +(define_insn "*rotldi3_internal7be" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (zero_extend:DI + (subreg:QI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" "@ rldcl %0,%1,%2,56 rldicl %0,%1,%H2,56" [(set_attr "type" "var_shift_rotate,integer")]) -(define_insn "*rotldi3_internal8" +(define_insn "*rotldi3_internal8le" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:QI @@ -6571,7 +7075,24 @@ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" + "TARGET_64BIT && !BYTES_BIG_ENDIAN" + "@ + rldcl. %3,%1,%2,56 + rldicl. %3,%1,%H2,56 + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotldi3_internal8be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:DI + (subreg:QI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) + (const_int 0))) + (clobber (match_scratch:DI 3 "=r,r,r,r"))] + "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ rldcl. %3,%1,%2,56 rldicl. %3,%1,%H2,56 @@ -6588,7 +7109,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 3) (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) @@ -6598,7 +7119,25 @@ (const_int 0)))] "") -(define_insn "*rotldi3_internal9" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:DI + (subreg:QI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "reg_or_cint_operand" "")) 7)) + (const_int 0))) + (clobber (match_scratch:DI 3 ""))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 3) + (zero_extend:DI (subreg:QI + (rotate:DI (match_dup 1) + (match_dup 2)) 7))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*rotldi3_internal9le" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:QI @@ -6607,7 +7146,25 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] - "TARGET_64BIT" + "TARGET_64BIT && !BYTES_BIG_ENDIAN" + "@ + rldcl. %0,%1,%2,56 + rldicl. %0,%1,%H2,56 + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotldi3_internal9be" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:DI + (subreg:QI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))] + "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ rldcl. %0,%1,%2,56 rldicl. %0,%1,%H2,56 @@ -6625,7 +7182,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] - "TARGET_POWERPC64 && reload_completed" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 0) (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -6633,19 +7190,48 @@ (const_int 0)))] "") -(define_insn "*rotldi3_internal10" +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:DI + (subreg:QI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "reg_or_cint_operand" "")) 7)) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "") + (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 0) + (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*rotldi3_internal10le" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" + "@ + rldcl %0,%1,%2,48 + rldicl %0,%1,%H2,48" + [(set_attr "type" "var_shift_rotate,integer")]) + +(define_insn "*rotldi3_internal10be" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (zero_extend:DI + (subreg:HI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" "@ rldcl %0,%1,%2,48 rldicl %0,%1,%H2,48" [(set_attr "type" "var_shift_rotate,integer")]) -(define_insn "*rotldi3_internal11" +(define_insn "*rotldi3_internal11le" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:HI @@ -6653,7 +7239,24 @@ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" + "TARGET_64BIT && !BYTES_BIG_ENDIAN" + "@ + rldcl. %3,%1,%2,48 + rldicl. %3,%1,%H2,48 + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotldi3_internal11be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:DI + (subreg:HI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) + (const_int 0))) + (clobber (match_scratch:DI 3 "=r,r,r,r"))] + "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ rldcl. %3,%1,%2,48 rldicl. %3,%1,%H2,48 @@ -6670,7 +7273,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 3) (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) @@ -6680,7 +7283,25 @@ (const_int 0)))] "") -(define_insn "*rotldi3_internal12" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:DI + (subreg:HI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "reg_or_cint_operand" "")) 6)) + (const_int 0))) + (clobber (match_scratch:DI 3 ""))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 3) + (zero_extend:DI (subreg:HI + (rotate:DI (match_dup 1) + (match_dup 2)) 6))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*rotldi3_internal12le" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:HI @@ -6689,7 +7310,25 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] - "TARGET_64BIT" + "TARGET_64BIT && !BYTES_BIG_ENDIAN" + "@ + rldcl. %0,%1,%2,48 + rldicl. %0,%1,%H2,48 + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotldi3_internal12be" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:DI + (subreg:HI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))] + "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ rldcl. %0,%1,%2,48 rldicl. %0,%1,%H2,48 @@ -6707,7 +7346,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] - "TARGET_POWERPC64 && reload_completed" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 0) (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -6715,19 +7354,48 @@ (const_int 0)))] "") -(define_insn "*rotldi3_internal13" +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:DI + (subreg:HI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "reg_or_cint_operand" "")) 6)) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "") + (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 0) + (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +(define_insn "*rotldi3_internal13le" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (zero_extend:DI (subreg:SI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] - "TARGET_POWERPC64" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" "@ rldcl %0,%1,%2,32 rldicl %0,%1,%H2,32" [(set_attr "type" "var_shift_rotate,integer")]) -(define_insn "*rotldi3_internal14" +(define_insn "*rotldi3_internal13be" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (zero_extend:DI + (subreg:SI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" + "@ + rldcl %0,%1,%2,32 + rldicl %0,%1,%H2,32" + [(set_attr "type" "var_shift_rotate,integer")]) + +(define_insn "*rotldi3_internal14le" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:SI @@ -6735,7 +7403,24 @@ (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 "=r,r,r,r"))] - "TARGET_64BIT" + "TARGET_64BIT && !BYTES_BIG_ENDIAN" + "@ + rldcl. %3,%1,%2,32 + rldicl. %3,%1,%H2,32 + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotldi3_internal14be" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:DI + (subreg:SI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) + (const_int 0))) + (clobber (match_scratch:DI 3 "=r,r,r,r"))] + "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ rldcl. %3,%1,%2,32 rldicl. %3,%1,%H2,32 @@ -6752,7 +7437,7 @@ (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) (const_int 0))) (clobber (match_scratch:DI 3 ""))] - "TARGET_POWERPC64 && reload_completed" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 3) (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) @@ -6762,16 +7447,52 @@ (const_int 0)))] "") -(define_insn "*rotldi3_internal15" +(define_split + [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:DI + (subreg:SI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "reg_or_cint_operand" "")) 4)) + (const_int 0))) + (clobber (match_scratch:DI 3 ""))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 3) + (zero_extend:DI (subreg:SI + (rotate:DI (match_dup 1) + (match_dup 2)) 4))) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*rotldi3_internal15le" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") + (compare:CC (zero_extend:DI + (subreg:SI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") + (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] + "TARGET_64BIT && !BYTES_BIG_ENDIAN" + "@ + rldcl. %0,%1,%2,32 + rldicl. %0,%1,%H2,32 + # + #" + [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") + (set_attr "length" "4,4,8,8")]) + +(define_insn "*rotldi3_internal15be" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") (compare:CC (zero_extend:DI (subreg:SI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") - (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) + (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] - "TARGET_64BIT" + (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))] + "TARGET_64BIT && BYTES_BIG_ENDIAN" "@ rldcl. %0,%1,%2,32 rldicl. %0,%1,%H2,32 @@ -6789,7 +7510,7 @@ (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "") (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] - "TARGET_POWERPC64 && reload_completed" + "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" [(set (match_dup 0) (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) (set (match_dup 3) @@ -6797,6 +7518,23 @@ (const_int 0)))] "") +(define_split + [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") + (compare:CC (zero_extend:DI + (subreg:SI + (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "reg_or_cint_operand" "")) 4)) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "") + (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))] + "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" + [(set (match_dup 0) + (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4))) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + (define_expand "ashldi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7195,10 +7933,19 @@ [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "") (and:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "and64_2_operand" ""))) + (match_operand:DI 2 "reg_or_cint_operand" ""))) (clobber (match_scratch:CC 3 ""))])] - "TARGET_POWERPC64" - "") + "" +{ + if (!TARGET_POWERPC64) + { + rtx cc = gen_rtx_SCRATCH (CCmode); + rs6000_split_logical (operands, AND, false, false, false, cc); + DONE; + } + else if (!and64_2_operand (operands[2], DImode)) + operands[2] = force_reg (DImode, operands[2]); +}) (define_insn "anddi3_mc" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") @@ -7379,11 +8126,17 @@ (define_expand "iordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] - "TARGET_POWERPC64" - " + (match_operand:DI 2 "reg_or_cint_operand" "")))] + "" { - if (non_logical_cint_operand (operands[2], DImode)) + if (!TARGET_POWERPC64) + { + rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX); + DONE; + } + else if (!reg_or_logical_cint_operand (operands[2], DImode)) + operands[2] = force_reg (DImode, operands[2]); + else if (non_logical_cint_operand (operands[2], DImode)) { HOST_WIDE_INT value; rtx tmp = ((!can_create_pseudo_p () @@ -7408,15 +8161,21 @@ emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } -}") +}) (define_expand "xordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") - (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] - "TARGET_POWERPC64" - " + (match_operand:DI 2 "reg_or_cint_operand" "")))] + "" { + if (!TARGET_POWERPC64) + { + rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX); + DONE; + } + else if (!reg_or_logical_cint_operand (operands[2], DImode)) + operands[2] = force_reg (DImode, operands[2]); if (non_logical_cint_operand (operands[2], DImode)) { HOST_WIDE_INT value; @@ -7442,7 +8201,7 @@ emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; } -}") +}) (define_insn "*booldi3_internal1" [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") @@ -7678,6 +8437,384 @@ (compare:CC (match_dup 0) (const_int 0)))] "") + +;; Eqv operation. +(define_insn "*eqv3" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (not:GPR + (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r"))))] + "" + "eqv %0,%1,%2" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + + +;; 128-bit logical operations expanders + +(define_expand "and3" + [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 + (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" ""))) + (clobber (match_scratch:CC 3 ""))])] + "" + "") + +(define_expand "ior3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" "")))] + "" + "") + +(define_expand "xor3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" "")))] + "" + "") + +(define_expand "one_cmpl2" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))] + "" + "") + +(define_expand "nor3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + "" + "") + +(define_expand "andc3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (and:BOOL_128 + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) + (match_operand:BOOL_128 1 "vlogical_operand" "")))] + "" + "") + +;; Power8 vector logical instructions. +(define_expand "eqv3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (not:BOOL_128 + (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + "mode == TImode || mode == PTImode || TARGET_P8_VECTOR" + "") + +;; Rewrite nand into canonical form +(define_expand "nand3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (ior:BOOL_128 + (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + "mode == TImode || mode == PTImode || TARGET_P8_VECTOR" + "") + +;; The canonical form is to have the negated element first, so we need to +;; reverse arguments. +(define_expand "orc3" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "") + (ior:BOOL_128 + (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) + (match_operand:BOOL_128 1 "vlogical_operand" "")))] + "mode == TImode || mode == PTImode || TARGET_P8_VECTOR" + "") + +;; 128-bit logical operations insns and split operations +(define_insn_and_split "*and3_internal" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") + (and:BOOL_128 + (match_operand:BOOL_128 1 "vlogical_operand" "%") + (match_operand:BOOL_128 2 "vlogical_operand" ""))) + (clobber (match_scratch:CC 3 ""))] + "" +{ + if (TARGET_VSX && vsx_register_operand (operands[0], mode)) + return "xxland %x0,%x1,%x2"; + + if (TARGET_ALTIVEC && altivec_register_operand (operands[0], mode)) + return "vand %0,%1,%2"; + + return "#"; +} + "reload_completed && int_reg_operand (operands[0], mode)" + [(const_int 0)] +{ + rs6000_split_logical (operands, AND, false, false, false, operands[3]); + DONE; +} + [(set (attr "type") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "vecsimple") + (const_string "integer"))) + (set (attr "length") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "4") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))))]) + +;; 128-bit IOR/XOR +(define_insn_and_split "*bool3_internal" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") + (match_operator:BOOL_128 3 "boolean_or_operator" + [(match_operand:BOOL_128 1 "vlogical_operand" "%") + (match_operand:BOOL_128 2 "vlogical_operand" "")]))] + "" +{ + if (TARGET_VSX && vsx_register_operand (operands[0], mode)) + return "xxl%q3 %x0,%x1,%x2"; + + if (TARGET_ALTIVEC && altivec_register_operand (operands[0], mode)) + return "v%q3 %0,%1,%2"; + + return "#"; +} + "reload_completed && int_reg_operand (operands[0], mode)" + [(const_int 0)] +{ + rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false, + NULL_RTX); + DONE; +} + [(set (attr "type") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "vecsimple") + (const_string "integer"))) + (set (attr "length") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "4") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))))]) + +;; 128-bit ANDC/ORC +(define_insn_and_split "*boolc3_internal1" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") + (match_operator:BOOL_128 3 "boolean_operator" + [(not:BOOL_128 + (match_operand:BOOL_128 2 "vlogical_operand" "")) + (match_operand:BOOL_128 1 "vlogical_operand" "")]))] + "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)" +{ + if (TARGET_VSX && vsx_register_operand (operands[0], mode)) + return "xxl%q3 %x0,%x1,%x2"; + + if (TARGET_ALTIVEC && altivec_register_operand (operands[0], mode)) + return "v%q3 %0,%1,%2"; + + return "#"; +} + "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)) + && reload_completed && int_reg_operand (operands[0], mode)" + [(const_int 0)] +{ + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false, + NULL_RTX); + DONE; +} + [(set (attr "type") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "vecsimple") + (const_string "integer"))) + (set (attr "length") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "4") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))))]) + +(define_insn_and_split "*boolc3_internal2" + [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") + (match_operator:TI2 3 "boolean_operator" + [(not:TI2 + (match_operand:TI2 1 "int_reg_operand" "r,0,r")) + (match_operand:TI2 2 "int_reg_operand" "r,r,0")]))] + "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" + "#" + "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" + [(const_int 0)] +{ + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, false, + NULL_RTX); + DONE; +} + [(set_attr "type" "integer") + (set (attr "length") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")))]) + +;; 128-bit NAND/NOR +(define_insn_and_split "*boolcc3_internal1" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") + (match_operator:BOOL_128 3 "boolean_operator" + [(not:BOOL_128 + (match_operand:BOOL_128 1 "vlogical_operand" "")) + (not:BOOL_128 + (match_operand:BOOL_128 2 "vlogical_operand" ""))]))] + "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)" +{ + if (TARGET_VSX && vsx_register_operand (operands[0], mode)) + return "xxl%q3 %x0,%x1,%x2"; + + if (TARGET_ALTIVEC && altivec_register_operand (operands[0], mode)) + return "v%q3 %0,%1,%2"; + + return "#"; +} + "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)) + && reload_completed && int_reg_operand (operands[0], mode)" + [(const_int 0)] +{ + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true, + NULL_RTX); + DONE; +} + [(set (attr "type") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "vecsimple") + (const_string "integer"))) + (set (attr "length") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "4") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))))]) + +(define_insn_and_split "*boolcc3_internal2" + [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") + (match_operator:TI2 3 "boolean_operator" + [(not:TI2 + (match_operand:TI2 1 "int_reg_operand" "r,0,r")) + (not:TI2 + (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))] + "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" + "#" + "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" + [(const_int 0)] +{ + rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true, + NULL_RTX); + DONE; +} + [(set_attr "type" "integer") + (set (attr "length") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")))]) + + +;; 128-bit EQV +(define_insn_and_split "*eqv3_internal1" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") + (not:BOOL_128 + (xor:BOOL_128 + (match_operand:BOOL_128 1 "vlogical_operand" "") + (match_operand:BOOL_128 2 "vlogical_operand" ""))))] + "TARGET_P8_VECTOR" +{ + if (vsx_register_operand (operands[0], mode)) + return "xxleqv %x0,%x1,%x2"; + + return "#"; +} + "TARGET_P8_VECTOR && reload_completed + && int_reg_operand (operands[0], mode)" + [(const_int 0)] +{ + rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX); + DONE; +} + [(set (attr "type") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "vecsimple") + (const_string "integer"))) + (set (attr "length") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "4") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))))]) + +(define_insn_and_split "*eqv3_internal2" + [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") + (not:TI2 + (xor:TI2 + (match_operand:TI2 1 "int_reg_operand" "r,0,r") + (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))] + "!TARGET_P8_VECTOR" + "#" + "reload_completed && !TARGET_P8_VECTOR" + [(const_int 0)] +{ + rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX); + DONE; +} + [(set_attr "type" "integer") + (set (attr "length") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16")))]) + +;; 128-bit one's complement +(define_insn_and_split "*one_cmpl3_internal" + [(set (match_operand:BOOL_128 0 "vlogical_operand" "=") + (not:BOOL_128 + (match_operand:BOOL_128 1 "vlogical_operand" "")))] + "" +{ + if (TARGET_VSX && vsx_register_operand (operands[0], mode)) + return "xxlnor %x0,%x1,%x1"; + + if (TARGET_ALTIVEC && altivec_register_operand (operands[0], mode)) + return "vnor %0,%1,%1"; + + return "#"; +} + "reload_completed && int_reg_operand (operands[0], mode)" + [(const_int 0)] +{ + rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX); + DONE; +} + [(set (attr "type") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "vecsimple") + (const_string "integer"))) + (set (attr "length") + (if_then_else + (match_test "vsx_register_operand (operands[0], mode)") + (const_string "4") + (if_then_else + (match_test "TARGET_POWERPC64") + (const_string "8") + (const_string "16"))))]) + ;; Now define ways of moving data around. @@ -7765,7 +8902,31 @@ mt%0 %1 mt%0 %1 nop" - [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*") + [(set_attr_alternative "type" + [(const_string "*") + (const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "mfjmpr") + (const_string "mtjmpr") + (const_string "*") + (const_string "*")]) + (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")]) (define_insn "*movsi_internal1_single" @@ -7787,7 +8948,44 @@ nop stfs%U0%X0 %1,%0 lfs%U1%X1 %0,%1" - [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,mtjmpr,*,*,*,*") + [(set_attr_alternative "type" + [(const_string "*") + (const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "mfjmpr") + (const_string "mtjmpr") + (const_string "*") + (const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload")))]) (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) ;; Split a load of a large constant into the appropriate two-insn @@ -7822,7 +9020,7 @@ cmpi %2,%0,0 mr. %0,%1 #" - [(set_attr "type" "cmp,compare,cmp") + [(set_attr "type" "cmp,fast_compare,cmp") (set_attr "length" "4,4,8")]) (define_split @@ -7850,7 +9048,26 @@ mf%1 %0 mt%0 %1 nop" - [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")]) + [(set_attr_alternative "type" + [(const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (const_string "*") + (const_string "mfjmpr") + (const_string "mtjmpr") + (const_string "*")])]) (define_expand "mov" [(set (match_operand:INT 0 "general_operand" "") @@ -7871,7 +9088,26 @@ mf%1 %0 mt%0 %1 nop" - [(set_attr "type" "*,load,store,*,mfjmpr,mtjmpr,*")]) + [(set_attr_alternative "type" + [(const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (const_string "*") + (const_string "mfjmpr") + (const_string "mtjmpr") + (const_string "*")])]) ;; Here is how to move condition codes around. When we store CC data in ;; an integer register or memory, we store just the high-order 4 bits. @@ -7899,7 +9135,7 @@ mf%1 %0 mt%0 %1 lwz%U1%X1 %0,%1 - stw%U0%U1 %1,%0" + stw%U0%X0 %1,%0" [(set (attr "type") (cond [(eq_attr "alternative" "0,3") (const_string "cr_logical") @@ -7912,9 +9148,23 @@ (eq_attr "alternative" "9") (const_string "mtjmpr") (eq_attr "alternative" "10") - (const_string "load") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], + VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) (eq_attr "alternative" "11") - (const_string "store") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], + VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) (match_test "TARGET_MFCRF") (const_string "mfcrf") ] @@ -7926,15 +9176,17 @@ ;; can produce floating-point values in fixed-point registers. Unless the ;; value is a simple constant or already in memory, we deal with this by ;; allocating memory and copying the value explicitly via that memory location. -(define_expand "movsf" - [(set (match_operand:SF 0 "nonimmediate_operand" "") - (match_operand:SF 1 "any_operand" ""))] - "" - "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") + +;; Move 32-bit binary/decimal floating point +(define_expand "mov" + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "") + (match_operand:FMOVE32 1 "any_operand" ""))] + "" + "{ rs6000_emit_move (operands[0], operands[1], mode); DONE; }") (define_split - [(set (match_operand:SF 0 "gpc_reg_operand" "") - (match_operand:SF 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "") + (match_operand:FMOVE32 1 "const_double_operand" ""))] "reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -7947,42 +9199,89 @@ REAL_VALUE_TYPE rv; REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_SINGLE (rv, l); + (rv, l); if (! TARGET_POWERPC64) - operands[2] = operand_subword (operands[0], 0, 0, SFmode); + operands[2] = operand_subword (operands[0], 0, 0, mode); else operands[2] = gen_lowpart (SImode, operands[0]); operands[3] = gen_int_mode (l, SImode); }") -(define_insn "*movsf_hardfloat" - [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,!r,*h,!r,!r") - (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,h,0,G,Fn"))] - "(gpc_reg_operand (operands[0], SFmode) - || gpc_reg_operand (operands[1], SFmode)) +(define_insn "mov_hardfloat" + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,wa,wa,,,wu,Z,?,?r,*c*l,!r,*h,!r,!r") + (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,wa,j,,,Z,wu,r,,r,h,0,G,Fn"))] + "(gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode)) && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" "@ mr %0,%1 lwz%U1%X1 %0,%1 stw%U0%X0 %1,%0 fmr %0,%1 - lfs%U1%X1 %0,%1 - stfs%U0%X0 %1,%0 + xxlor %x0,%x1,%x1 + xxlxor %x0,%x0,%x0 + + + + + mtvsrwz %x0,%1 + mfvsrwz %0,%x1 mt%0 %1 mf%1 %0 nop # #" - [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) - -(define_insn "*movsf_softfloat" - [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h") - (match_operand:SF 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))] - "(gpc_reg_operand (operands[0], SFmode) - || gpc_reg_operand (operands[1], SFmode)) + [(set_attr_alternative "type" + [(const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (const_string "fp") + (const_string "vecsimple") + (const_string "vecsimple") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (const_string "fpload") + (const_string "fpstore") + (const_string "mftgpr") + (const_string "mffgpr") + (const_string "mtjmpr") + (const_string "mfjmpr") + (const_string "*") + (const_string "*") + (const_string "*")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")]) + +(define_insn "*mov_softfloat" + [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h") + (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))] + "(gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode)) && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" "@ mr %0,%1 @@ -7995,19 +9294,42 @@ # # nop" - [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*") + [(set_attr_alternative "type" + [(const_string "*") + (const_string "mtjmpr") + (const_string "mfjmpr") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "*")]) (set_attr "length" "4,4,4,4,4,4,4,4,8,4")]) -(define_expand "movdf" - [(set (match_operand:DF 0 "nonimmediate_operand" "") - (match_operand:DF 1 "any_operand" ""))] +;; Move 64-bit binary/decimal floating point +(define_expand "mov" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "") + (match_operand:FMOVE64 1 "any_operand" ""))] "" - "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") + "{ rs6000_emit_move (operands[0], operands[1], mode); DONE; }") (define_split - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "const_int_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") + (match_operand:FMOVE64 1 "const_int_operand" ""))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -8020,8 +9342,8 @@ int endian = (WORDS_BIG_ENDIAN == 0); HOST_WIDE_INT value = INTVAL (operands[1]); - operands[2] = operand_subword (operands[0], endian, 0, DFmode); - operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); + operands[2] = operand_subword (operands[0], endian, 0, mode); + operands[3] = operand_subword (operands[0], 1 - endian, 0, mode); #if HOST_BITS_PER_WIDE_INT == 32 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; #else @@ -8031,8 +9353,8 @@ }") (define_split - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") + (match_operand:FMOVE64 1 "const_double_operand" ""))] "! TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -8047,17 +9369,17 @@ REAL_VALUE_TYPE rv; REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DOUBLE (rv, l); + (rv, l); - operands[2] = operand_subword (operands[0], endian, 0, DFmode); - operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); + operands[2] = operand_subword (operands[0], endian, 0, mode); + operands[3] = operand_subword (operands[0], 1 - endian, 0, mode); operands[4] = gen_int_mode (l[endian], SImode); operands[5] = gen_int_mode (l[1 - endian], SImode); }") (define_split - [(set (match_operand:DF 0 "gpc_reg_operand" "") - (match_operand:DF 1 "const_double_operand" ""))] + [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") + (match_operand:FMOVE64 1 "const_double_operand" ""))] "TARGET_POWERPC64 && reload_completed && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) || (GET_CODE (operands[0]) == SUBREG @@ -8074,7 +9396,7 @@ #endif REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); - REAL_VALUE_TO_TARGET_DOUBLE (rv, l); + (rv, l); operands[2] = gen_lowpart (DImode, operands[0]); /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ @@ -8099,22 +9421,19 @@ ;; since the D-form version of the memory instructions does not need a GPR for ;; reloading. -(define_insn "*movdf_hardfloat32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,ws,?wa,Z,?Z,ws,?wa,wa,Y,r,!r,!r,!r,!r") - (match_operand:DF 1 "input_operand" "d,m,d,Z,Z,ws,wa,ws,wa,j,r,Y,r,G,H,F"))] +(define_insn "*mov_hardfloat32" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,!r,!r,!r") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,G,H,F"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 lxsd%U1x %x0,%y1 - lxsd%U1x %x0,%y1 - stxsd%U0x %x1,%y0 stxsd%U0x %x1,%y0 xxlor %x0,%x1,%x1 - xxlor %x0,%x1,%x1 xxlxor %x0,%x0,%x0 # # @@ -8122,115 +9441,141 @@ # # #" - [(set_attr "type" "fpstore,fpload,fp,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,store,load,two,fp,fp,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,8,8,8,12,16")]) - -(define_insn "*movdf_softfloat32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r") - (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))] + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (const_string "fp") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload")) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (const_string "fpstore")) + (const_string "vecsimple") + (const_string "vecsimple") + (const_string "store") + (const_string "load") + (const_string "two") + (const_string "fp") + (const_string "fp") + (const_string "*")]) + (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")]) + +(define_insn "*mov_softfloat32" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") + (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] "! TARGET_POWERPC64 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) - || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" + || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE + || (mode == DDmode && TARGET_E500_DOUBLE)) + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "#" [(set_attr "type" "store,load,two,*,*,*") (set_attr "length" "8,8,8,8,12,16")]) -;; Reload patterns to support gpr load/store with misaligned mem. -;; and multiple gpr load/store at offset >= 0xfffc -(define_expand "reload__store" - [(parallel [(match_operand 0 "memory_operand" "=m") - (match_operand 1 "gpc_reg_operand" "r") - (match_operand:GPR 2 "register_operand" "=&b")])] - "" -{ - rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true); - DONE; -}) - -(define_expand "reload__load" - [(parallel [(match_operand 0 "gpc_reg_operand" "=r") - (match_operand 1 "memory_operand" "m") - (match_operand:GPR 2 "register_operand" "=b")])] - "" -{ - rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false); - DONE; -}) - -; ld/std require word-aligned displacements -> 'Y' constraint. -; List Y->r and r->Y before r->r for reload. -(define_insn "*movdf_hardfloat64_mfpgpr" - [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d") - (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))] - "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && TARGET_DOUBLE_FLOAT - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - xxlor %x0,%x1,%x1 - xxlor %x0,%x1,%x1 - lxsd%U1x %x0,%y1 - lxsd%U1x %x0,%y1 - stxsd%U0x %x1,%y0 - stxsd%U0x %x1,%y0 - stfd%U0%X0 %1,%0 - lfd%U1%X1 %0,%1 - fmr %0,%1 - xxlxor %x0,%x0,%x0 - mt%0 %1 - mf%1 %0 - nop - # - # - # - mftgpr %0,%1 - mffgpr %0,%1" - [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")]) - ; ld/std require word-aligned displacements -> 'Y' constraint. ; List Y->r and r->Y before r->r for reload. -(define_insn "*movdf_hardfloat64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=m,d,d,Y,r,!r,ws,?wa,Z,?Z,ws,?wa,wa,*c*l,!r,*h,!r,!r,!r") - (match_operand:DF 1 "input_operand" "d,m,d,r,Y,r,Z,Z,ws,wa,ws,wa,j,r,h,0,G,H,F"))] - "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && TARGET_DOUBLE_FLOAT - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" +(define_insn "*mov_hardfloat64" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,wv,Z,wa,wa,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,wm") + (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,wv,wa,j,r,Y,r,r,h,0,G,H,F,wg,r,wm,r"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - lxsd%U1x %x0,%y1 lxsd%U1x %x0,%y1 stxsd%U0x %x1,%y0 - stxsd%U0x %x1,%y0 - xxlor %x0,%x1,%x1 xxlor %x0,%x1,%x1 xxlxor %x0,%x0,%x0 + std%U0%X0 %1,%0 + ld%U1%X1 %0,%1 + mr %0,%1 mt%0 %1 mf%1 %0 nop # # - #" - [(set_attr "type" "fpstore,fpload,fp,store,load,*,fpload,fpload,fpstore,fpstore,vecsimple,vecsimple,vecsimple,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")]) - -(define_insn "*movdf_softfloat64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") - (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] + # + mftgpr %0,%1 + mffgpr %0,%1 + mfvsrd %0,%x1 + mtvsrd %x0,%1" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (const_string "fp") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload")) + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (const_string "fpstore")) + (const_string "vecsimple") + (const_string "vecsimple") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*") + (const_string "mtjmpr") + (const_string "mfjmpr") + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "mftgpr") + (const_string "mffgpr") + (const_string "mftgpr") + (const_string "mffgpr")]) + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")]) + +(define_insn "*mov_softfloat64" + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") + (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) - && (gpc_reg_operand (operands[0], DFmode) - || gpc_reg_operand (operands[1], DFmode))" + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "@ std%U0%X0 %1,%0 ld%U1%X1 %0,%1 @@ -8241,38 +9586,87 @@ # # nop" - [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*") + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*") + (const_string "mtjmpr") + (const_string "mfjmpr") + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "*")]) (set_attr "length" "4,4,4,4,4,8,12,16,4")]) -(define_expand "movtf" - [(set (match_operand:TF 0 "general_operand" "") - (match_operand:TF 1 "any_operand" ""))] - "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128" - "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") +(define_expand "mov" + [(set (match_operand:FMOVE128 0 "general_operand" "") + (match_operand:FMOVE128 1 "any_operand" ""))] + "" + "{ rs6000_emit_move (operands[0], operands[1], mode); DONE; }") ;; It's important to list Y->r and r->Y before r->r because otherwise ;; reload, given m->r, will try to pick r->r and reload it, which ;; doesn't make progress. -(define_insn_and_split "*movtf_internal" - [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r") - (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))] - "!TARGET_IEEEQUAD - && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 - && (gpc_reg_operand (operands[0], TFmode) - || gpc_reg_operand (operands[1], TFmode))" + +;; We can't split little endian direct moves of TDmode, because the words are +;; not swapped like they are for TImode or TFmode. Subregs therefore are +;; problematical. Don't allow direct move for this case. + +(define_insn_and_split "*mov_64bit_dm" + [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm") + (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 + && (mode != TDmode || WORDS_BIG_ENDIAN) + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" + "#" + "&& reload_completed" + [(pc)] +{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } + [(set_attr "length" "8,8,8,12,12,8,8,8")]) + +(define_insn_and_split "*movtd_64bit_nodm" + [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") + (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN + && (gpc_reg_operand (operands[0], TDmode) + || gpc_reg_operand (operands[1], TDmode))" + "#" + "&& reload_completed" + [(pc)] +{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } + [(set_attr "length" "8,8,8,12,12,8")]) + +(define_insn_and_split "*mov_32bit" + [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r") + (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))] + "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "#" "&& reload_completed" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } [(set_attr "length" "8,8,8,20,20,16")]) -(define_insn_and_split "*movtf_softfloat" - [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r") - (match_operand:TF 1 "input_operand" "r,YGHF,r"))] - "!TARGET_IEEEQUAD - && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128 - && (gpc_reg_operand (operands[0], TFmode) - || gpc_reg_operand (operands[1], TFmode))" +(define_insn_and_split "*mov_softfloat" + [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r") + (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))] + "(TARGET_SOFT_FLOAT || !TARGET_FPRS) + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "#" "&& reload_completed" [(pc)] @@ -8556,6 +9950,252 @@ operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); }") + +;; Reload helper functions used by rs6000_secondary_reload. The patterns all +;; must have 3 arguments, and scratch register constraint must be a single +;; constraint. + +;; Reload patterns to support gpr load/store with misaligned mem. +;; and multiple gpr load/store at offset >= 0xfffc +(define_expand "reload__store" + [(parallel [(match_operand 0 "memory_operand" "=m") + (match_operand 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "register_operand" "=&b")])] + "" +{ + rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true); + DONE; +}) + +(define_expand "reload__load" + [(parallel [(match_operand 0 "gpc_reg_operand" "=r") + (match_operand 1 "memory_operand" "m") + (match_operand:GPR 2 "register_operand" "=b")])] + "" +{ + rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false); + DONE; +}) + + +;; Power8 merge instructions to allow direct move to/from floating point +;; registers in 32-bit mode. We use TF mode to get two registers to move the +;; individual 32-bit parts across. Subreg doesn't work too well on the TF +;; value, since it is allocated in reload and not all of the flow information +;; is setup for it. We have two patterns to do the two moves between gprs and +;; fprs. There isn't a dependancy between the two, but we could potentially +;; schedule other instructions between the two instructions. TFmode is +;; currently limited to traditional FPR registers. If/when this is changed, we +;; will need to revist %L to make sure it works with VSX registers, or add an +;; %x version of %L. + +(define_insn "p8_fmrgow_" + [(set (match_operand:FMOVE64X 0 "register_operand" "=d") + (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")] + UNSPEC_P8V_FMRGOW))] + "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "fmrgow %0,%1,%L1" + [(set_attr "type" "vecperm")]) + +(define_insn "p8_mtvsrwz_1" + [(set (match_operand:TF 0 "register_operand" "=d") + (unspec:TF [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_P8V_MTVSRWZ))] + "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrwz %x0,%1" + [(set_attr "type" "mftgpr")]) + +(define_insn "p8_mtvsrwz_2" + [(set (match_operand:TF 0 "register_operand" "+d") + (unspec:TF [(match_dup 0) + (match_operand:SI 1 "register_operand" "r")] + UNSPEC_P8V_MTVSRWZ))] + "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrwz %L0,%1" + [(set_attr "type" "mftgpr")]) + +(define_insn_and_split "reload_fpr_from_gpr" + [(set (match_operand:FMOVE64X 0 "register_operand" "=ws") + (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")] + UNSPEC_P8V_RELOAD_FROM_GPR)) + (clobber (match_operand:TF 2 "register_operand" "=d"))] + "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx tmp = operands[2]; + rtx gpr_hi_reg = gen_highpart (SImode, src); + rtx gpr_lo_reg = gen_lowpart (SImode, src); + + emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg)); + emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg)); + emit_insn (gen_p8_fmrgow_ (dest, tmp)); + DONE; +} + [(set_attr "length" "12") + (set_attr "type" "three")]) + +;; Move 128 bit values from GPRs to VSX registers in 64-bit mode +(define_insn "p8_mtvsrd_1" + [(set (match_operand:TF 0 "register_operand" "=ws") + (unspec:TF [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_P8V_MTVSRD))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrd %0,%1" + [(set_attr "type" "mftgpr")]) + +(define_insn "p8_mtvsrd_2" + [(set (match_operand:TF 0 "register_operand" "+ws") + (unspec:TF [(match_dup 0) + (match_operand:DI 1 "register_operand" "r")] + UNSPEC_P8V_MTVSRD))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mtvsrd %L0,%1" + [(set_attr "type" "mftgpr")]) + +(define_insn "p8_xxpermdi_" + [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa") + (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")] + UNSPEC_P8V_XXPERMDI))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "xxpermdi %x0,%1,%L1,0" + [(set_attr "type" "vecperm")]) + +(define_insn_and_split "reload_vsx_from_gpr" + [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa") + (unspec:FMOVE128_GPR + [(match_operand:FMOVE128_GPR 1 "register_operand" "r")] + UNSPEC_P8V_RELOAD_FROM_GPR)) + (clobber (match_operand:TF 2 "register_operand" "=ws"))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx tmp = operands[2]; + rtx gpr_hi_reg = gen_highpart (DImode, src); + rtx gpr_lo_reg = gen_lowpart (DImode, src); + + emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg)); + emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg)); + emit_insn (gen_p8_xxpermdi_ (dest, tmp)); +} + [(set_attr "length" "12") + (set_attr "type" "three")]) + +(define_split + [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "") + (match_operand:FMOVE128_GPR 1 "input_operand" ""))] + "reload_completed + && (int_reg_operand (operands[0], mode) + || int_reg_operand (operands[1], mode))" + [(pc)] +{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) + +;; Move SFmode to a VSX from a GPR register. Because scalar floating point +;; type is stored internally as double precision in the VSX registers, we have +;; to convert it from the vector format. + +(define_insn_and_split "reload_vsx_from_gprsf" + [(set (match_operand:SF 0 "register_operand" "=wa") + (unspec:SF [(match_operand:SF 1 "register_operand" "r")] + UNSPEC_P8V_RELOAD_FROM_GPR)) + (clobber (match_operand:DI 2 "register_operand" "=r"))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0); + rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); + + /* Move SF value to upper 32-bits for xscvspdpn. */ + emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); + emit_move_insn (op0_di, op2); + emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); + DONE; +} + [(set_attr "length" "8") + (set_attr "type" "two")]) + +;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a +;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value, +;; and then doing a move of that. +(define_insn "p8_mfvsrd_3_" + [(set (match_operand:DF 0 "register_operand" "=r") + (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")] + UNSPEC_P8V_RELOAD_FROM_VSX))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mfvsrd %0,%x1" + [(set_attr "type" "mftgpr")]) + +(define_insn_and_split "reload_gpr_from_vsx" + [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r") + (unspec:FMOVE128_GPR + [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")] + UNSPEC_P8V_RELOAD_FROM_VSX)) + (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx dest = operands[0]; + rtx src = operands[1]; + rtx tmp = operands[2]; + rtx gpr_hi_reg = gen_highpart (DFmode, dest); + rtx gpr_lo_reg = gen_lowpart (DFmode, dest); + + emit_insn (gen_p8_mfvsrd_3_ (gpr_hi_reg, src)); + emit_insn (gen_vsx_xxpermdi_ (tmp, src, src, GEN_INT (3))); + emit_insn (gen_p8_mfvsrd_3_ (gpr_lo_reg, tmp)); +} + [(set_attr "length" "12") + (set_attr "type" "three")]) + +;; Move SFmode to a GPR from a VSX register. Because scalar floating point +;; type is stored internally as double precision, we have to convert it to the +;; vector format. + +(define_insn_and_split "reload_gpr_from_vsxsf" + [(set (match_operand:SF 0 "register_operand" "=r") + (unspec:SF [(match_operand:SF 1 "register_operand" "wa")] + UNSPEC_P8V_RELOAD_FROM_VSX)) + (clobber (match_operand:V4SF 2 "register_operand" "=wa"))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(const_int 0)] +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0); + + emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1)); + emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2)); + emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32))); + DONE; +} + [(set_attr "length" "12") + (set_attr "type" "three")]) + +(define_insn "p8_mfvsrd_4_disf" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")] + UNSPEC_P8V_RELOAD_FROM_VSX))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "mfvsrd %0,%x1" + [(set_attr "type" "mftgpr")]) + ;; Next come the multi-word integer load and store and the load and store ;; multiple insns. @@ -8565,8 +10205,8 @@ ;; Use of fprs is disparaged slightly otherwise reload prefers to reload ;; a gpr into a fpr instead of reloading an invalid 'Y' address (define_insn "*movdi_internal32" - [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa") - (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))] + [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r") + (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))] "! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" @@ -8577,15 +10217,34 @@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 fmr %0,%1 - # - xxlxor %x0,%x0,%x0" - [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")]) + #" + [(set_attr_alternative "type" + [(const_string "store") + (const_string "load") + (const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (const_string "fp") + (const_string "*")])]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") (match_operand:DI 1 "const_int_operand" ""))] "! TARGET_POWERPC64 && reload_completed - && gpr_or_gpr_p (operands[0], operands[1])" + && gpr_or_gpr_p (operands[0], operands[1]) + && !direct_move_p (operands[0], operands[1])" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 1))] " @@ -8607,38 +10266,15 @@ [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "") (match_operand:DIFD 1 "input_operand" ""))] "reload_completed && !TARGET_POWERPC64 - && gpr_or_gpr_p (operands[0], operands[1])" + && gpr_or_gpr_p (operands[0], operands[1]) + && !direct_move_p (operands[0], operands[1])" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) -(define_insn "*movdi_mfpgpr" - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))] - "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS - && (gpc_reg_operand (operands[0], DImode) - || gpc_reg_operand (operands[1], DImode))" - "@ - std%U0%X0 %1,%0 - ld%U1%X1 %0,%1 - mr %0,%1 - li %0,%1 - lis %0,%v1 - # - stfd%U0%X0 %1,%0 - lfd%U1%X1 %0,%1 - fmr %0,%1 - mf%1 %0 - mt%0 %1 - nop - mftgpr %0,%1 - mffgpr %0,%1" - [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr") - (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")]) - (define_insn "*movdi_internal64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa") - (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))] - "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS) + [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wm") + (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wm,r"))] + "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) || gpc_reg_operand (operands[1], DImode))" "@ @@ -8654,9 +10290,52 @@ mf%1 %0 mt%0 %1 nop - xxlxor %x0,%x0,%x0" - [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple") - (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) + mftgpr %0,%1 + mffgpr %0,%1 + mfvsrd %0,%x1 + mtvsrd %x0,%1" + [(set_attr_alternative "type" + [(if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "load_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "load_u") + (const_string "load"))) + (const_string "*") + (const_string "*") + (const_string "*") + (const_string "*") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "fpstore_u") + (const_string "fpstore"))) + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (if_then_else + (match_test "update_address_mem (operands[1], VOIDmode)") + (const_string "fpload_u") + (const_string "fpload"))) + (const_string "fp") + (const_string "mfjmpr") + (const_string "mtjmpr") + (const_string "*") + (const_string "mftgpr") + (const_string "mffgpr") + (const_string "mftgpr") + (const_string "mffgpr")]) + (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4")]) ;; immediate value valid for a single instruction hiding in a const_double (define_insn "" @@ -8719,14 +10398,16 @@ FAIL; }") -;; TImode is similar, except that we usually want to compute the address into -;; a register and use lsi/stsi (the exception is during reload). +;; TImode/PTImode is similar, except that we usually want to compute the +;; address into a register and use lsi/stsi (the exception is during reload). -(define_insn "*movti_string" - [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r") - (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))] +(define_insn "*mov_string" + [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r") + (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))] "! TARGET_POWERPC64 - && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" + && (mode != TImode || VECTOR_MEM_NONE_P (TImode)) + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode))" "* { switch (which_alternative) @@ -8756,27 +10437,32 @@ (const_string "always") (const_string "conditional")))]) -(define_insn "*movti_ppc64" - [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r") - (match_operand:TI 1 "input_operand" "r,Y,r"))] - "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) - || gpc_reg_operand (operands[1], TImode))) - && VECTOR_MEM_NONE_P (TImode)" - "#" - [(set_attr "type" "store,load,*")]) +(define_insn "*mov_ppc64" + [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r") + (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))] + "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (mode) + && (gpc_reg_operand (operands[0], mode) + || gpc_reg_operand (operands[1], mode)))" +{ + return rs6000_output_move_128bit (operands); +} + [(set_attr "type" "store,store,load,load,*,*") + (set_attr "length" "8")]) (define_split - [(set (match_operand:TI 0 "gpc_reg_operand" "") - (match_operand:TI 1 "const_double_operand" ""))] - "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)" + [(set (match_operand:TI2 0 "int_reg_operand" "") + (match_operand:TI2 1 "const_double_operand" ""))] + "TARGET_POWERPC64 + && (VECTOR_MEM_NONE_P (mode) + || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))" [(set (match_dup 2) (match_dup 4)) (set (match_dup 3) (match_dup 5))] " { operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, - TImode); + mode); operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, - TImode); + mode); if (GET_CODE (operands[1]) == CONST_DOUBLE) { operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); @@ -8792,10 +10478,12 @@ }") (define_split - [(set (match_operand:TI 0 "nonimmediate_operand" "") - (match_operand:TI 1 "input_operand" ""))] - "reload_completed && VECTOR_MEM_NONE_P (TImode) - && gpr_or_gpr_p (operands[0], operands[1])" + [(set (match_operand:TI2 0 "nonimmediate_operand" "") + (match_operand:TI2 1 "input_operand" ""))] + "reload_completed + && gpr_or_gpr_p (operands[0], operands[1]) + && !direct_move_p (operands[0], operands[1]) + && !quad_load_store_p (operands[0], operands[1])" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) @@ -9651,7 +11339,7 @@ (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD) (clobber (reg:SI LR_REGNO))] - "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX" + "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" { if (TARGET_CMODEL != CMODEL_SMALL) return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;" @@ -9723,7 +11411,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) - (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))] + (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))] " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -9746,7 +11434,8 @@ (define_insn "*tls_gd_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] + (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%2@got@tlsgd@l" @@ -9759,7 +11448,8 @@ (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGD) (clobber (reg:SI LR_REGNO))] - "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS" + "HAVE_AS_TLS && TARGET_TLS_MARKERS + && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" "bl %z1(%3@tlsgd)\;nop" [(set_attr "type" "branch") (set_attr "length" "8")]) @@ -9791,7 +11481,7 @@ (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] UNSPEC_TLSLD) (clobber (reg:SI LR_REGNO))] - "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX" + "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" { if (TARGET_CMODEL != CMODEL_SMALL) return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;" @@ -9858,7 +11548,7 @@ (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 2) - (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))] + (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))] " { operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -9881,7 +11571,9 @@ (define_insn "*tls_ld_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))] + (unspec:TLSmode [(const_int 0) + (match_operand:TLSmode 2 "gpc_reg_operand" "b")] + UNSPEC_TLSLD)))] "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" "addi %0,%1,%&@got@tlsld@l" [(set_attr "length" "4")]) @@ -9892,7 +11584,8 @@ (match_operand 2 "" "g"))) (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD) (clobber (reg:SI LR_REGNO))] - "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS" + "HAVE_AS_TLS && TARGET_TLS_MARKERS + && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" "bl %z1(%&@tlsld)\;nop" [(set_attr "type" "branch") (set_attr "length" "8")]) @@ -9953,7 +11646,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) - (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))] + (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))] " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -9976,7 +11669,8 @@ (define_insn "*tls_got_dtprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] + (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTDTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l %0,%2@got@dtprel@l(%1)" @@ -10022,7 +11716,7 @@ (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL))) (set (match_dup 0) (lo_sum:TLSmode (match_dup 3) - (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))] + (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))] " { operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); @@ -10045,7 +11739,8 @@ (define_insn "*tls_got_tprel_low" [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") - (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] + (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") + (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] UNSPEC_TLSGOTTPREL)))] "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" "l %0,%2@got@tprel@l(%1)" @@ -10261,7 +11956,7 @@ [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (unspec:SI [(const_int 0)] UNSPEC_TOC)) (use (reg:SI 2))])] - "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" + "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT" "* { char buf[30]; @@ -10276,7 +11971,7 @@ [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (unspec:DI [(const_int 0)] UNSPEC_TOC)) (use (reg:DI 2))])] - "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" + "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT" "* { char buf[30]; @@ -10306,7 +12001,7 @@ [(parallel [(set (reg:SI LR_REGNO) (match_operand:SI 0 "immediate_operand" "s")) (use (unspec [(match_dup 0)] UNSPEC_TOC))])] - "TARGET_ELF && DEFAULT_ABI != ABI_AIX + "TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" "") @@ -10314,7 +12009,7 @@ [(set (reg:SI LR_REGNO) (match_operand:SI 0 "immediate_operand" "s")) (use (unspec [(match_dup 0)] UNSPEC_TOC))] - "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX + "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" "bcl 20,31,%0\\n%0:" [(set_attr "type" "branch") @@ -10324,7 +12019,7 @@ [(set (reg:SI LR_REGNO) (match_operand:SI 0 "immediate_operand" "s")) (use (unspec [(match_dup 0)] UNSPEC_TOC))] - "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX + "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" "* { @@ -10344,7 +12039,7 @@ (label_ref (match_operand 1 "" ""))] UNSPEC_TOCPTR)) (match_dup 1)])] - "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" "") (define_insn "load_toc_v4_PIC_1b_normal" @@ -10353,7 +12048,7 @@ (label_ref (match_operand 1 "" ""))] UNSPEC_TOCPTR)) (match_dup 1)] - "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" + "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" "bcl 20,31,$+8\;.long %0-$" [(set_attr "type" "branch") (set_attr "length" "8")]) @@ -10364,7 +12059,7 @@ (label_ref (match_operand 1 "" ""))] UNSPEC_TOCPTR)) (match_dup 1)] - "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" + "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" "* { char name[32]; @@ -10382,7 +12077,7 @@ (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] - "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" + "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" "lwz %0,%2-%3(%1)" [(set_attr "type" "load")]) @@ -10392,7 +12087,7 @@ (high:SI (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") (match_operand:SI 3 "symbol_ref_operand" "s")))))] - "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" + "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic" "addis %0,%1,%2-%3@ha") (define_insn "load_toc_v4_PIC_3c" @@ -10400,7 +12095,7 @@ (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") (match_operand:SI 3 "symbol_ref_operand" "s"))))] - "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" + "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic" "addi %0,%1,%2-%3@l") ;; If the TOC is shared over a translation unit, as happens with all @@ -10542,8 +12237,13 @@ operands[0] = XEXP (operands[0], 0); + if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + { + rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]); + DONE; + } + if (GET_CODE (operands[0]) != SYMBOL_REF - || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) { if (INTVAL (operands[2]) & CALL_LONG) @@ -10556,12 +12256,6 @@ operands[0] = force_reg (Pmode, operands[0]); break; - case ABI_AIX: - /* AIX function pointers are really pointers to a three word - area. */ - rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]); - DONE; - default: gcc_unreachable (); } @@ -10587,8 +12281,13 @@ operands[1] = XEXP (operands[1], 0); + if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + { + rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]); + DONE; + } + if (GET_CODE (operands[1]) != SYMBOL_REF - || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) { if (INTVAL (operands[3]) & CALL_LONG) @@ -10601,12 +12300,6 @@ operands[1] = force_reg (Pmode, operands[1]); break; - case ABI_AIX: - /* AIX function pointers are really pointers to a three word - area. */ - rs6000_call_indirect_aix (operands[0], operands[1], operands[2]); - DONE; - default: gcc_unreachable (); } @@ -10698,135 +12391,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) -;; Call to indirect functions with the AIX abi using a 3 word descriptor. -;; Operand0 is the addresss of the function to call -;; Operand1 is the flag for System V.4 for unprototyped or FP registers -;; Operand2 is the location in the function descriptor to load r2 from -;; Operand3 is the stack location to hold the current TOC pointer - -(define_insn "call_indirect_aix" - [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) - (match_operand 1 "" "g,g")) - (use (match_operand:P 2 "memory_operand" ",")) - (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" ",")) - (use (reg:P STATIC_CHAIN_REGNUM)) - (clobber (reg:P LR_REGNO))] - "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS" - " 2,%2\;b%T0l\; 2,%3" - [(set_attr "type" "jmpreg") - (set_attr "length" "12")]) - -;; Like call_indirect_aix, but no use of the static chain -;; Operand0 is the addresss of the function to call -;; Operand1 is the flag for System V.4 for unprototyped or FP registers -;; Operand2 is the location in the function descriptor to load r2 from -;; Operand3 is the stack location to hold the current TOC pointer - -(define_insn "call_indirect_aix_nor11" - [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) - (match_operand 1 "" "g,g")) - (use (match_operand:P 2 "memory_operand" ",")) - (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" ",")) - (clobber (reg:P LR_REGNO))] - "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS" - " 2,%2\;b%T0l\; 2,%3" - [(set_attr "type" "jmpreg") - (set_attr "length" "12")]) - -;; Operand0 is the return result of the function -;; Operand1 is the addresss of the function to call -;; Operand2 is the flag for System V.4 for unprototyped or FP registers -;; Operand3 is the location in the function descriptor to load r2 from -;; Operand4 is the stack location to hold the current TOC pointer - -(define_insn "call_value_indirect_aix" - [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:P 1 "register_operand" "c,*l")) - (match_operand 2 "" "g,g"))) - (use (match_operand:P 3 "memory_operand" ",")) - (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" ",")) - (use (reg:P STATIC_CHAIN_REGNUM)) - (clobber (reg:P LR_REGNO))] - "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS" - " 2,%3\;b%T1l\; 2,%4" - [(set_attr "type" "jmpreg") - (set_attr "length" "12")]) - -;; Like call_value_indirect_aix, but no use of the static chain -;; Operand0 is the return result of the function -;; Operand1 is the addresss of the function to call -;; Operand2 is the flag for System V.4 for unprototyped or FP registers -;; Operand3 is the location in the function descriptor to load r2 from -;; Operand4 is the stack location to hold the current TOC pointer - -(define_insn "call_value_indirect_aix_nor11" - [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:P 1 "register_operand" "c,*l")) - (match_operand 2 "" "g,g"))) - (use (match_operand:P 3 "memory_operand" ",")) - (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" ",")) - (clobber (reg:P LR_REGNO))] - "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS" - " 2,%3\;b%T1l\; 2,%4" - [(set_attr "type" "jmpreg") - (set_attr "length" "12")]) - -;; Call to function which may be in another module. Restore the TOC -;; pointer (r2) after the call unless this is System V. -;; Operand2 is nonzero if we are using the V.4 calling sequence and -;; either the function was not prototyped, or it was prototyped as a -;; variable argument function. It is > 0 if FP registers were passed -;; and < 0 if they were not. - -(define_insn "*call_nonlocal_aix32" - [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) - (match_operand 1 "" "g")) - (use (match_operand:SI 2 "immediate_operand" "O")) - (clobber (reg:SI LR_REGNO))] - "TARGET_32BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[2]) & CALL_LONG) == 0" - "bl %z0\;nop" - [(set_attr "type" "branch") - (set_attr "length" "8")]) - -(define_insn "*call_nonlocal_aix64" - [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) - (match_operand 1 "" "g")) - (use (match_operand:SI 2 "immediate_operand" "O")) - (clobber (reg:SI LR_REGNO))] - "TARGET_64BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[2]) & CALL_LONG) == 0" - "bl %z0\;nop" - [(set_attr "type" "branch") - (set_attr "length" "8")]) - -(define_insn "*call_value_nonlocal_aix32" - [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) - (match_operand 2 "" "g"))) - (use (match_operand:SI 3 "immediate_operand" "O")) - (clobber (reg:SI LR_REGNO))] - "TARGET_32BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[3]) & CALL_LONG) == 0" - "bl %z1\;nop" - [(set_attr "type" "branch") - (set_attr "length" "8")]) - -(define_insn "*call_value_nonlocal_aix64" - [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) - (match_operand 2 "" "g"))) - (use (match_operand:SI 3 "immediate_operand" "O")) - (clobber (reg:SI LR_REGNO))] - "TARGET_64BIT - && DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[3]) & CALL_LONG) == 0" - "bl %z1\;nop" - [(set_attr "type" "branch") - (set_attr "length" "8")]) ;; A function pointer under System V is just a normal pointer ;; operands[0] is the function pointer @@ -10984,30 +12548,128 @@ [(set_attr "type" "branch,branch") (set_attr "length" "4,8")]) -(define_insn "*call_value_nonlocal_sysv_secure" +(define_insn "*call_value_nonlocal_sysv_secure" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s")) + (match_operand 2 "" "g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (use (match_operand:SI 4 "register_operand" "r,r")) + (clobber (reg:SI LR_REGNO))] + "(DEFAULT_ABI == ABI_V4 + && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1]) + && (INTVAL (operands[3]) & CALL_LONG) == 0)" +{ + if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) + output_asm_insn ("crxor 6,6,6", operands); + + else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn ("creqv 6,6,6", operands); + + if (flag_pic == 2) + return "bl %z1+32768@plt"; + else + return "bl %z1@plt"; +} + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + + +;; Call to AIX abi function in the same module. + +(define_insn "*call_local_aix" + [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s")) + (match_operand 1 "" "g")) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" + "bl %z0" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*call_value_local_aix" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s")) + (match_operand 2 "" "g"))) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" + "bl %z1" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +;; Call to AIX abi function which may be in another module. +;; Restore the TOC pointer (r2) after the call. + +(define_insn "*call_nonlocal_aix" + [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s")) + (match_operand 1 "" "g")) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" + "bl %z0\;nop" + [(set_attr "type" "branch") + (set_attr "length" "8")]) + +(define_insn "*call_value_nonlocal_aix" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s")) + (match_operand 2 "" "g"))) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" + "bl %z1\;nop" + [(set_attr "type" "branch") + (set_attr "length" "8")]) + +;; Call to indirect functions with the AIX abi using a 3 word descriptor. +;; Operand0 is the addresss of the function to call +;; Operand2 is the location in the function descriptor to load r2 from +;; Operand3 is the stack location to hold the current TOC pointer + +(define_insn "*call_indirect_aix" + [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) + (match_operand 1 "" "g,g")) + (use (match_operand:P 2 "memory_operand" ",")) + (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" ",")) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_AIX" + " 2,%2\;b%T0l\; 2,%3" + [(set_attr "type" "jmpreg") + (set_attr "length" "12")]) + +(define_insn "*call_value_indirect_aix" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s")) + (call (mem:SI (match_operand:P 1 "register_operand" "c,*l")) (match_operand 2 "" "g,g"))) - (use (match_operand:SI 3 "immediate_operand" "O,n")) - (use (match_operand:SI 4 "register_operand" "r,r")) - (clobber (reg:SI LR_REGNO))] - "(DEFAULT_ABI == ABI_V4 - && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1]) - && (INTVAL (operands[3]) & CALL_LONG) == 0)" -{ - if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn ("crxor 6,6,6", operands); + (use (match_operand:P 3 "memory_operand" ",")) + (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" ",")) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_AIX" + " 2,%3\;b%T1l\; 2,%4" + [(set_attr "type" "jmpreg") + (set_attr "length" "12")]) - else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn ("creqv 6,6,6", operands); +;; Call to indirect functions with the ELFv2 ABI. +;; Operand0 is the addresss of the function to call +;; Operand2 is the stack location to hold the current TOC pointer + +(define_insn "*call_indirect_elfv2" + [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) + (match_operand 1 "" "g,g")) + (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" ",")) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_ELFv2" + "b%T0l\; 2,%2" + [(set_attr "type" "jmpreg") + (set_attr "length" "8")]) + +(define_insn "*call_value_indirect_elfv2" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:P 1 "register_operand" "c,*l")) + (match_operand 2 "" "g,g"))) + (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" ",")) + (clobber (reg:P LR_REGNO))] + "DEFAULT_ABI == ABI_ELFv2" + "b%T1l\; 2,%3" + [(set_attr "type" "jmpreg") + (set_attr "length" "8")]) - if (flag_pic == 2) - return "bl %z1+32768@plt"; - else - return "bl %z1@plt"; -} - [(set_attr "type" "branch,branch") - (set_attr "length" "4,8")]) ;; Call subroutine returning any type. (define_expand "untyped_call" @@ -11056,6 +12718,39 @@ gcc_assert (GET_CODE (operands[1]) == CONST_INT); operands[0] = XEXP (operands[0], 0); + + if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + { + rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]); + DONE; + } +}") + +(define_expand "sibcall_value" + [(parallel [(set (match_operand 0 "register_operand" "") + (call (mem:SI (match_operand 1 "address_operand" "")) + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (use (reg:SI LR_REGNO)) + (simple_return)])] + "" + " +{ +#if TARGET_MACHO + if (MACHOPIC_INDIRECT) + operands[1] = machopic_indirect_call_target (operands[1]); +#endif + + gcc_assert (GET_CODE (operands[1]) == MEM); + gcc_assert (GET_CODE (operands[2]) == CONST_INT); + + operands[1] = XEXP (operands[1], 0); + + if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) + { + rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]); + DONE; + } }") ;; this and similar patterns must be marked as using LR, otherwise @@ -11123,7 +12818,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) - (define_insn "*sibcall_value_local64" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) @@ -11145,35 +12839,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8")]) -(define_insn "*sibcall_nonlocal_aix" - [(call (mem:SI (match_operand:P 0 "call_operand" "s,c")) - (match_operand 1 "" "g,g")) - (use (match_operand:SI 2 "immediate_operand" "O,O")) - (use (reg:SI LR_REGNO)) - (simple_return)] - "DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[2]) & CALL_LONG) == 0" - "@ - b %z0 - b%T0" - [(set_attr "type" "branch") - (set_attr "length" "4")]) - -(define_insn "*sibcall_value_nonlocal_aix" - [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:P 1 "call_operand" "s,c")) - (match_operand 2 "" "g,g"))) - (use (match_operand:SI 3 "immediate_operand" "O,O")) - (use (reg:SI LR_REGNO)) - (simple_return)] - "DEFAULT_ABI == ABI_AIX - && (INTVAL (operands[3]) & CALL_LONG) == 0" - "@ - b %z1 - b%T1" - [(set_attr "type" "branch") - (set_attr "length" "4")]) - (define_insn "*sibcall_nonlocal_sysv" [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c")) (match_operand 1 "" "")) @@ -11204,27 +12869,6 @@ [(set_attr "type" "branch") (set_attr "length" "4,8,4,8")]) -(define_expand "sibcall_value" - [(parallel [(set (match_operand 0 "register_operand" "") - (call (mem:SI (match_operand 1 "address_operand" "")) - (match_operand 2 "" ""))) - (use (match_operand 3 "" "")) - (use (reg:SI LR_REGNO)) - (simple_return)])] - "" - " -{ -#if TARGET_MACHO - if (MACHOPIC_INDIRECT) - operands[1] = machopic_indirect_call_target (operands[1]); -#endif - - gcc_assert (GET_CODE (operands[1]) == MEM); - gcc_assert (GET_CODE (operands[2]) == CONST_INT); - - operands[1] = XEXP (operands[1], 0); -}") - (define_insn "*sibcall_value_nonlocal_sysv" [(set (match_operand 0 "" "") (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c")) @@ -11256,6 +12900,31 @@ [(set_attr "type" "branch") (set_attr "length" "4,8,4,8")]) +;; AIX ABI sibling call patterns. + +(define_insn "*sibcall_aix" + [(call (mem:SI (match_operand:P 0 "call_operand" "s,c")) + (match_operand 1 "" "g,g")) + (simple_return)] + "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" + "@ + b %z0 + b%T0" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_value_aix" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:P 1 "call_operand" "s,c")) + (match_operand 2 "" "g,g"))) + (simple_return)] + "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" + "@ + b %z1 + b%T1" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + (define_expand "sibcall_epilogue" [(use (const_int 0))] "" @@ -11294,7 +12963,14 @@ operands[1] = gen_rtx_REG (Pmode, 0); return "st%U0%X0 %1,%0"; } - [(set_attr "type" "store") + [(set (attr "type") + (if_then_else + (match_test "update_indexed_address_mem (operands[0], VOIDmode)") + (const_string "store_ux") + (if_then_else + (match_test "update_address_mem (operands[0], VOIDmode)") + (const_string "store_u") + (const_string "store")))) (set_attr "length" "4")]) (define_insn "probe_stack_range" @@ -11589,23 +13265,6 @@ [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) -(define_insn "*cmpsf_internal1" - [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") - (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" - "fcmpu %0,%1,%2" - [(set_attr "type" "fpcompare")]) - -(define_insn "*cmpdf_internal1" - [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d") - (match_operand:DF 2 "gpc_reg_operand" "d")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && !VECTOR_UNIT_VSX_P (DFmode)" - "fcmpu %0,%1,%2" - [(set_attr "type" "fpcompare")]) - ;; Only need to compare second words if first words equal (define_insn "*cmptf_internal1" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") @@ -13501,6 +15160,14 @@ "mfcr %0" [(set_attr "type" "mfcr")]) +(define_insn "*crsave" + [(match_parallel 0 "crsave_operation" + [(set (match_operand:SI 1 "memory_operand" "=m") + (match_operand:SI 2 "gpc_reg_operand" "r"))])] + "" + "stw %2,%1" + [(set_attr "type" "store")]) + (define_insn "*stmw" [(match_parallel 0 "stmw_operation" [(set (match_operand:SI 1 "memory_operand" "=m") @@ -13885,7 +15552,7 @@ (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))] "TARGET_POPCNTD" "bpermd %0,%1,%2" - [(set_attr "type" "integer")]) + [(set_attr "type" "popcnt")]) ;; Builtin fma support. Handle @@ -13900,6 +15567,20 @@ "" "") +(define_insn "*fma4_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + (fma:SFDF + (match_operand:SFDF 1 "gpc_reg_operand" "%,,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))] + "TARGET__FPR" + "@ + fmadd %0,%1,%2,%3 + xsmadda %x0,%x1,%x2 + xsmaddm %x0,%x1,%x3" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_maddsub_")]) + ; Altivec only has fma and nfms. (define_expand "fms4" [(set (match_operand:FMA_F 0 "register_operand" "") @@ -13910,6 +15591,20 @@ "!VECTOR_UNIT_ALTIVEC_P (mode)" "") +(define_insn "*fms4_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + (fma:SFDF + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] + "TARGET__FPR" + "@ + fmsub %0,%1,%2,%3 + xsmsuba %x0,%x1,%x2 + xsmsubm %x0,%x1,%x3" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_maddsub_")]) + ;; If signed zeros are ignored, -(a * b - c) = -a * b + c. (define_expand "fnma4" [(set (match_operand:FMA_F 0 "register_operand" "") @@ -13943,6 +15638,21 @@ "!VECTOR_UNIT_ALTIVEC_P (mode)" "") +(define_insn "*nfma4_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + (neg:SFDF + (fma:SFDF + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (match_operand:SFDF 3 "gpc_reg_operand" ",0,"))))] + "TARGET__FPR" + "@ + fnmadd %0,%1,%2,%3 + xsnmadda %x0,%x1,%x2 + xsnmaddm %x0,%x1,%x3" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_maddsub_")]) + ; Not an official optab name, but used from builtins. (define_expand "nfms4" [(set (match_operand:FMA_F 0 "register_operand" "") @@ -13954,6 +15664,23 @@ "" "") +(define_insn "*nfmssf4_fpr" + [(set (match_operand:SFDF 0 "gpc_reg_operand" "=,,") + (neg:SFDF + (fma:SFDF + (match_operand:SFDF 1 "gpc_reg_operand" ",,") + (match_operand:SFDF 2 "gpc_reg_operand" ",,0") + (neg:SFDF + (match_operand:SFDF 3 "gpc_reg_operand" ",0,")))))] + "TARGET__FPR" + "@ + fnmsub %0,%1,%2,%3 + xsnmsuba %x0,%x1,%x2 + xsnmsubm %x0,%x1,%x3" + [(set_attr "type" "fp") + (set_attr "fp_type" "fp_maddsub_")]) + + (define_expand "rs6000_get_timebase" [(use (match_operand:DI 0 "gpc_reg_operand" ""))] "" @@ -14019,6 +15746,228 @@ return "mftb %0"; }) + +;; Power8 fusion support for fusing an addis instruction with a D-form load of +;; a GPR. The addis instruction must be adjacent to the load, and use the same +;; register that is being loaded. The fused ops must be physically adjacent. + +;; We use define_peephole for the actual addis/load, and the register used to +;; hold the addis value must be the same as the register being loaded. We use +;; define_peephole2 to change the register used for addis to be the register +;; being loaded, since we can look at whether it is dead after the load insn. + +(define_peephole + [(set (match_operand:P 0 "base_reg_operand" "") + (match_operand:P 1 "fusion_gpr_addis" "")) + (set (match_operand:INT1 2 "base_reg_operand" "") + (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] + "TARGET_P8_FUSION && fusion_gpr_load_p (operands, false)" +{ + return emit_fusion_gpr_load (operands); +} + [(set_attr "type" "load") + (set_attr "length" "8")]) + +(define_peephole2 + [(set (match_operand:P 0 "base_reg_operand" "") + (match_operand:P 1 "fusion_gpr_addis" "")) + (set (match_operand:INT1 2 "base_reg_operand" "") + (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] + "TARGET_P8_FUSION + && (REGNO (operands[0]) != REGNO (operands[2]) + || GET_CODE (operands[3]) == SIGN_EXTEND) + && fusion_gpr_load_p (operands, true)" + [(const_int 0)] +{ + expand_fusion_gpr_load (operands); + DONE; +}) + + +;; Miscellaneous ISA 2.06 (power7) instructions +(define_insn "addg6s" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_ADDG6S))] + "TARGET_POPCNTD" + "addg6s %0,%1,%2" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + +(define_insn "cdtbcd" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CDTBCD))] + "TARGET_POPCNTD" + "cdtbcd %0,%1" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + +(define_insn "cbcdtd" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_CBCDTD))] + "TARGET_POPCNTD" + "cbcdtd %0,%1" + [(set_attr "type" "integer") + (set_attr "length" "4")]) + +(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE + UNSPEC_DIVEO + UNSPEC_DIVEU + UNSPEC_DIVEUO]) + +(define_int_attr div_extend [(UNSPEC_DIVE "e") + (UNSPEC_DIVEO "eo") + (UNSPEC_DIVEU "eu") + (UNSPEC_DIVEUO "euo")]) + +(define_insn "div_" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") + (match_operand:GPR 2 "register_operand" "r")] + UNSPEC_DIV_EXTEND))] + "TARGET_POPCNTD" + "div %0,%1,%2" + [(set_attr "type" "")]) + + +;; Pack/unpack 128-bit floating point types that take 2 scalar registers + +; Type of the 64-bit part when packing/unpacking 128-bit floating point types +(define_mode_attr FP128_64 [(TF "DF") (TD "DI")]) + +(define_expand "unpack" + [(set (match_operand: 0 "nonimmediate_operand" "") + (unspec: + [(match_operand:FMOVE128 1 "register_operand" "") + (match_operand:QI 2 "const_0_to_1_operand" "")] + UNSPEC_UNPACK_128BIT))] + "" + "") + +;; The Advance Toolchain 7.0-3 added private builtins: __builtin_longdouble_dw0 +;; and __builtin_longdouble_dw1 to optimize glibc. Add support for these +;; builtins here. + +(define_expand "unpacktf_0" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (unspec:DF [(match_operand:TF 1 "register_operand" "") + (const_int 0)] + UNSPEC_UNPACK_128BIT))] + "" + "") + +(define_expand "unpacktf_1" + [(set (match_operand:DF 0 "nonimmediate_operand" "") + (unspec:DF [(match_operand:TF 1 "register_operand" "") + (const_int 1)] + UNSPEC_UNPACK_128BIT))] + "" + "") + +(define_insn_and_split "unpack_dm" + [(set (match_operand: 0 "nonimmediate_operand" "=d,m,d,r,m") + (unspec: + [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") + (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] + UNSPEC_UNPACK_128BIT))] + "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); + + if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) + { + emit_note (NOTE_INSN_DELETED); + DONE; + } + + operands[3] = gen_rtx_REG (mode, fp_regno); +} + [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store") + (set_attr "length" "4")]) + +(define_insn_and_split "unpack_nodm" + [(set (match_operand: 0 "nonimmediate_operand" "=d,m") + (unspec: + [(match_operand:FMOVE128 1 "register_operand" "d,d") + (match_operand:QI 2 "const_0_to_1_operand" "i,i")] + UNSPEC_UNPACK_128BIT))] + "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE" + "#" + "&& reload_completed" + [(set (match_dup 0) (match_dup 3))] +{ + unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); + + if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) + { + emit_note (NOTE_INSN_DELETED); + DONE; + } + + operands[3] = gen_rtx_REG (mode, fp_regno); +} + [(set_attr "type" "fp,fpstore") + (set_attr "length" "4")]) + +(define_insn_and_split "pack" + [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d") + (unspec:FMOVE128 + [(match_operand: 1 "register_operand" "0,d") + (match_operand: 2 "register_operand" "d,d")] + UNSPEC_PACK_128BIT))] + "" + "@ + fmr %L0,%2 + #" + "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 4) (match_dup 2))] +{ + unsigned dest_hi = REGNO (operands[0]); + unsigned dest_lo = dest_hi + 1; + + gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo)); + gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo)); + + operands[3] = gen_rtx_REG (mode, dest_hi); + operands[4] = gen_rtx_REG (mode, dest_lo); +} + [(set_attr "type" "fp,fp") + (set_attr "length" "4,8")]) + +(define_insn "unpackv1ti" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa") + (match_operand:QI 2 "const_0_to_1_operand" "O,i")] + UNSPEC_UNPACK_128BIT))] + "TARGET_VSX" +{ + if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0) + return ASM_COMMENT_START " xxpermdi to same register"; + + operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3); + return "xxpermdi %x0,%x1,%x1,%3"; +} + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + +(define_insn "packv1ti" + [(set (match_operand:V1TI 0 "register_operand" "=wa") + (unspec:V1TI + [(match_operand:DI 1 "register_operand" "d") + (match_operand:DI 2 "register_operand" "d")] + UNSPEC_PACK_128BIT))] + "TARGET_VSX" + "xxpermdi %x0,%x1,%x2,0" + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + (include "sync.md") @@ -14028,3 +15977,5 @@ (include "spe.md") (include "dfp.md") (include "paired.md") +(include "crypto.md") +(include "htm.md") diff --git a/gcc-4.8/gcc/config/rs6000/rs6000.opt b/gcc-4.8/gcc/config/rs6000/rs6000.opt index 8e3cea121..5b56eb0da 100644 --- a/gcc-4.8/gcc/config/rs6000/rs6000.opt +++ b/gcc-4.8/gcc/config/rs6000/rs6000.opt @@ -1,6 +1,6 @@ ; Options for the rs6000 port of the compiler ; -; Copyright (C) 2005-2013 Free Software Foundation, Inc. +; Copyright (C) 2005-2014 Free Software Foundation, Inc. ; Contributed by Aldy Hernandez . ; ; This file is part of GCC. @@ -137,6 +137,14 @@ maltivec Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) Use AltiVec instructions +maltivec=le +Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save +Generate Altivec instructions using little-endian element order + +maltivec=be +Target Report RejectNegative Var(rs6000_altivec_element_order, 2) +Generate Altivec instructions using big-endian element order + mhard-dfp Target Report Mask(DFP) Var(rs6000_isa_flags) Use decimal floating point instructions @@ -181,13 +189,16 @@ mvsx Target Report Mask(VSX) Var(rs6000_isa_flags) Use vector/scalar (VSX) instructions +mvsx-scalar-float +Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1) +; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default) + mvsx-scalar-double -Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) -; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) +Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1) +; If -mvsx, use VSX arithmetic instructions for DFmode (on by default) mvsx-scalar-memory -Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) -; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) +Target Undocumented Report Alias(mupper-regs-df) mvsx-align-128 Target Undocumented Report Var(TARGET_VSX_ALIGN_128) @@ -363,6 +374,14 @@ mabi=no-spe Target RejectNegative Var(rs6000_spe_abi, 0) Do not use the SPE ABI extensions +mabi=elfv1 +Target RejectNegative Var(rs6000_elf_abi, 1) Save +Use the ELFv1 ABI + +mabi=elfv2 +Target RejectNegative Var(rs6000_elf_abi, 2) +Use the ELFv2 ABI + ; These are here for testing during development only, do not document ; in the manual please. @@ -443,6 +462,10 @@ mlong-double- Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save -mlong-double- Specify size of long double (64 or 128 bits) +mlra +Target Report Var(rs6000_lra_flag) Init(0) Save +Use LRA instead of reload + msched-costly-dep= Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) Determine which dependences between insns are considered costly @@ -514,3 +537,51 @@ Use/do not use r11 to hold the static link in calls to functions via pointers. msave-toc-indirect Target Report Var(TARGET_SAVE_TOC_INDIRECT) Save Control whether we save the TOC in the prologue for indirect calls or generate the save inline + +mvsx-timode +Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags) +Allow 128-bit integers in VSX registers + +mpower8-fusion +Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) +Fuse certain integer operations together for better performance on power8 + +mpower8-fusion-sign +Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) +Allow sign extension in fusion operations + +mpower8-vector +Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) +Use/do not use vector and scalar instructions added in ISA 2.07. + +mcrypto +Target Report Mask(CRYPTO) Var(rs6000_isa_flags) +Use ISA 2.07 crypto instructions + +mdirect-move +Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) +Use ISA 2.07 direct move between GPR & VSX register instructions + +mhtm +Target Report Mask(HTM) Var(rs6000_isa_flags) +Use ISA 2.07 transactional memory (HTM) instructions + +mquad-memory +Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) +Generate the quad word memory instructions (lq/stq). + +mquad-memory-atomic +Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) +Generate the quad word memory atomic instructions (lqarx/stqcx). + +mcompat-align-parm +Target Report Var(rs6000_compat_align_parm) Init(1) Save +Generate aggregate parameter passing code with at most 64-bit alignment. + +mupper-regs-df +Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) +Allow double variables in upper registers with -mcpu=power7 or -mvsx + +mupper-regs-sf +Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) +Allow float variables in upper registers with -mcpu=power8 or -mp8-vector diff --git a/gcc-4.8/gcc/config/rs6000/sync.md b/gcc-4.8/gcc/config/rs6000/sync.md index 252e2690a..74b59ec2c 100644 --- a/gcc-4.8/gcc/config/rs6000/sync.md +++ b/gcc-4.8/gcc/config/rs6000/sync.md @@ -1,5 +1,5 @@ ;; Machine description for PowerPC synchronization instructions. -;; Copyright (C) 2005-2013 Free Software Foundation, Inc. +;; Copyright (C) 2005-2014 Free Software Foundation, Inc. ;; Contributed by Geoffrey Keating. ;; This file is part of GCC. @@ -18,14 +18,23 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -(define_mode_attr larx [(SI "lwarx") (DI "ldarx")]) -(define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")]) +(define_mode_attr larx [(QI "lbarx") + (HI "lharx") + (SI "lwarx") + (DI "ldarx") + (TI "lqarx")]) + +(define_mode_attr stcx [(QI "stbcx.") + (HI "sthcx.") + (SI "stwcx.") + (DI "stdcx.") + (TI "stqcx.")]) (define_code_iterator FETCHOP [plus minus ior xor and]) (define_code_attr fetchop_name [(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")]) (define_code_attr fetchop_pred - [(plus "add_operand") (minus "gpc_reg_operand") + [(plus "add_operand") (minus "int_reg_operand") (ior "logical_operand") (xor "logical_operand") (and "and_operand")]) (define_expand "mem_thread_fence" @@ -98,10 +107,17 @@ "isync" [(set_attr "type" "isync")]) +;; Types that we should provide atomic instructions for. +(define_mode_iterator AINT [QI + HI + SI + (DI "TARGET_POWERPC64") + (TI "TARGET_SYNC_TI")]) + ;; The control dependency used for load dependency described ;; in B.2.3 of the Power ISA 2.06B. (define_insn "loadsync_" - [(unspec_volatile:BLK [(match_operand:INT1 0 "register_operand" "r")] + [(unspec_volatile:BLK [(match_operand:AINT 0 "register_operand" "r")] UNSPECV_ISYNC) (clobber (match_scratch:CC 1 "=y"))] "" @@ -109,18 +125,73 @@ [(set_attr "type" "isync") (set_attr "length" "12")]) +(define_insn "load_quadpti" + [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") + (unspec:PTI + [(match_operand:TI 1 "quad_memory_operand" "wQ")] UNSPEC_LSQ))] + "TARGET_SYNC_TI + && !reg_mentioned_p (operands[0], operands[1])" + "lq %0,%1" + [(set_attr "type" "load") + (set_attr "length" "4")]) + (define_expand "atomic_load" - [(set (match_operand:INT1 0 "register_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "")) ;; memory + [(set (match_operand:AINT 0 "register_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "")) ;; memory (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { + if (mode == TImode && !TARGET_SYNC_TI) + FAIL; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); if (model == MEMMODEL_SEQ_CST) emit_insn (gen_hwsync ()); + if (mode != TImode) emit_move_insn (operands[0], operands[1]); + else + { + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti_reg = gen_reg_rtx (PTImode); + + // Can't have indexed address for 'lq' + if (indexed_address (XEXP (op1, 0), TImode)) + { + rtx old_addr = XEXP (op1, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[1] = op1 = replace_equiv_address (op1, new_addr); + } + + emit_insn (gen_load_quadpti (pti_reg, op1)); + + /* For 4.8 we need to do explicit dword copies, even in big endian mode, + unless we are using the LRA register allocator. The 4.9 register + allocator is smart enough to assign an even/odd pair. */ + if (WORDS_BIG_ENDIAN && rs6000_lra_flag) + emit_move_insn (op0, gen_lowpart (TImode, pti_reg)); + else + { + rtx op0_lo = gen_lowpart (DImode, op0); + rtx op0_hi = gen_highpart (DImode, op0); + rtx pti_lo = gen_lowpart (DImode, pti_reg); + rtx pti_hi = gen_highpart (DImode, pti_reg); + + emit_insn (gen_rtx_CLOBBER (VOIDmode, op0)); + if (WORDS_BIG_ENDIAN) + { + emit_move_insn (op0_hi, pti_hi); + emit_move_insn (op0_lo, pti_lo); + } + else + { + emit_move_insn (op0_hi, pti_lo); + emit_move_insn (op0_lo, pti_hi); + } + } + } switch (model) { @@ -129,16 +200,7 @@ case MEMMODEL_CONSUME: case MEMMODEL_ACQUIRE: case MEMMODEL_SEQ_CST: - if (GET_MODE (operands[0]) == QImode) - emit_insn (gen_loadsync_qi (operands[0])); - else if (GET_MODE (operands[0]) == HImode) - emit_insn (gen_loadsync_hi (operands[0])); - else if (GET_MODE (operands[0]) == SImode) - emit_insn (gen_loadsync_si (operands[0])); - else if (GET_MODE (operands[0]) == DImode) - emit_insn (gen_loadsync_di (operands[0])); - else - gcc_unreachable (); + emit_insn (gen_loadsync_ (operands[0])); break; default: gcc_unreachable (); @@ -146,12 +208,24 @@ DONE; }) +(define_insn "store_quadpti" + [(set (match_operand:PTI 0 "quad_memory_operand" "=wQ") + (unspec:PTI + [(match_operand:PTI 1 "quad_int_reg_operand" "r")] UNSPEC_LSQ))] + "TARGET_SYNC_TI" + "stq %1,%0" + [(set_attr "type" "store") + (set_attr "length" "4")]) + (define_expand "atomic_store" - [(set (match_operand:INT1 0 "memory_operand" "") ;; memory - (match_operand:INT1 1 "register_operand" "")) ;; input + [(set (match_operand:AINT 0 "memory_operand" "") ;; memory + (match_operand:AINT 1 "register_operand" "")) ;; input (use (match_operand:SI 2 "const_int_operand" ""))] ;; model "" { + if (mode == TImode && !TARGET_SYNC_TI) + FAIL; + enum memmodel model = (enum memmodel) INTVAL (operands[2]); switch (model) { @@ -166,39 +240,224 @@ default: gcc_unreachable (); } + if (mode != TImode) emit_move_insn (operands[0], operands[1]); + else + { + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti_reg = gen_reg_rtx (PTImode); + + // Can't have indexed address for 'stq' + if (indexed_address (XEXP (op0, 0), TImode)) + { + rtx old_addr = XEXP (op0, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[0] = op0 = replace_equiv_address (op0, new_addr); + } + + /* For 4.8 we need to do explicit dword copies, even in big endian mode, + unless we are using the LRA register allocator. The 4.9 register + allocator is smart enough to assign an even/odd pair. */ + if (WORDS_BIG_ENDIAN && rs6000_lra_flag) + emit_move_insn (pti_reg, gen_lowpart (PTImode, op1)); + else + { + rtx op1_lo = gen_lowpart (DImode, op1); + rtx op1_hi = gen_highpart (DImode, op1); + rtx pti_lo = gen_lowpart (DImode, pti_reg); + rtx pti_hi = gen_highpart (DImode, pti_reg); + + emit_insn (gen_rtx_CLOBBER (VOIDmode, pti_reg)); + if (WORDS_BIG_ENDIAN) + { + emit_move_insn (pti_hi, op1_hi); + emit_move_insn (pti_lo, op1_lo); + } + else + { + emit_move_insn (pti_hi, op1_lo); + emit_move_insn (pti_lo, op1_hi); + } + } + + emit_insn (gen_store_quadpti (gen_lowpart (PTImode, op0), pti_reg)); + } + DONE; }) -;; ??? Power ISA 2.06B says that there *is* a load-{byte,half}-and-reserve -;; opcode that is "phased-in". Not implemented as of Power7, so not yet used, -;; but let's prepare the macros anyway. - -(define_mode_iterator ATOMIC [SI (DI "TARGET_POWERPC64")]) +;; Any supported integer mode that has atomic larx/stcx. instrucitons +;; other than the quad memory operations, which have special restrictions. +;; Byte/halfword atomic instructions were added in ISA 2.06B, but were phased +;; in and did not show up until power8. TImode atomic lqarx/stqcx. require +;; special handling due to even/odd register requirements. +(define_mode_iterator ATOMIC [(QI "TARGET_SYNC_HI_QI") + (HI "TARGET_SYNC_HI_QI") + SI + (DI "TARGET_POWERPC64")]) (define_insn "load_locked" - [(set (match_operand:ATOMIC 0 "gpc_reg_operand" "=r") + [(set (match_operand:ATOMIC 0 "int_reg_operand" "=r") (unspec_volatile:ATOMIC [(match_operand:ATOMIC 1 "memory_operand" "Z")] UNSPECV_LL))] "" " %0,%y1" [(set_attr "type" "load_l")]) +(define_insn "load_locked_si" + [(set (match_operand:SI 0 "int_reg_operand" "=r") + (unspec_volatile:SI + [(match_operand:QHI 1 "memory_operand" "Z")] UNSPECV_LL))] + "TARGET_SYNC_HI_QI" + " %0,%y1" + [(set_attr "type" "load_l")]) + +;; Use PTImode to get even/odd register pairs. + +;; Use a temporary register to force getting an even register for the +;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy, +;; even in big endian mode, unless we are using the LRA register allocator. In +;; GCC 4.9, the register allocator is smart enough to assign a even/odd +;; register pair. + +;; On little endian systems where non-atomic quad word load/store instructions +;; are not used, the address can be register+offset, so make sure the address +;; is indexed or indirect before register allocation. + +(define_expand "load_lockedti" + [(use (match_operand:TI 0 "quad_int_reg_operand" "")) + (use (match_operand:TI 1 "memory_operand" ""))] + "TARGET_SYNC_TI" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx pti = gen_reg_rtx (PTImode); + + if (!indexed_or_indirect_operand (op1, TImode)) + { + rtx old_addr = XEXP (op1, 0); + rtx new_addr = force_reg (Pmode, old_addr); + operands[1] = op1 = change_address (op1, TImode, new_addr); + } + + emit_insn (gen_load_lockedpti (pti, op1)); + if (WORDS_BIG_ENDIAN && rs6000_lra_flag) + emit_move_insn (op0, gen_lowpart (TImode, pti)); + else + { + rtx op0_lo = gen_lowpart (DImode, op0); + rtx op0_hi = gen_highpart (DImode, op0); + rtx pti_lo = gen_lowpart (DImode, pti); + rtx pti_hi = gen_highpart (DImode, pti); + + emit_insn (gen_rtx_CLOBBER (VOIDmode, op0)); + if (WORDS_BIG_ENDIAN) + { + emit_move_insn (op0_hi, pti_hi); + emit_move_insn (op0_lo, pti_lo); + } + else + { + emit_move_insn (op0_hi, pti_lo); + emit_move_insn (op0_lo, pti_hi); + } + } + DONE; +}) + +(define_insn "load_lockedpti" + [(set (match_operand:PTI 0 "quad_int_reg_operand" "=&r") + (unspec_volatile:PTI + [(match_operand:TI 1 "indexed_or_indirect_operand" "Z")] UNSPECV_LL))] + "TARGET_SYNC_TI + && !reg_mentioned_p (operands[0], operands[1]) + && quad_int_reg_operand (operands[0], PTImode)" + "lqarx %0,%y1" + [(set_attr "type" "load_l")]) + (define_insn "store_conditional" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (unspec_volatile:CC [(const_int 0)] UNSPECV_SC)) (set (match_operand:ATOMIC 1 "memory_operand" "=Z") - (match_operand:ATOMIC 2 "gpc_reg_operand" "r"))] + (match_operand:ATOMIC 2 "int_reg_operand" "r"))] "" " %2,%y1" [(set_attr "type" "store_c")]) +;; Use a temporary register to force getting an even register for the +;; lqarx/stqcrx. instructions. Under AT 7.0, we need use an explicit copy, +;; even in big endian mode. In GCC 4.9, the register allocator is smart enough +;; to assign a even/odd register pair. + +;; On little endian systems where non-atomic quad word load/store instructions +;; are not used, the address can be register+offset, so make sure the address +;; is indexed or indirect before register allocation. + +(define_expand "store_conditionalti" + [(use (match_operand:CC 0 "cc_reg_operand" "")) + (use (match_operand:TI 1 "memory_operand" "")) + (use (match_operand:TI 2 "quad_int_reg_operand" ""))] + "TARGET_SYNC_TI" +{ + rtx op0 = operands[0]; + rtx op1 = operands[1]; + rtx op2 = operands[2]; + rtx addr = XEXP (op1, 0); + rtx pti_mem; + rtx pti_reg; + + if (!indexed_or_indirect_operand (op1, TImode)) + { + rtx new_addr = force_reg (Pmode, addr); + operands[1] = op1 = change_address (op1, TImode, new_addr); + addr = new_addr; + } + + pti_mem = change_address (op1, PTImode, addr); + pti_reg = gen_reg_rtx (PTImode); + + if (WORDS_BIG_ENDIAN && rs6000_lra_flag) + emit_move_insn (pti_reg, gen_lowpart (PTImode, op2)); + else + { + rtx op2_lo = gen_lowpart (DImode, op2); + rtx op2_hi = gen_highpart (DImode, op2); + rtx pti_lo = gen_lowpart (DImode, pti_reg); + rtx pti_hi = gen_highpart (DImode, pti_reg); + + emit_insn (gen_rtx_CLOBBER (VOIDmode, op0)); + if (WORDS_BIG_ENDIAN) + { + emit_move_insn (pti_hi, op2_hi); + emit_move_insn (pti_lo, op2_lo); + } + else + { + emit_move_insn (pti_hi, op2_lo); + emit_move_insn (pti_lo, op2_hi); + } + } + + emit_insn (gen_store_conditionalpti (op0, pti_mem, pti_reg)); + DONE; +}) + +(define_insn "store_conditionalpti" + [(set (match_operand:CC 0 "cc_reg_operand" "=x") + (unspec_volatile:CC [(const_int 0)] UNSPECV_SC)) + (set (match_operand:PTI 1 "indexed_or_indirect_operand" "=Z") + (match_operand:PTI 2 "quad_int_reg_operand" "r"))] + "TARGET_SYNC_TI && quad_int_reg_operand (operands[2], PTImode)" + "stqcx. %2,%y1" + [(set_attr "type" "store_c")]) + (define_expand "atomic_compare_and_swap" - [(match_operand:SI 0 "gpc_reg_operand" "") ;; bool out - (match_operand:INT1 1 "gpc_reg_operand" "") ;; val out - (match_operand:INT1 2 "memory_operand" "") ;; memory - (match_operand:INT1 3 "reg_or_short_operand" "") ;; expected - (match_operand:INT1 4 "gpc_reg_operand" "") ;; desired + [(match_operand:SI 0 "int_reg_operand" "") ;; bool out + (match_operand:AINT 1 "int_reg_operand" "") ;; val out + (match_operand:AINT 2 "memory_operand" "") ;; memory + (match_operand:AINT 3 "reg_or_short_operand" "") ;; expected + (match_operand:AINT 4 "int_reg_operand" "") ;; desired (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; model succ (match_operand:SI 7 "const_int_operand" "")] ;; model fail @@ -209,9 +468,9 @@ }) (define_expand "atomic_exchange" - [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "") ;; memory - (match_operand:INT1 2 "gpc_reg_operand" "") ;; input + [(match_operand:AINT 0 "int_reg_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "") ;; memory + (match_operand:AINT 2 "int_reg_operand" "") ;; input (match_operand:SI 3 "const_int_operand" "")] ;; model "" { @@ -220,9 +479,9 @@ }) (define_expand "atomic_" - [(match_operand:INT1 0 "memory_operand" "") ;; memory - (FETCHOP:INT1 (match_dup 0) - (match_operand:INT1 1 "" "")) ;; operand + [(match_operand:AINT 0 "memory_operand" "") ;; memory + (FETCHOP:AINT (match_dup 0) + (match_operand:AINT 1 "" "")) ;; operand (match_operand:SI 2 "const_int_operand" "")] ;; model "" { @@ -232,8 +491,8 @@ }) (define_expand "atomic_nand" - [(match_operand:INT1 0 "memory_operand" "") ;; memory - (match_operand:INT1 1 "gpc_reg_operand" "") ;; operand + [(match_operand:AINT 0 "memory_operand" "") ;; memory + (match_operand:AINT 1 "int_reg_operand" "") ;; operand (match_operand:SI 2 "const_int_operand" "")] ;; model "" { @@ -243,10 +502,10 @@ }) (define_expand "atomic_fetch_" - [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "") ;; memory - (FETCHOP:INT1 (match_dup 1) - (match_operand:INT1 2 "" "")) ;; operand + [(match_operand:AINT 0 "int_reg_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "") ;; memory + (FETCHOP:AINT (match_dup 1) + (match_operand:AINT 2 "" "")) ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model "" { @@ -256,9 +515,9 @@ }) (define_expand "atomic_fetch_nand" - [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "") ;; memory - (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand + [(match_operand:AINT 0 "int_reg_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "") ;; memory + (match_operand:AINT 2 "int_reg_operand" "") ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model "" { @@ -268,10 +527,10 @@ }) (define_expand "atomic__fetch" - [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "") ;; memory - (FETCHOP:INT1 (match_dup 1) - (match_operand:INT1 2 "" "")) ;; operand + [(match_operand:AINT 0 "int_reg_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "") ;; memory + (FETCHOP:AINT (match_dup 1) + (match_operand:AINT 2 "" "")) ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model "" { @@ -281,9 +540,9 @@ }) (define_expand "atomic_nand_fetch" - [(match_operand:INT1 0 "gpc_reg_operand" "") ;; output - (match_operand:INT1 1 "memory_operand" "") ;; memory - (match_operand:INT1 2 "gpc_reg_operand" "") ;; operand + [(match_operand:AINT 0 "int_reg_operand" "") ;; output + (match_operand:AINT 1 "memory_operand" "") ;; memory + (match_operand:AINT 2 "int_reg_operand" "") ;; operand (match_operand:SI 3 "const_int_operand" "")] ;; model "" { diff --git a/gcc-4.8/gcc/config/rs6000/sysv4.h b/gcc-4.8/gcc/config/rs6000/sysv4.h index fabc22c8c..965751b4f 100644 --- a/gcc-4.8/gcc/config/rs6000/sysv4.h +++ b/gcc-4.8/gcc/config/rs6000/sysv4.h @@ -45,7 +45,7 @@ & (OPTION_MASK_RELOCATABLE \ | OPTION_MASK_MINIMAL_TOC)) \ && flag_pic > 1) \ - || DEFAULT_ABI == ABI_AIX) + || DEFAULT_ABI != ABI_V4) #define TARGET_BITFIELD_TYPE (! TARGET_NO_BITFIELD_TYPE) #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) @@ -147,7 +147,7 @@ do { \ rs6000_sdata_name); \ } \ \ - else if (flag_pic && DEFAULT_ABI != ABI_AIX \ + else if (flag_pic && DEFAULT_ABI == ABI_V4 \ && (rs6000_sdata == SDATA_EABI \ || rs6000_sdata == SDATA_SYSV)) \ { \ @@ -173,14 +173,14 @@ do { \ error ("-mrelocatable and -mno-minimal-toc are incompatible"); \ } \ \ - if (TARGET_RELOCATABLE && rs6000_current_abi == ABI_AIX) \ + if (TARGET_RELOCATABLE && rs6000_current_abi != ABI_V4) \ { \ rs6000_isa_flags &= ~OPTION_MASK_RELOCATABLE; \ error ("-mrelocatable and -mcall-%s are incompatible", \ rs6000_abi_name); \ } \ \ - if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi == ABI_AIX) \ + if (!TARGET_64BIT && flag_pic > 1 && rs6000_current_abi != ABI_V4) \ { \ flag_pic = 0; \ error ("-fPIC and -mcall-%s are incompatible", \ @@ -193,7 +193,7 @@ do { \ } \ \ /* Treat -fPIC the same as -mrelocatable. */ \ - if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \ + if (flag_pic > 1 && DEFAULT_ABI == ABI_V4) \ { \ rs6000_isa_flags |= OPTION_MASK_RELOCATABLE | OPTION_MASK_MINIMAL_TOC; \ TARGET_NO_FP_IN_TOC = 1; \ @@ -317,7 +317,7 @@ do { \ /* Put PC relative got entries in .got2. */ #define MINIMAL_TOC_SECTION_ASM_OP \ - (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI != ABI_AIX) \ + (TARGET_RELOCATABLE || (flag_pic && DEFAULT_ABI == ABI_V4) \ ? "\t.section\t\".got2\",\"aw\"" : "\t.section\t\".got1\",\"aw\"") #define SDATA_SECTION_ASM_OP "\t.section\t\".sdata\",\"aw\"" @@ -522,8 +522,6 @@ extern int fixuplabelno; #define ENDIAN_SELECT(BIG_OPT, LITTLE_OPT, DEFAULT_OPT) \ "%{mlittle|mlittle-endian:" LITTLE_OPT ";" \ "mbig|mbig-endian:" BIG_OPT ";" \ - "mcall-aixdesc|mcall-freebsd|mcall-netbsd|" \ - "mcall-openbsd|mcall-linux:" BIG_OPT ";" \ "mcall-i960-old:" LITTLE_OPT ";" \ ":" DEFAULT_OPT "}" @@ -536,25 +534,12 @@ extern int fixuplabelno; %{memb|msdata=eabi: -memb}" \ ENDIAN_SELECT(" -mbig", " -mlittle", DEFAULT_ASM_ENDIAN) -#define CC1_ENDIAN_BIG_SPEC "" - -#define CC1_ENDIAN_LITTLE_SPEC "\ -%{!mstrict-align: %{!mno-strict-align: \ - %{!mcall-i960-old: \ - -mstrict-align \ - } \ -}}" - -#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_big)" - #ifndef CC1_SECURE_PLT_DEFAULT_SPEC #define CC1_SECURE_PLT_DEFAULT_SPEC "" #endif -/* Pass -G xxx to the compiler and set correct endian mode. */ +/* Pass -G xxx to the compiler. */ #define CC1_SPEC "%{G*} %(cc1_cpu)" \ - ENDIAN_SELECT(" %(cc1_endian_big)", " %(cc1_endian_little)", \ - " %(cc1_endian_default)") \ "%{meabi: %{!mcall-*: -mcall-sysv }} \ %{!meabi: %{!mno-eabi: \ %{mrelocatable: -meabi } \ @@ -912,9 +897,6 @@ ncrtn.o%s" { "link_os_netbsd", LINK_OS_NETBSD_SPEC }, \ { "link_os_openbsd", LINK_OS_OPENBSD_SPEC }, \ { "link_os_default", LINK_OS_DEFAULT_SPEC }, \ - { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \ - { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \ - { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \ { "cc1_secure_plt_default", CC1_SECURE_PLT_DEFAULT_SPEC }, \ { "cpp_os_ads", CPP_OS_ADS_SPEC }, \ { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \ diff --git a/gcc-4.8/gcc/config/rs6000/sysv4le.h b/gcc-4.8/gcc/config/rs6000/sysv4le.h index 3901122a7..28da1c99c 100644 --- a/gcc-4.8/gcc/config/rs6000/sysv4le.h +++ b/gcc-4.8/gcc/config/rs6000/sysv4le.h @@ -22,9 +22,6 @@ #undef TARGET_DEFAULT #define TARGET_DEFAULT MASK_LITTLE_ENDIAN -#undef CC1_ENDIAN_DEFAULT_SPEC -#define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" - #undef DEFAULT_ASM_ENDIAN #define DEFAULT_ASM_ENDIAN " -mlittle" @@ -34,3 +31,7 @@ #undef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS { "mlittle", "mcall-sysv" } + +/* Little-endian PowerPC64 Linux uses the ELF v2 ABI by default. */ +#define LINUX64_DEFAULT_ABI_ELFv2 + diff --git a/gcc-4.8/gcc/config/rs6000/t-linux64 b/gcc-4.8/gcc/config/rs6000/t-linux64 index 9175de2ff..70e928dd7 100644 --- a/gcc-4.8/gcc/config/rs6000/t-linux64 +++ b/gcc-4.8/gcc/config/rs6000/t-linux64 @@ -25,8 +25,8 @@ # it doesn't tell anything about the 32bit libraries on those systems. Set # MULTILIB_OSDIRNAMES according to what is found on the target. -MULTILIB_OPTIONS = m64/m32 -MULTILIB_DIRNAMES = 64 32 -MULTILIB_EXTRA_OPTS = fPIC -MULTILIB_OSDIRNAMES = ../lib64$(call if_multiarch,:powerpc64-linux-gnu) -MULTILIB_OSDIRNAMES += $(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu) +MULTILIB_OPTIONS := m64/m32 +MULTILIB_DIRNAMES := 64 32 +MULTILIB_EXTRA_OPTS := +MULTILIB_OSDIRNAMES := m64=../lib64$(call if_multiarch,:powerpc64-linux-gnu) +MULTILIB_OSDIRNAMES += m32=$(if $(wildcard $(shell echo $(SYSTEM_HEADER_DIR))/../../usr/lib32),../lib32,../lib)$(call if_multiarch,:powerpc-linux-gnu) diff --git a/gcc-4.8/gcc/config/rs6000/t-linux64bele b/gcc-4.8/gcc/config/rs6000/t-linux64bele new file mode 100644 index 000000000..97c1ee6fb --- /dev/null +++ b/gcc-4.8/gcc/config/rs6000/t-linux64bele @@ -0,0 +1,7 @@ +#rs6000/t-linux64end + +MULTILIB_OPTIONS += mlittle +MULTILIB_DIRNAMES += le +MULTILIB_OSDIRNAMES += $(subst =,.mlittle=,$(subst lible32,lib32le,$(subst lible64,lib64le,$(subst lib,lible,$(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES)))))) +MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mlittle%,$(MULTILIB_OSDIRNAMES))) +MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN} diff --git a/gcc-4.8/gcc/config/rs6000/t-linux64le b/gcc-4.8/gcc/config/rs6000/t-linux64le new file mode 100644 index 000000000..0cf38e152 --- /dev/null +++ b/gcc-4.8/gcc/config/rs6000/t-linux64le @@ -0,0 +1,3 @@ +#rs6000/t-linux64le + +MULTILIB_OSDIRNAMES := $(subst -linux,le-linux,$(MULTILIB_OSDIRNAMES)) diff --git a/gcc-4.8/gcc/config/rs6000/t-linux64lebe b/gcc-4.8/gcc/config/rs6000/t-linux64lebe new file mode 100644 index 000000000..2e63bdb9f --- /dev/null +++ b/gcc-4.8/gcc/config/rs6000/t-linux64lebe @@ -0,0 +1,7 @@ +#rs6000/t-linux64leend + +MULTILIB_OPTIONS += mbig +MULTILIB_DIRNAMES += be +MULTILIB_OSDIRNAMES += $(subst =,.mbig=,$(subst libbe32,lib32be,$(subst libbe64,lib64be,$(subst lib,libbe,$(subst le-linux,-linux,$(MULTILIB_OSDIRNAMES)))))) +MULTILIB_OSDIRNAMES += $(subst $(if $(findstring 64,$(target)),m64,m32).,,$(filter $(if $(findstring 64,$(target)),m64,m32).mbig%,$(MULTILIB_OSDIRNAMES))) +MULTILIB_MATCHES := ${MULTILIB_MATCHES_ENDIAN} diff --git a/gcc-4.8/gcc/config/rs6000/t-rs6000 b/gcc-4.8/gcc/config/rs6000/t-rs6000 index 52c183915..81372dfb1 100644 --- a/gcc-4.8/gcc/config/rs6000/t-rs6000 +++ b/gcc-4.8/gcc/config/rs6000/t-rs6000 @@ -60,6 +60,7 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ $(srcdir)/config/rs6000/power5.md \ $(srcdir)/config/rs6000/power6.md \ $(srcdir)/config/rs6000/power7.md \ + $(srcdir)/config/rs6000/power8.md \ $(srcdir)/config/rs6000/cell.md \ $(srcdir)/config/rs6000/xfpu.md \ $(srcdir)/config/rs6000/a2.md \ @@ -70,6 +71,8 @@ MD_INCLUDES = $(srcdir)/config/rs6000/rs64.md \ $(srcdir)/config/rs6000/vector.md \ $(srcdir)/config/rs6000/vsx.md \ $(srcdir)/config/rs6000/altivec.md \ + $(srcdir)/config/rs6000/crypto.md \ + $(srcdir)/config/rs6000/htm.md \ $(srcdir)/config/rs6000/spe.md \ $(srcdir)/config/rs6000/dfp.md \ $(srcdir)/config/rs6000/paired.md diff --git a/gcc-4.8/gcc/config/rs6000/vector.md b/gcc-4.8/gcc/config/rs6000/vector.md index 5a6e1fb30..5c45ec3f9 100644 --- a/gcc-4.8/gcc/config/rs6000/vector.md +++ b/gcc-4.8/gcc/config/rs6000/vector.md @@ -24,28 +24,28 @@ ;; Vector int modes -(define_mode_iterator VEC_I [V16QI V8HI V4SI]) +(define_mode_iterator VEC_I [V16QI V8HI V4SI V2DI]) ;; Vector float modes (define_mode_iterator VEC_F [V4SF V2DF]) ;; Vector arithmetic modes -(define_mode_iterator VEC_A [V16QI V8HI V4SI V4SF V2DF]) +(define_mode_iterator VEC_A [V16QI V8HI V4SI V2DI V4SF V2DF]) ;; Vector modes that need alginment via permutes (define_mode_iterator VEC_K [V16QI V8HI V4SI V4SF]) ;; Vector logical modes -(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF TI]) +(define_mode_iterator VEC_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI]) ;; Vector modes for moves. Don't do TImode here. -(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF]) +(define_mode_iterator VEC_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI]) ;; Vector modes for types that don't need a realignment under VSX -(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF]) +(define_mode_iterator VEC_N [V4SI V4SF V2DI V2DF V1TI]) ;; Vector comparison modes -(define_mode_iterator VEC_C [V16QI V8HI V4SI V4SF V2DF]) +(define_mode_iterator VEC_C [V16QI V8HI V4SI V2DI V4SF V2DF]) ;; Vector init/extract modes (define_mode_iterator VEC_E [V16QI V8HI V4SI V2DI V4SF V2DF]) @@ -54,7 +54,8 @@ (define_mode_iterator VEC_64 [V2DI V2DF]) ;; Vector reload iterator -(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF DF TI]) +(define_mode_iterator VEC_R [V16QI V8HI V4SI V2DI V4SF V2DF V1TI + SF SD SI DF DD DI TI]) ;; Base type from vector mode (define_mode_attr VEC_base [(V16QI "QI") @@ -63,6 +64,7 @@ (V2DI "DI") (V4SF "SF") (V2DF "DF") + (V1TI "TI") (TI "TI")]) ;; Same size integer type for floating point data @@ -88,7 +90,8 @@ (smax "smax")]) -;; Vector move instructions. +;; Vector move instructions. Little-endian VSX loads and stores require +;; special handling to circumvent "element endianness." (define_expand "mov" [(set (match_operand:VEC_M 0 "nonimmediate_operand" "") (match_operand:VEC_M 1 "any_operand" ""))] @@ -104,6 +107,15 @@ && !vlogical_operand (operands[1], mode)) operands[1] = force_reg (mode, operands[1]); } + if (!BYTES_BIG_ENDIAN + && VECTOR_MEM_VSX_P (mode) + && !gpr_or_gpr_p (operands[0], operands[1]) + && (memory_operand (operands[0], mode) + ^ memory_operand (operands[1], mode))) + { + rs6000_emit_le_vsx_move (operands[0], operands[1], mode); + DONE; + } }) ;; Generic vector floating point load/store instructions. These will match @@ -126,7 +138,9 @@ (match_operand:VEC_L 1 "input_operand" ""))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) && reload_completed - && gpr_or_gpr_p (operands[0], operands[1])" + && gpr_or_gpr_p (operands[0], operands[1]) + && !direct_move_p (operands[0], operands[1]) + && !quad_load_store_p (operands[0], operands[1])" [(pc)] { rs6000_split_multireg_move (operands[0], operands[1]); @@ -249,7 +263,7 @@ [(set (match_operand:VEC_F 0 "vfloat_operand" "") (mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "") (match_operand:VEC_F 2 "vfloat_operand" "")))] - "VECTOR_UNIT_VSX_P (mode) || VECTOR_UNIT_ALTIVEC_P (mode)" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" { if (mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (mode)) { @@ -395,7 +409,7 @@ (match_operand:VEC_I 5 "vint_operand" "")]) (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], @@ -451,7 +465,7 @@ (match_operand:VEC_I 5 "vint_operand" "")]) (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" " { if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2], @@ -505,14 +519,14 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") (define_expand "vector_geu" [(set (match_operand:VEC_I 0 "vint_operand" "") (geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "VECTOR_UNIT_ALTIVEC_P (mode)" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") (define_insn_and_split "*vector_uneq" @@ -595,8 +609,8 @@ (ge:VEC_F (match_dup 2) (match_dup 1))) (set (match_dup 0) - (not:VEC_F (ior:VEC_F (match_dup 3) - (match_dup 4))))] + (and:VEC_F (not:VEC_F (match_dup 3)) + (not:VEC_F (match_dup 4))))] " { operands[3] = gen_reg_rtx (mode); @@ -708,47 +722,18 @@ "") -;; Vector logical instructions -(define_expand "xor3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (xor:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:VEC_L 2 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "") - -(define_expand "ior3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:VEC_L 2 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "") - -(define_expand "and3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (and:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:VEC_L 2 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "") +;; Vector count leading zeros +(define_expand "clz2" + [(set (match_operand:VEC_I 0 "register_operand" "") + (clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + "TARGET_P8_VECTOR") -(define_expand "one_cmpl2" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (not:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "") +;; Vector population count +(define_expand "popcount2" + [(set (match_operand:VEC_I 0 "register_operand" "") + (popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))] + "TARGET_P8_VECTOR") -(define_expand "nor3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (not:VEC_L (ior:VEC_L (match_operand:VEC_L 1 "vlogical_operand" "") - (match_operand:VEC_L 2 "vlogical_operand" ""))))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "") - -(define_expand "andc3" - [(set (match_operand:VEC_L 0 "vlogical_operand" "") - (and:VEC_L (not:VEC_L (match_operand:VEC_L 2 "vlogical_operand" "")) - (match_operand:VEC_L 1 "vlogical_operand" "")))] - "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "") ;; Same size conversions (define_expand "float2" @@ -889,7 +874,7 @@ { rtx reg = gen_reg_rtx (V4SFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], true); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_vsx_xvcvspdp (operands[0], reg)); DONE; }) @@ -901,7 +886,7 @@ { rtx reg = gen_reg_rtx (V4SFmode); - rs6000_expand_interleave (reg, operands[1], operands[1], false); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_vsx_xvcvspdp (operands[0], reg)); DONE; }) @@ -913,7 +898,7 @@ { rtx reg = gen_reg_rtx (V4SImode); - rs6000_expand_interleave (reg, operands[1], operands[1], true); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg)); DONE; }) @@ -925,7 +910,7 @@ { rtx reg = gen_reg_rtx (V4SImode); - rs6000_expand_interleave (reg, operands[1], operands[1], false); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_vsx_xvcvsxwdp (operands[0], reg)); DONE; }) @@ -937,7 +922,7 @@ { rtx reg = gen_reg_rtx (V4SImode); - rs6000_expand_interleave (reg, operands[1], operands[1], true); + rs6000_expand_interleave (reg, operands[1], operands[1], BYTES_BIG_ENDIAN); emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg)); DONE; }) @@ -949,7 +934,7 @@ { rtx reg = gen_reg_rtx (V4SImode); - rs6000_expand_interleave (reg, operands[1], operands[1], false); + rs6000_expand_interleave (reg, operands[1], operands[1], !BYTES_BIG_ENDIAN); emit_insn (gen_vsx_xvcvuxwdp (operands[0], reg)); DONE; }) @@ -963,8 +948,19 @@ (match_operand:V16QI 3 "vlogical_operand" "")] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" { - emit_insn (gen_altivec_vperm_ (operands[0], operands[1], operands[2], - operands[3])); + if (BYTES_BIG_ENDIAN) + emit_insn (gen_altivec_vperm_ (operands[0], operands[1], + operands[2], operands[3])); + else + { + /* We have changed lvsr to lvsl, so to complete the transformation + of vperm for LE, we must swap the inputs. */ + rtx unspec = gen_rtx_UNSPEC (mode, + gen_rtvec (3, operands[2], + operands[1], operands[3]), + UNSPEC_VPERM); + emit_move_insn (operands[0], unspec); + } DONE; }) @@ -1064,7 +1060,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Expanders for arithmetic shift left on each vector element @@ -1072,7 +1068,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Expanders for logical shift right on each vector element @@ -1080,7 +1076,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Expanders for arithmetic shift right on each vector element @@ -1088,7 +1084,7 @@ [(set (match_operand:VEC_I 0 "vint_operand" "") (ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "") (match_operand:VEC_I 2 "vint_operand" "")))] - "TARGET_ALTIVEC" + "VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode)" "") ;; Vector reduction expanders for VSX diff --git a/gcc-4.8/gcc/config/rs6000/vsx.md b/gcc-4.8/gcc/config/rs6000/vsx.md index 3fafd9b27..5f5e4a3b8 100644 --- a/gcc-4.8/gcc/config/rs6000/vsx.md +++ b/gcc-4.8/gcc/config/rs6000/vsx.md @@ -34,11 +34,20 @@ (define_mode_iterator VSX_F [V4SF V2DF]) ;; Iterator for logical types supported by VSX -(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF TI]) +(define_mode_iterator VSX_L [V16QI V8HI V4SI V2DI V4SF V2DF V1TI TI]) ;; Iterator for memory move. Handle TImode specially to allow ;; it to use gprs as well as vsx registers. -(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF]) +(define_mode_iterator VSX_M [V16QI V8HI V4SI V2DI V4SF V2DF V1TI]) + +(define_mode_iterator VSX_M2 [V16QI + V8HI + V4SI + V2DI + V4SF + V2DF + V1TI + (TI "TARGET_VSX_TIMODE")]) ;; Map into the appropriate load/store name based on the type (define_mode_attr VSm [(V16QI "vw4") @@ -48,7 +57,8 @@ (V2DF "vd2") (V2DI "vd2") (DF "d") - (TI "vw4")]) + (V1TI "vd2") + (TI "vd2")]) ;; Map into the appropriate suffix based on the type (define_mode_attr VSs [(V16QI "sp") @@ -59,7 +69,8 @@ (V2DI "dp") (DF "dp") (SF "sp") - (TI "sp")]) + (V1TI "dp") + (TI "dp")]) ;; Map the register class used (define_mode_attr VSr [(V16QI "v") @@ -70,7 +81,8 @@ (V2DF "wd") (DF "ws") (SF "d") - (TI "wd")]) + (V1TI "v") + (TI "wt")]) ;; Map the register class used for float<->int conversions (define_mode_attr VSr2 [(V2DF "wd") @@ -115,7 +127,7 @@ (V4SF "v") (V2DI "v") (V2DF "v") - (TI "v") + (V1TI "v") (DF "s")]) ;; Appropriate type for add ops (and other simple FP ops) @@ -173,7 +185,8 @@ (V2DF "vecdouble")]) ;; Map the scalar mode for a vector type -(define_mode_attr VS_scalar [(V2DF "DF") +(define_mode_attr VS_scalar [(V1TI "TI") + (V2DF "DF") (V2DI "DI") (V4SF "SF") (V4SI "SI") @@ -184,7 +197,8 @@ (define_mode_attr VS_double [(V4SI "V8SI") (V4SF "V8SF") (V2DI "V4DI") - (V2DF "V4DF")]) + (V2DF "V4DF") + (V1TI "V2TI")]) ;; Constants for creating unspecs (define_c_enum "unspec" @@ -192,6 +206,8 @@ UNSPEC_VSX_CVDPSXWS UNSPEC_VSX_CVDPUXWS UNSPEC_VSX_CVSPDP + UNSPEC_VSX_CVSPDPN + UNSPEC_VSX_CVDPSPN UNSPEC_VSX_CVSXWDP UNSPEC_VSX_CVUXWDP UNSPEC_VSX_CVSXDSP @@ -204,77 +220,394 @@ UNSPEC_VSX_ROUND_I UNSPEC_VSX_ROUND_IC UNSPEC_VSX_SLDWI + UNSPEC_VSX_XXSPLTW ]) ;; VSX moves -(define_insn "*vsx_mov" - [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,,,?Z,?wa,?wa,*Y,*r,*r,,?wa,*r,v,wZ,v") - (match_operand:VSX_M 1 "input_operand" ",Z,,wa,Z,wa,r,Y,r,j,j,j,W,v,wZ"))] - "VECTOR_MEM_VSX_P (mode) - && (register_operand (operands[0], mode) - || register_operand (operands[1], mode))" + +;; The patterns for LE permuted loads and stores come before the general +;; VSX moves so they match first. +(define_insn_and_split "*vsx_le_perm_load_" + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") + (match_operand:VSX_D 1 "memory_operand" "Z"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + "!BYTES_BIG_ENDIAN && TARGET_VSX" + [(set (match_dup 2) + (vec_select: + (match_dup 1) + (parallel [(const_int 1) (const_int 0)]))) + (set (match_dup 0) + (vec_select: + (match_dup 2) + (parallel [(const_int 1) (const_int 0)])))] + " { - switch (which_alternative) - { - case 0: - case 3: - gcc_assert (MEM_P (operands[0]) - && GET_CODE (XEXP (operands[0], 0)) != PRE_INC - && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC - && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY); - return "stxx %x1,%y0"; + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) + : operands[0]; +} + " + [(set_attr "type" "vecload") + (set_attr "length" "8")]) - case 1: - case 4: - gcc_assert (MEM_P (operands[1]) - && GET_CODE (XEXP (operands[1], 0)) != PRE_INC - && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC - && GET_CODE (XEXP (operands[1], 0)) != PRE_MODIFY); - return "lxx %x0,%y1"; +(define_insn_and_split "*vsx_le_perm_load_" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (match_operand:VSX_W 1 "memory_operand" "Z"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + "!BYTES_BIG_ENDIAN && TARGET_VSX" + [(set (match_dup 2) + (vec_select: + (match_dup 1) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)]))) + (set (match_dup 0) + (vec_select: + (match_dup 2) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)])))] + " +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) + : operands[0]; +} + " + [(set_attr "type" "vecload") + (set_attr "length" "8")]) - case 2: - case 5: - return "xxlor %x0,%x1,%x1"; +(define_insn_and_split "*vsx_le_perm_load_v8hi" + [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") + (match_operand:V8HI 1 "memory_operand" "Z"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + "!BYTES_BIG_ENDIAN && TARGET_VSX" + [(set (match_dup 2) + (vec_select:V8HI + (match_dup 1) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))) + (set (match_dup 0) + (vec_select:V8HI + (match_dup 2) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)])))] + " +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) + : operands[0]; +} + " + [(set_attr "type" "vecload") + (set_attr "length" "8")]) - case 6: - case 7: - case 8: - case 11: - return "#"; +(define_insn_and_split "*vsx_le_perm_load_v16qi" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (match_operand:V16QI 1 "memory_operand" "Z"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + "!BYTES_BIG_ENDIAN && TARGET_VSX" + [(set (match_dup 2) + (vec_select:V16QI + (match_dup 1) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))) + (set (match_dup 0) + (vec_select:V16QI + (match_dup 2) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])))] + " +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[0]) + : operands[0]; +} + " + [(set_attr "type" "vecload") + (set_attr "length" "8")]) - case 9: - case 10: - return "xxlxor %x0,%x0,%x0"; +(define_insn "*vsx_le_perm_store_" + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (match_operand:VSX_D 1 "vsx_register_operand" "+wa"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + [(set_attr "type" "vecstore") + (set_attr "length" "12")]) + +(define_split + [(set (match_operand:VSX_D 0 "memory_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + [(set (match_dup 2) + (vec_select: + (match_dup 1) + (parallel [(const_int 1) (const_int 0)]))) + (set (match_dup 0) + (vec_select: + (match_dup 2) + (parallel [(const_int 1) (const_int 0)])))] +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) + : operands[1]; +}) - case 12: - return output_vec_const_move (operands); +;; The post-reload split requires that we re-permute the source +;; register in case it is still live. +(define_split + [(set (match_operand:VSX_D 0 "memory_operand" "") + (match_operand:VSX_D 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + [(set (match_dup 1) + (vec_select: + (match_dup 1) + (parallel [(const_int 1) (const_int 0)]))) + (set (match_dup 0) + (vec_select: + (match_dup 1) + (parallel [(const_int 1) (const_int 0)]))) + (set (match_dup 1) + (vec_select: + (match_dup 1) + (parallel [(const_int 1) (const_int 0)])))] + "") - case 13: - gcc_assert (MEM_P (operands[0]) - && GET_CODE (XEXP (operands[0], 0)) != PRE_INC - && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC - && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY); - return "stvx %1,%y0"; +(define_insn "*vsx_le_perm_store_" + [(set (match_operand:VSX_W 0 "memory_operand" "=Z") + (match_operand:VSX_W 1 "vsx_register_operand" "+wa"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + [(set_attr "type" "vecstore") + (set_attr "length" "12")]) + +(define_split + [(set (match_operand:VSX_W 0 "memory_operand" "") + (match_operand:VSX_W 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + [(set (match_dup 2) + (vec_select: + (match_dup 1) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)]))) + (set (match_dup 0) + (vec_select: + (match_dup 2) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)])))] +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) + : operands[1]; +}) - case 14: - gcc_assert (MEM_P (operands[0]) - && GET_CODE (XEXP (operands[0], 0)) != PRE_INC - && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC - && GET_CODE (XEXP (operands[0], 0)) != PRE_MODIFY); - return "lvx %0,%y1"; +;; The post-reload split requires that we re-permute the source +;; register in case it is still live. +(define_split + [(set (match_operand:VSX_W 0 "memory_operand" "") + (match_operand:VSX_W 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + [(set (match_dup 1) + (vec_select: + (match_dup 1) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)]))) + (set (match_dup 0) + (vec_select: + (match_dup 1) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)]))) + (set (match_dup 1) + (vec_select: + (match_dup 1) + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)])))] + "") - default: - gcc_unreachable (); - } +(define_insn "*vsx_le_perm_store_v8hi" + [(set (match_operand:V8HI 0 "memory_operand" "=Z") + (match_operand:V8HI 1 "vsx_register_operand" "+wa"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + [(set_attr "type" "vecstore") + (set_attr "length" "12")]) + +(define_split + [(set (match_operand:V8HI 0 "memory_operand" "") + (match_operand:V8HI 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + [(set (match_dup 2) + (vec_select:V8HI + (match_dup 1) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))) + (set (match_dup 0) + (vec_select:V8HI + (match_dup 2) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)])))] +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) + : operands[1]; +}) + +;; The post-reload split requires that we re-permute the source +;; register in case it is still live. +(define_split + [(set (match_operand:V8HI 0 "memory_operand" "") + (match_operand:V8HI 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + [(set (match_dup 1) + (vec_select:V8HI + (match_dup 1) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))) + (set (match_dup 0) + (vec_select:V8HI + (match_dup 1) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))) + (set (match_dup 1) + (vec_select:V8HI + (match_dup 1) + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)])))] + "") + +(define_insn "*vsx_le_perm_store_v16qi" + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (match_operand:V16QI 1 "vsx_register_operand" "+wa"))] + "!BYTES_BIG_ENDIAN && TARGET_VSX" + "#" + [(set_attr "type" "vecstore") + (set_attr "length" "12")]) + +(define_split + [(set (match_operand:V16QI 0 "memory_operand" "") + (match_operand:V16QI 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed" + [(set (match_dup 2) + (vec_select:V16QI + (match_dup 1) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))) + (set (match_dup 0) + (vec_select:V16QI + (match_dup 2) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])))] +{ + operands[2] = can_create_pseudo_p () ? gen_reg_rtx_and_attrs (operands[1]) + : operands[1]; +}) + +;; The post-reload split requires that we re-permute the source +;; register in case it is still live. +(define_split + [(set (match_operand:V16QI 0 "memory_operand" "") + (match_operand:V16QI 1 "vsx_register_operand" ""))] + "!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed" + [(set (match_dup 1) + (vec_select:V16QI + (match_dup 1) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))) + (set (match_dup 0) + (vec_select:V16QI + (match_dup 1) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))) + (set (match_dup 1) + (vec_select:V16QI + (match_dup 1) + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])))] + "") + + +(define_insn "*vsx_mov" + [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=Z,,,?Z,?wa,?wa,wQ,?&r,??Y,??r,??r,,?wa,*r,v,wZ, v") + (match_operand:VSX_M 1 "input_operand" ",Z,,wa,Z,wa,r,wQ,r,Y,r,j,j,j,W,v,wZ"))] + "VECTOR_MEM_VSX_P (mode) + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" +{ + return rs6000_output_move_128bit (operands); } - [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,*,*,*,vecsimple,vecsimple,*,*,vecstore,vecload")]) - -;; Unlike other VSX moves, allow the GPRs, since a normal use of TImode is for -;; unions. However for plain data movement, slightly favor the vector loads -(define_insn "*vsx_movti" - [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,?Y,?r,?r,wa,v,v,wZ") - (match_operand:TI 1 "input_operand" "wa,Z,wa,r,Y,r,j,W,wZ,v"))] - "VECTOR_MEM_VSX_P (TImode) + [(set_attr "type" "vecstore,vecload,vecsimple,vecstore,vecload,vecsimple,load,store,store,load, *,vecsimple,vecsimple,*, *,vecstore,vecload") + (set_attr "length" "4,4,4,4,4,4,12,12,12,12,16,4,4,*,16,4,4")]) + +;; Unlike other VSX moves, allow the GPRs even for reloading, since a normal +;; use of TImode is for unions. However for plain data movement, slightly +;; favor the vector loads +(define_insn "*vsx_movti_64bit" + [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v,v,wZ,wQ,&r,Y,r,r,?r") + (match_operand:TI 1 "input_operand" "wa,Z,wa,O,W,wZ,v,r,wQ,r,Y,r,n"))] + "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode) + && (register_operand (operands[0], TImode) + || register_operand (operands[1], TImode))" +{ + return rs6000_output_move_128bit (operands); +} + [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store,load,store,load,*,*") + (set_attr "length" "4,4,4,4,16,4,4,8,8,8,8,8,8")]) + +(define_insn "*vsx_movti_32bit" + [(set (match_operand:TI 0 "nonimmediate_operand" "=Z,wa,wa,wa,v, v,wZ,Q,Y,????r,????r,????r,r") + (match_operand:TI 1 "input_operand" "wa, Z,wa, O,W,wZ, v,r,r, Q, Y, r,n"))] + "! TARGET_POWERPC64 && VECTOR_MEM_VSX_P (TImode) && (register_operand (operands[0], TImode) || register_operand (operands[1], TImode))" { @@ -290,27 +623,45 @@ return "xxlor %x0,%x1,%x1"; case 3: + return "xxlxor %x0,%x0,%x0"; + case 4: + return output_vec_const_move (operands); + case 5: - return "#"; + return "stvx %1,%y0"; case 6: - return "xxlxor %x0,%x0,%x0"; + return "lvx %0,%y1"; case 7: - return output_vec_const_move (operands); + if (TARGET_STRING) + return \"stswi %1,%P0,16\"; case 8: - return "stvx %1,%y0"; + return \"#\"; case 9: - return "lvx %0,%y1"; + /* If the address is not used in the output, we can use lsi. Otherwise, + fall through to generating four loads. */ + if (TARGET_STRING + && ! reg_overlap_mentioned_p (operands[0], operands[1])) + return \"lswi %0,%P1,16\"; + /* ... fall through ... */ + case 10: + case 11: + case 12: + return \"#\"; default: gcc_unreachable (); } } - [(set_attr "type" "vecstore,vecload,vecsimple,*,*,*,vecsimple,*,vecstore,vecload")]) + [(set_attr "type" "vecstore,vecload,vecsimple,vecsimple,vecsimple,vecstore,vecload,store_ux,store_ux,load_ux,load_ux, *, *") + (set_attr "length" " 4, 4, 4, 4, 8, 4, 4, 16, 16, 16, 16,16,16") + (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") + (const_string "always") + (const_string "conditional")))]) ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_" @@ -320,46 +671,48 @@ "") (define_expand "vsx_store_" - [(set (match_operand:VEC_M 0 "memory_operand" "") - (match_operand:VEC_M 1 "vsx_register_operand" ""))] + [(set (match_operand:VSX_M 0 "memory_operand" "") + (match_operand:VSX_M 1 "vsx_register_operand" ""))] "VECTOR_MEM_VSX_P (mode)" "") -;; VSX scalar and vector floating point arithmetic instructions +;; VSX vector floating point arithmetic instructions. The VSX scalar +;; instructions are now combined with the insn for the traditional floating +;; point unit. (define_insn "*vsx_add3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (plus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (plus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xadd %x0,%x1,%x2" + "xvadd %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_sub3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (minus:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (minus:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xsub %x0,%x1,%x2" + "xvsub %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_mul3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (mult:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (mult:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xmul %x0,%x1,%x2" - [(set_attr "type" "") + "xvmul %x0,%x1,%x2" + [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_div3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (div:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (div:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xdiv %x0,%x1,%x2" + "xvdiv %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) @@ -402,94 +755,72 @@ (set_attr "fp_type" "")]) (define_insn "vsx_fre2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] UNSPEC_FRES))] "VECTOR_UNIT_VSX_P (mode)" - "xre %x0,%x1" + "xvre %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_neg2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (neg:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (neg:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xneg %x0,%x1" + "xvneg %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_abs2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (abs:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (abs:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xabs %x0,%x1" + "xvabs %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_nabs2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (neg:VSX_B - (abs:VSX_B - (match_operand:VSX_B 1 "vsx_register_operand" ",wa"))))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (neg:VSX_F + (abs:VSX_F + (match_operand:VSX_F 1 "vsx_register_operand" ",wa"))))] "VECTOR_UNIT_VSX_P (mode)" - "xnabs %x0,%x1" + "xvnabs %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_smax3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (smax:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (smax:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xmax %x0,%x1,%x2" + "xvmax %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_smin3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (smin:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (smin:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xmin %x0,%x1,%x2" + "xvmin %x0,%x1,%x2" [(set_attr "type" "") (set_attr "fp_type" "")]) -;; Special VSX version of smin/smax for single precision floating point. Since -;; both numbers are rounded to single precision, we can just use the DP version -;; of the instruction. - -(define_insn "*vsx_smaxsf3" - [(set (match_operand:SF 0 "vsx_register_operand" "=f") - (smax:SF (match_operand:SF 1 "vsx_register_operand" "f") - (match_operand:SF 2 "vsx_register_operand" "f")))] - "VECTOR_UNIT_VSX_P (DFmode)" - "xsmaxdp %x0,%x1,%x2" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_addsub_d")]) - -(define_insn "*vsx_sminsf3" - [(set (match_operand:SF 0 "vsx_register_operand" "=f") - (smin:SF (match_operand:SF 1 "vsx_register_operand" "f") - (match_operand:SF 2 "vsx_register_operand" "f")))] - "VECTOR_UNIT_VSX_P (DFmode)" - "xsmindp %x0,%x1,%x2" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_addsub_d")]) - (define_insn "*vsx_sqrt2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (sqrt:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (sqrt:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xsqrt %x0,%x1" + "xvsqrt %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "*vsx_rsqrte2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] UNSPEC_RSQRT))] "VECTOR_UNIT_VSX_P (mode)" - "xrsqrte %x0,%x1" + "xvrsqrte %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) @@ -528,26 +859,10 @@ [(set_attr "type" "") (set_attr "fp_type" "")]) -;; Fused vector multiply/add instructions Support the classical DF versions of -;; fma, which allows the target to be a separate register from the 3 inputs. -;; Under VSX, the target must be either the addend or the first multiply. -;; Where we can, also do the same for the Altivec V4SF fmas. - -(define_insn "*vsx_fmadf4" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d") - (fma:DF - (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d") - (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d") - (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))] - "VECTOR_UNIT_VSX_P (DFmode)" - "@ - xsmaddadp %x0,%x1,%x2 - xsmaddmdp %x0,%x1,%x3 - xsmaddadp %x0,%x1,%x2 - xsmaddmdp %x0,%x1,%x3 - fmadd %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) +;; Fused vector multiply/add instructions. Support the classical Altivec +;; versions of fma, which allows the target to be a separate register from the +;; 3 inputs. Under VSX, the target must be either the addend or the first +;; multiply. (define_insn "*vsx_fmav4sf4" [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,v") @@ -578,23 +893,6 @@ xvmaddmdp %x0,%x1,%x3" [(set_attr "type" "vecdouble")]) -(define_insn "*vsx_fmsdf4" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d") - (fma:DF - (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d") - (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d") - (neg:DF - (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))] - "VECTOR_UNIT_VSX_P (DFmode)" - "@ - xsmsubadp %x0,%x1,%x2 - xsmsubmdp %x0,%x1,%x3 - xsmsubadp %x0,%x1,%x2 - xsmsubmdp %x0,%x1,%x3 - fmsub %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - (define_insn "*vsx_fms4" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,,?wa,?wa") (fma:VSX_F @@ -604,29 +902,12 @@ (match_operand:VSX_F 3 "vsx_register_operand" "0,,0,wa"))))] "VECTOR_UNIT_VSX_P (mode)" "@ - xmsuba %x0,%x1,%x2 - xmsubm %x0,%x1,%x3 - xmsuba %x0,%x1,%x2 - xmsubm %x0,%x1,%x3" + xvmsuba %x0,%x1,%x2 + xvmsubm %x0,%x1,%x3 + xvmsuba %x0,%x1,%x2 + xvmsubm %x0,%x1,%x3" [(set_attr "type" "")]) -(define_insn "*vsx_nfmadf4" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d") - (neg:DF - (fma:DF - (match_operand:DF 1 "vsx_register_operand" "ws,ws,wa,wa,d") - (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d") - (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d"))))] - "VECTOR_UNIT_VSX_P (DFmode)" - "@ - xsnmaddadp %x0,%x1,%x2 - xsnmaddmdp %x0,%x1,%x3 - xsnmaddadp %x0,%x1,%x2 - xsnmaddmdp %x0,%x1,%x3 - fnmadd %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - (define_insn "*vsx_nfma4" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,,?wa,?wa") (neg:VSX_F @@ -636,31 +917,13 @@ (match_operand:VSX_F 3 "vsx_register_operand" "0,,0,wa"))))] "VECTOR_UNIT_VSX_P (mode)" "@ - xnmadda %x0,%x1,%x2 - xnmaddm %x0,%x1,%x3 - xnmadda %x0,%x1,%x2 - xnmaddm %x0,%x1,%x3" + xvnmadda %x0,%x1,%x2 + xvnmaddm %x0,%x1,%x3 + xvnmadda %x0,%x1,%x2 + xvnmaddm %x0,%x1,%x3" [(set_attr "type" "") (set_attr "fp_type" "")]) -(define_insn "*vsx_nfmsdf4" - [(set (match_operand:DF 0 "vsx_register_operand" "=ws,ws,?wa,?wa,d") - (neg:DF - (fma:DF - (match_operand:DF 1 "vsx_register_operand" "%ws,ws,wa,wa,d") - (match_operand:DF 2 "vsx_register_operand" "ws,0,wa,0,d") - (neg:DF - (match_operand:DF 3 "vsx_register_operand" "0,ws,0,wa,d")))))] - "VECTOR_UNIT_VSX_P (DFmode)" - "@ - xsnmsubadp %x0,%x1,%x2 - xsnmsubmdp %x0,%x1,%x3 - xsnmsubadp %x0,%x1,%x2 - xsnmsubmdp %x0,%x1,%x3 - fnmsub %0,%1,%2,%3" - [(set_attr "type" "fp") - (set_attr "fp_type" "fp_maddsub_d")]) - (define_insn "*vsx_nfmsv4sf4" [(set (match_operand:V4SF 0 "vsx_register_operand" "=wf,wf,?wa,?wa,v") (neg:V4SF @@ -722,16 +985,6 @@ [(set_attr "type" "") (set_attr "fp_type" "")]) -;; Floating point scalar compare -(define_insn "*vsx_cmpdf_internal1" - [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,?y") - (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "ws,wa") - (match_operand:DF 2 "gpc_reg_operand" "ws,wa")))] - "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT - && VECTOR_UNIT_VSX_P (DFmode)" - "xscmpudp %0,%x1,%x2" - [(set_attr "type" "fpcompare")]) - ;; Compare vectors producing a vector result and a predicate, setting CR6 to ;; indicate a combined status (define_insn "*vsx_eq__p" @@ -798,13 +1051,13 @@ ;; Copy sign (define_insn "vsx_copysign3" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B - [(match_operand:VSX_B 1 "vsx_register_operand" ",wa") - (match_operand:VSX_B 2 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (unspec:VSX_F + [(match_operand:VSX_F 1 "vsx_register_operand" ",wa") + (match_operand:VSX_F 2 "vsx_register_operand" ",wa")] UNSPEC_COPYSIGN))] "VECTOR_UNIT_VSX_P (mode)" - "xcpsgn %x0,%x2,%x1" + "xvcpsgn %x0,%x2,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) @@ -865,10 +1118,10 @@ (set_attr "fp_type" "")]) (define_insn "vsx_btrunc2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (fix:VSX_B (match_operand:VSX_B 1 "vsx_register_operand" ",wa")))] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (fix:VSX_F (match_operand:VSX_F 1 "vsx_register_operand" ",wa")))] "VECTOR_UNIT_VSX_P (mode)" - "xriz %x0,%x1" + "xvriz %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) @@ -882,20 +1135,20 @@ (set_attr "fp_type" "")]) (define_insn "vsx_floor2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] UNSPEC_FRIM))] "VECTOR_UNIT_VSX_P (mode)" - "xrim %x0,%x1" + "xvrim %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) (define_insn "vsx_ceil2" - [(set (match_operand:VSX_B 0 "vsx_register_operand" "=,?wa") - (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" ",wa")] + [(set (match_operand:VSX_F 0 "vsx_register_operand" "=,?wa") + (unspec:VSX_F [(match_operand:VSX_F 1 "vsx_register_operand" ",wa")] UNSPEC_FRIP))] "VECTOR_UNIT_VSX_P (mode)" - "xrip %x0,%x1" + "xvrip %x0,%x1" [(set_attr "type" "") (set_attr "fp_type" "")]) @@ -942,6 +1195,40 @@ "xscvspdp %x0,%x1" [(set_attr "type" "fp")]) +;; ISA 2.07 xscvdpspn/xscvspdpn that does not raise an error on signalling NaNs +(define_insn "vsx_xscvdpspn" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=ws,?wa") + (unspec:V4SF [(match_operand:DF 1 "vsx_register_operand" "wd,wa")] + UNSPEC_VSX_CVDPSPN))] + "TARGET_XSCVDPSPN" + "xscvdpspn %x0,%x1" + [(set_attr "type" "fp")]) + +(define_insn "vsx_xscvspdpn" + [(set (match_operand:DF 0 "vsx_register_operand" "=ws,?wa") + (unspec:DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")] + UNSPEC_VSX_CVSPDPN))] + "TARGET_XSCVSPDPN" + "xscvspdpn %x0,%x1" + [(set_attr "type" "fp")]) + +(define_insn "vsx_xscvdpspn_scalar" + [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa") + (unspec:V4SF [(match_operand:SF 1 "vsx_register_operand" "f")] + UNSPEC_VSX_CVDPSPN))] + "TARGET_XSCVDPSPN" + "xscvdpspn %x0,%x1" + [(set_attr "type" "fp")]) + +;; Used by direct move to move a SFmode value from GPR to VSX register +(define_insn "vsx_xscvspdpn_directmove" + [(set (match_operand:SF 0 "vsx_register_operand" "=wa") + (unspec:SF [(match_operand:SF 1 "vsx_register_operand" "wa")] + UNSPEC_VSX_CVSPDPN))] + "TARGET_XSCVSPDPN" + "xscvspdpn %x0,%x1" + [(set_attr "type" "fp")]) + ;; Convert from 64-bit to 32-bit types ;; Note, favor the Altivec registers since the usual use of these instructions ;; is in vector converts and we need to use the Altivec vperm instruction. @@ -1026,74 +1313,22 @@ [(set_attr "type" "") (set_attr "fp_type" "")]) - -;; Logical and permute operations -(define_insn "*vsx_and3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (and:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_L 2 "vsx_register_operand" ",?wa")))] - "VECTOR_MEM_VSX_P (mode)" - "xxland %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*vsx_ior3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L (match_operand:VSX_L 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_L 2 "vsx_register_operand" ",?wa")))] - "VECTOR_MEM_VSX_P (mode)" - "xxlor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*vsx_xor3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (xor:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_L 2 "vsx_register_operand" ",?wa")))] - "VECTOR_MEM_VSX_P (mode)" - "xxlxor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*vsx_one_cmpl2" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (not:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",?wa")))] - "VECTOR_MEM_VSX_P (mode)" - "xxlnor %x0,%x1,%x1" - [(set_attr "type" "vecsimple")]) - -(define_insn "*vsx_nor3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (not:VSX_L - (ior:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",?wa") - (match_operand:VSX_L 2 "vsx_register_operand" ",?wa"))))] - "VECTOR_MEM_VSX_P (mode)" - "xxlnor %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - -(define_insn "*vsx_andc3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (and:VSX_L - (not:VSX_L - (match_operand:VSX_L 2 "vsx_register_operand" ",?wa")) - (match_operand:VSX_L 1 "vsx_register_operand" ",?wa")))] - "VECTOR_MEM_VSX_P (mode)" - "xxlandc %x0,%x1,%x2" - [(set_attr "type" "vecsimple")]) - ;; Permute operations ;; Build a V2DF/V2DI vector from two scalars (define_insn "vsx_concat_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa") - (unspec:VSX_D - [(match_operand: 1 "vsx_register_operand" "ws,wa") - (match_operand: 2 "vsx_register_operand" "ws,wa")] - UNSPEC_VSX_CONCAT))] + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=,?wa") + (vec_concat:VSX_D + (match_operand: 1 "vsx_register_operand" "ws,wa") + (match_operand: 2 "vsx_register_operand" "ws,wa")))] "VECTOR_MEM_VSX_P (mode)" - "xxpermdi %x0,%x1,%x2,0" +{ + if (BYTES_BIG_ENDIAN) + return "xxpermdi %x0,%x1,%x2,0"; + else + return "xxpermdi %x0,%x2,%x1,0"; +} [(set_attr "type" "vecperm")]) ;; Special purpose concat using xxpermdi to glue two single precision values @@ -1106,9 +1341,176 @@ (match_operand:SF 2 "vsx_register_operand" "f,f")] UNSPEC_VSX_CONCAT))] "VECTOR_MEM_VSX_P (V2DFmode)" - "xxpermdi %x0,%x1,%x2,0" +{ + if (BYTES_BIG_ENDIAN) + return "xxpermdi %x0,%x1,%x2,0"; + else + return "xxpermdi %x0,%x2,%x1,0"; +} + [(set_attr "type" "vecperm")]) + +;; xxpermdi for little endian loads and stores. We need several of +;; these since the form of the PARALLEL differs by mode. +(define_insn "*vsx_xxpermdi2_le_" + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") + (vec_select:VSX_D + (match_operand:VSX_D 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 0)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" + "xxpermdi %x0,%x1,%x1,2" + [(set_attr "type" "vecperm")]) + +(define_insn "*vsx_xxpermdi4_le_" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (vec_select:VSX_W + (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" + "xxpermdi %x0,%x1,%x1,2" [(set_attr "type" "vecperm")]) +(define_insn "*vsx_xxpermdi8_le_V8HI" + [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") + (vec_select:V8HI + (match_operand:V8HI 1 "vsx_register_operand" "wa") + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)" + "xxpermdi %x0,%x1,%x1,2" + [(set_attr "type" "vecperm")]) + +(define_insn "*vsx_xxpermdi16_le_V16QI" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (vec_select:V16QI + (match_operand:V16QI 1 "vsx_register_operand" "wa") + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)" + "xxpermdi %x0,%x1,%x1,2" + [(set_attr "type" "vecperm")]) + +;; lxvd2x for little endian loads. We need several of +;; these since the form of the PARALLEL differs by mode. +(define_insn "*vsx_lxvd2x2_le_" + [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa") + (vec_select:VSX_D + (match_operand:VSX_D 1 "memory_operand" "Z") + (parallel [(const_int 1) (const_int 0)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" + "lxvd2x %x0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "*vsx_lxvd2x4_le_" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa") + (vec_select:VSX_W + (match_operand:VSX_W 1 "memory_operand" "Z") + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" + "lxvd2x %x0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "*vsx_lxvd2x8_le_V8HI" + [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa") + (vec_select:V8HI + (match_operand:V8HI 1 "memory_operand" "Z") + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)" + "lxvd2x %x0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "*vsx_lxvd2x16_le_V16QI" + [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") + (vec_select:V16QI + (match_operand:V16QI 1 "memory_operand" "Z") + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)" + "lxvd2x %x0,%y1" + [(set_attr "type" "vecload")]) + +;; stxvd2x for little endian stores. We need several of +;; these since the form of the PARALLEL differs by mode. +(define_insn "*vsx_stxvd2x2_le_" + [(set (match_operand:VSX_D 0 "memory_operand" "=Z") + (vec_select:VSX_D + (match_operand:VSX_D 1 "vsx_register_operand" "wa") + (parallel [(const_int 1) (const_int 0)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" + "stxvd2x %x1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "*vsx_stxvd2x4_le_" + [(set (match_operand:VSX_W 0 "memory_operand" "=Z") + (vec_select:VSX_W + (match_operand:VSX_W 1 "vsx_register_operand" "wa") + (parallel [(const_int 2) (const_int 3) + (const_int 0) (const_int 1)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (mode)" + "stxvd2x %x1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "*vsx_stxvd2x8_le_V8HI" + [(set (match_operand:V8HI 0 "memory_operand" "=Z") + (vec_select:V8HI + (match_operand:V8HI 1 "vsx_register_operand" "wa") + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V8HImode)" + "stxvd2x %x1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "*vsx_stxvd2x16_le_V16QI" + [(set (match_operand:V16QI 0 "memory_operand" "=Z") + (vec_select:V16QI + (match_operand:V16QI 1 "vsx_register_operand" "wa") + (parallel [(const_int 8) (const_int 9) + (const_int 10) (const_int 11) + (const_int 12) (const_int 13) + (const_int 14) (const_int 15) + (const_int 0) (const_int 1) + (const_int 2) (const_int 3) + (const_int 4) (const_int 5) + (const_int 6) (const_int 7)])))] + "!BYTES_BIG_ENDIAN && VECTOR_MEM_VSX_P (V16QImode)" + "stxvd2x %x1,%y0" + [(set_attr "type" "vecstore")]) + +;; Convert a TImode value into V1TImode +(define_expand "vsx_set_v1ti" + [(match_operand:V1TI 0 "nonimmediate_operand" "") + (match_operand:V1TI 1 "nonimmediate_operand" "") + (match_operand:TI 2 "input_operand" "") + (match_operand:QI 3 "u5bit_cint_operand" "")] + "VECTOR_MEM_VSX_P (V1TImode)" +{ + if (operands[3] != const0_rtx) + gcc_unreachable (); + + emit_move_insn (operands[0], gen_lowpart (V1TImode, operands[1])); + DONE; +}) + ;; Set the element of a V2DI/VD2F mode (define_insn "vsx_set_" [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,?wa") @@ -1118,9 +1520,10 @@ UNSPEC_VSX_SET))] "VECTOR_MEM_VSX_P (mode)" { - if (INTVAL (operands[3]) == 0) + int idx_first = BYTES_BIG_ENDIAN ? 0 : 1; + if (INTVAL (operands[3]) == idx_first) return \"xxpermdi %x0,%x2,%x1,1\"; - else if (INTVAL (operands[3]) == 1) + else if (INTVAL (operands[3]) == 1 - idx_first) return \"xxpermdi %x0,%x1,%x2,0\"; else gcc_unreachable (); @@ -1135,8 +1538,12 @@ [(match_operand:QI 2 "u5bit_cint_operand" "i,i,i")])))] "VECTOR_MEM_VSX_P (mode)" { + int fldDM; gcc_assert (UINTVAL (operands[2]) <= 1); - operands[3] = GEN_INT (INTVAL (operands[2]) << 1); + fldDM = INTVAL (operands[2]) << 1; + if (!BYTES_BIG_ENDIAN) + fldDM = 3 - fldDM; + operands[3] = GEN_INT (fldDM); return \"xxpermdi %x0,%x1,%x1,%3\"; } [(set_attr "type" "vecperm")]) @@ -1149,7 +1556,26 @@ (parallel [(const_int 0)])))] "VECTOR_MEM_VSX_P (mode) && WORDS_BIG_ENDIAN" "lxsd%U1x %x0,%y1" - [(set_attr "type" "fpload") + [(set (attr "type") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload"))) + (set_attr "length" "4")]) + +;; Optimize extracting element 1 from memory for little endian +(define_insn "*vsx_extract__one_le" + [(set (match_operand: 0 "vsx_register_operand" "=ws,d,?wa") + (vec_select: + (match_operand:VSX_D 1 "indexed_or_indirect_operand" "Z,Z,Z") + (parallel [(const_int 1)])))] + "VECTOR_MEM_VSX_P (mode) && !WORDS_BIG_ENDIAN" + "lxsd%U1x %x0,%y1" + [(set (attr "type") + (if_then_else + (match_test "update_indexed_address_mem (operands[1], VOIDmode)") + (const_string "fpload_ux") + (const_string "fpload"))) (set_attr "length" "4")]) ;; Extract a SF element from V4SF @@ -1172,7 +1598,7 @@ rtx op2 = operands[2]; rtx op3 = operands[3]; rtx tmp; - HOST_WIDE_INT ele = INTVAL (op2); + HOST_WIDE_INT ele = BYTES_BIG_ENDIAN ? INTVAL (op2) : 3 - INTVAL (op2); if (ele == 0) tmp = op1; @@ -1213,11 +1639,22 @@ if (mode != V2DImode) { target = gen_lowpart (V2DImode, target); - op0 = gen_lowpart (V2DImode, target); - op1 = gen_lowpart (V2DImode, target); + op0 = gen_lowpart (V2DImode, op0); + op1 = gen_lowpart (V2DImode, op1); } } + /* In little endian mode, vsx_xxpermdi2__1 will perform a + transformation we don't want; it is necessary for + rs6000_expand_vec_perm_const_1 but not for this use. So we + prepare for that by reversing the transformation here. */ + if (BYTES_BIG_ENDIAN) emit_insn (gen (target, op0, op1, perm0, perm1)); + else + { + rtx p0 = GEN_INT (3 - INTVAL (perm1)); + rtx p1 = GEN_INT (3 - INTVAL (perm0)); + emit_insn (gen (target, op1, op0, p0, p1)); + } DONE; }) @@ -1231,9 +1668,32 @@ (match_operand 4 "const_2_to_3_operand" "")])))] "VECTOR_MEM_VSX_P (mode)" { - int mask = (INTVAL (operands[3]) << 1) | (INTVAL (operands[4]) - 2); + int op3, op4, mask; + + /* For little endian, swap operands and invert/swap selectors + to get the correct xxpermdi. The operand swap sets up the + inputs as a little endian array. The selectors are swapped + because they are defined to use big endian ordering. The + selectors are inverted to get the correct doublewords for + little endian ordering. */ + if (BYTES_BIG_ENDIAN) + { + op3 = INTVAL (operands[3]); + op4 = INTVAL (operands[4]); + } + else + { + op3 = 3 - INTVAL (operands[4]); + op4 = 3 - INTVAL (operands[3]); + } + + mask = (op3 << 1) | (op4 - 2); operands[3] = GEN_INT (mask); + + if (BYTES_BIG_ENDIAN) return "xxpermdi %x0,%x1,%x2,%3"; + else + return "xxpermdi %x0,%x2,%x1,%3"; } [(set_attr "type" "vecperm")]) @@ -1252,24 +1712,56 @@ ;; Expanders for builtins (define_expand "vsx_mergel_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "") - (vec_select:VSX_D - (vec_concat: - (match_operand:VSX_D 1 "vsx_register_operand" "") - (match_operand:VSX_D 2 "vsx_register_operand" "")) - (parallel [(const_int 1) (const_int 3)])))] + [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) + (use (match_operand:VSX_D 1 "vsx_register_operand" "")) + (use (match_operand:VSX_D 2 "vsx_register_operand" ""))] "VECTOR_MEM_VSX_P (mode)" - "") +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (2, GEN_INT (0), GEN_INT (2)); + x = gen_rtx_VEC_CONCAT (mode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (2, GEN_INT (1), GEN_INT (3)); + x = gen_rtx_VEC_CONCAT (mode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (mode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) (define_expand "vsx_mergeh_" - [(set (match_operand:VSX_D 0 "vsx_register_operand" "") - (vec_select:VSX_D - (vec_concat: - (match_operand:VSX_D 1 "vsx_register_operand" "") - (match_operand:VSX_D 2 "vsx_register_operand" "")) - (parallel [(const_int 0) (const_int 2)])))] + [(use (match_operand:VSX_D 0 "vsx_register_operand" "")) + (use (match_operand:VSX_D 1 "vsx_register_operand" "")) + (use (match_operand:VSX_D 2 "vsx_register_operand" ""))] "VECTOR_MEM_VSX_P (mode)" - "") +{ + rtvec v; + rtx x; + + /* Special handling for LE with -maltivec=be. */ + if (!BYTES_BIG_ENDIAN && VECTOR_ELT_ORDER_BIG) + { + v = gen_rtvec (2, GEN_INT (1), GEN_INT (3)); + x = gen_rtx_VEC_CONCAT (mode, operands[2], operands[1]); + } + else + { + v = gen_rtvec (2, GEN_INT (0), GEN_INT (2)); + x = gen_rtx_VEC_CONCAT (mode, operands[1], operands[2]); + } + + x = gen_rtx_VEC_SELECT (mode, x, gen_rtx_PARALLEL (VOIDmode, v)); + emit_insn (gen_rtx_SET (VOIDmode, operands[0], x)); + DONE; +}) ;; V2DF/V2DI splat (define_insn "vsx_splat_" @@ -1295,6 +1787,20 @@ (parallel [(match_operand:QI 2 "u5bit_cint_operand" "i,i")]))))] "VECTOR_MEM_VSX_P (mode)" +{ + if (!BYTES_BIG_ENDIAN) + operands[2] = GEN_INT (3 - INTVAL (operands[2])); + + return "xxspltw %x0,%x1,%2"; +} + [(set_attr "type" "vecperm")]) + +(define_insn "vsx_xxspltw__direct" + [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wf,?wa") + (unspec:VSX_W [(match_operand:VSX_W 1 "vsx_register_operand" "wf,wa") + (match_operand:QI 2 "u5bit_cint_operand" "i,i")] + UNSPEC_VSX_XXSPLTW))] + "VECTOR_MEM_VSX_P (mode)" "xxspltw %x0,%x1,%2" [(set_attr "type" "vecperm")]) @@ -1308,7 +1814,12 @@ (parallel [(const_int 0) (const_int 4) (const_int 1) (const_int 5)])))] "VECTOR_MEM_VSX_P (mode)" - "xxmrghw %x0,%x1,%x2" +{ + if (BYTES_BIG_ENDIAN) + return "xxmrghw %x0,%x1,%x2"; + else + return "xxmrglw %x0,%x2,%x1"; +} [(set_attr "type" "vecperm")]) (define_insn "vsx_xxmrglw_" @@ -1320,7 +1831,12 @@ (parallel [(const_int 2) (const_int 6) (const_int 3) (const_int 7)])))] "VECTOR_MEM_VSX_P (mode)" - "xxmrglw %x0,%x1,%x2" +{ + if (BYTES_BIG_ENDIAN) + return "xxmrglw %x0,%x1,%x2"; + else + return "xxmrghw %x0,%x2,%x1"; +} [(set_attr "type" "vecperm")]) ;; Shift left double by word immediate @@ -1483,3 +1999,27 @@ }" [(set_attr "length" "20") (set_attr "type" "veccomplex")]) + + +;; Power8 Vector fusion. The fused ops must be physically adjacent. +(define_peephole + [(set (match_operand:P 0 "base_reg_operand" "") + (match_operand:P 1 "short_cint_operand" "")) + (set (match_operand:VSX_M2 2 "vsx_register_operand" "") + (mem:VSX_M2 (plus:P (match_dup 0) + (match_operand:P 3 "int_reg_operand" ""))))] + "TARGET_VSX && TARGET_P8_FUSION" + "li %0,%1\t\t\t# vector load fusion\;lxx %x2,%0,%3" + [(set_attr "length" "8") + (set_attr "type" "vecload")]) + +(define_peephole + [(set (match_operand:P 0 "base_reg_operand" "") + (match_operand:P 1 "short_cint_operand" "")) + (set (match_operand:VSX_M2 2 "vsx_register_operand" "") + (mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "") + (match_dup 0))))] + "TARGET_VSX && TARGET_P8_FUSION" + "li %0,%1\t\t\t# vector load fusion\;lxx %x2,%0,%3" + [(set_attr "length" "8") + (set_attr "type" "vecload")]) diff --git a/gcc-4.8/gcc/config/s390/htmxlintrin.h b/gcc-4.8/gcc/config/s390/htmxlintrin.h index bb142195b..952b40975 100644 --- a/gcc-4.8/gcc/config/s390/htmxlintrin.h +++ b/gcc-4.8/gcc/config/s390/htmxlintrin.h @@ -33,13 +33,20 @@ extern "C" { the IBM XL compiler. For documentation please see the "z/OS XL C/C++ Programming Guide" publically available on the web. */ -extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +/* FIXME: __TM_simple_begin and __TM_begin should be marked + __always_inline__ as well but this currently produces an error + since the tbegin builtins are "returns_twice" and setjmp_call_p + (calls.c) therefore identifies the functions as calling setjmp. + The tree inliner currently refuses to inline functions calling + setjmp. */ + +long __TM_simple_begin () { return __builtin_tbegin_nofloat (0); } -extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) +long __TM_begin (void* const tdb) { return __builtin_tbegin_nofloat (tdb); @@ -78,7 +85,7 @@ __TM_nesting_depth (void* const tdb_ptr) if (depth != 0) return depth; - if (tdb->format == 0) + if (tdb->format != 1) return 0; return tdb->nesting_depth; } @@ -90,7 +97,7 @@ __TM_is_user_abort (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - if (tdb->format == 0) + if (tdb->format != 1) return 0; return !!(tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE); @@ -101,7 +108,7 @@ __TM_is_named_user_abort (void* const tdb_ptr, unsigned char* code) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - if (tdb->format == 0) + if (tdb->format != 1) return 0; if (tdb->abort_code >= _HTM_FIRST_USER_ABORT_CODE) @@ -117,7 +124,7 @@ __TM_is_illegal (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return (tdb->format == 0 + return (tdb->format == 1 && (tdb->abort_code == 4 /* unfiltered program interruption */ || tdb->abort_code == 11 /* restricted instruction */)); } @@ -127,7 +134,7 @@ __TM_is_footprint_exceeded (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return (tdb->format == 0 + return (tdb->format == 1 && (tdb->abort_code == 7 /* fetch overflow */ || tdb->abort_code == 8 /* store overflow */)); } @@ -137,7 +144,7 @@ __TM_is_nested_too_deep (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return tdb->format == 0 && tdb->abort_code == 13; /* depth exceeded */ + return tdb->format == 1 && tdb->abort_code == 13; /* depth exceeded */ } extern __inline long __attribute__((__gnu_inline__, __always_inline__, __artificial__)) @@ -145,7 +152,7 @@ __TM_is_conflict (void* const tdb_ptr) { struct __htm_tdb *tdb = (struct __htm_tdb*)tdb_ptr; - return (tdb->format == 0 + return (tdb->format == 1 && (tdb->abort_code == 9 /* fetch conflict */ || tdb->abort_code == 10 /* store conflict */)); } diff --git a/gcc-4.8/gcc/config/s390/s390-protos.h b/gcc-4.8/gcc/config/s390/s390-protos.h index 67283df45..7b43ed01b 100644 --- a/gcc-4.8/gcc/config/s390/s390-protos.h +++ b/gcc-4.8/gcc/config/s390/s390-protos.h @@ -110,5 +110,6 @@ extern bool s390_decompose_shift_count (rtx, rtx *, HOST_WIDE_INT *); extern int s390_branch_condition_mask (rtx); extern int s390_compare_and_branch_condition_mask (rtx); extern bool s390_extzv_shift_ok (int, int, unsigned HOST_WIDE_INT); +extern void s390_asm_output_function_label (FILE *, const char *, tree); #endif /* RTX_CODE */ diff --git a/gcc-4.8/gcc/config/s390/s390.c b/gcc-4.8/gcc/config/s390/s390.c index 273022778..836a3d4fd 100644 --- a/gcc-4.8/gcc/config/s390/s390.c +++ b/gcc-4.8/gcc/config/s390/s390.c @@ -407,6 +407,65 @@ struct GTY(()) machine_function bytes on a z10 (or higher) CPU. */ #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048) +static const int s390_hotpatch_trampoline_halfwords_default = 12; +static const int s390_hotpatch_trampoline_halfwords_max = 1000000; +static int s390_hotpatch_trampoline_halfwords = -1; + +/* Return the argument of the given hotpatch attribute or the default value if + no argument is present. */ + +static inline int +get_hotpatch_attribute (tree hotpatch_attr) +{ + const_tree args; + + args = TREE_VALUE (hotpatch_attr); + + return (args) ? + TREE_INT_CST_LOW (TREE_VALUE (args)): + s390_hotpatch_trampoline_halfwords_default; +} + +/* Check whether the hotpatch attribute is applied to a function and, if it has + an argument, the argument is valid. */ + +static tree +s390_handle_hotpatch_attribute (tree *node, tree name, tree args, + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) +{ + if (TREE_CODE (*node) != FUNCTION_DECL) + { + warning (OPT_Wattributes, "%qE attribute only applies to functions", + name); + *no_add_attrs = true; + } + else if (args) + { + tree expr = TREE_VALUE (args); + + if (TREE_CODE (expr) != INTEGER_CST + || !INTEGRAL_TYPE_P (TREE_TYPE (expr)) + || TREE_INT_CST_HIGH (expr) != 0 + || TREE_INT_CST_LOW (expr) > (unsigned int) + s390_hotpatch_trampoline_halfwords_max) + { + error ("requested %qE attribute is not a non-negative integer" + " constant or too large (max. %d)", name, + s390_hotpatch_trampoline_halfwords_max); + *no_add_attrs = true; + } + } + + return NULL_TREE; +} + +static const struct attribute_spec s390_attribute_table[] = { + { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false + }, + /* End element. */ + { NULL, 0, 0, false, false, false, NULL, false } +}; + /* Return the alignment for LABEL. We default to the -falign-labels value except for the literal pool base label. */ int @@ -883,7 +942,8 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1, { /* For CCRAWmode put the required cc mask into the second operand. */ - if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode) + if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode + && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3) *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1))); *op0 = XVECEXP (*op0, 0, 0); *code = new_code; @@ -1594,6 +1654,46 @@ s390_init_machine_status (void) static void s390_option_override (void) { + unsigned int i; + cl_deferred_option *opt; + vec *v = + (vec *) s390_deferred_options; + + if (v) + FOR_EACH_VEC_ELT (*v, i, opt) + { + switch (opt->opt_index) + { + case OPT_mhotpatch: + s390_hotpatch_trampoline_halfwords = (opt->value) ? + s390_hotpatch_trampoline_halfwords_default : -1; + break; + case OPT_mhotpatch_: + { + int val; + + val = integral_argument (opt->arg); + if (val == -1) + { + /* argument is not a plain number */ + error ("argument to %qs should be a non-negative integer", + "-mhotpatch="); + break; + } + else if (val > s390_hotpatch_trampoline_halfwords_max) + { + error ("argument to %qs is too large (max. %d)", + "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max); + break; + } + s390_hotpatch_trampoline_halfwords = val; + break; + } + default: + gcc_unreachable (); + } + } + /* Set up function hooks. */ init_machine_status = s390_init_machine_status; @@ -3015,15 +3115,22 @@ s390_preferred_reload_class (rtx op, reg_class_t rclass) prefer ADDR_REGS. If 'class' is not a superset of ADDR_REGS, e.g. FP_REGS, reject this reload. */ case CONST: - /* A larl operand with odd addend will get fixed via secondary - reload. So don't request it to be pushed into literal - pool. */ + /* Symrefs cannot be pushed into the literal pool with -fPIC + so we *MUST NOT* return NO_REGS for these cases + (s390_cannot_force_const_mem will return true). + + On the other hand we MUST return NO_REGS for symrefs with + invalid addend which might have been pushed to the literal + pool (no -fPIC). Usually we would expect them to be + handled via secondary reload but this does not happen if + they are used as literal pool slot replacement in reload + inheritance (see emit_input_reload_insns). */ if (TARGET_CPU_ZARCH && GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT) { - if (reg_class_subset_p (ADDR_REGS, rclass)) + if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass)) return ADDR_REGS; else return NO_REGS; @@ -4683,7 +4790,7 @@ s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) int smode_bsize, mode_bsize; rtx op, clobber; - if (bitsize + bitpos > GET_MODE_SIZE (mode)) + if (bitsize + bitpos > GET_MODE_BITSIZE (mode)) return false; /* Generate INSERT IMMEDIATE (IILL et al). */ @@ -5311,6 +5418,101 @@ get_some_local_dynamic_name (void) gcc_unreachable (); } +/* Returns -1 if the function should not be made hotpatchable. Otherwise it + returns a number >= 0 that is the desired size of the hotpatch trampoline + in halfwords. */ + +static int s390_function_num_hotpatch_trampoline_halfwords (tree decl, + bool do_warn) +{ + tree attr; + + if (DECL_DECLARED_INLINE_P (decl) + || DECL_ARTIFICIAL (decl) + || MAIN_NAME_P (DECL_NAME (decl))) + { + /* - Explicitly inlined functions cannot be hotpatched. + - Artificial functions need not be hotpatched. + - Making the main function hotpatchable is useless. */ + return -1; + } + attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl)); + if (attr || s390_hotpatch_trampoline_halfwords >= 0) + { + if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl))) + { + if (do_warn) + warning (OPT_Wattributes, "function %qE with the %qs attribute" + " is not hotpatchable", DECL_NAME (decl), "always_inline"); + return -1; + } + else + { + return (attr) ? + get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords; + } + } + + return -1; +} + +/* Hook to determine if one function can safely inline another. */ + +static bool +s390_can_inline_p (tree caller, tree callee) +{ + if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0) + return false; + + return default_target_can_inline_p (caller, callee); +} + +/* Write the extra assembler code needed to declare a function properly. */ + +void +s390_asm_output_function_label (FILE *asm_out_file, const char *fname, + tree decl) +{ + int hotpatch_trampoline_halfwords = -1; + + if (decl) + { + hotpatch_trampoline_halfwords = + s390_function_num_hotpatch_trampoline_halfwords (decl, true); + if (hotpatch_trampoline_halfwords >= 0 + && decl_function_context (decl) != NULL_TREE) + { + warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch, + "hotpatching is not compatible with nested functions"); + hotpatch_trampoline_halfwords = -1; + } + } + + if (hotpatch_trampoline_halfwords > 0) + { + int i; + + /* Add a trampoline code area before the function label and initialize it + with two-byte nop instructions. This area can be overwritten with code + that jumps to a patched version of the function. */ + for (i = 0; i < hotpatch_trampoline_halfwords; i++) + asm_fprintf (asm_out_file, "\tnopr\t%%r7\n"); + /* Note: The function label must be aligned so that (a) the bytes of the + following nop do not cross a cacheline boundary, and (b) a jump address + (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be + stored directly before the label without crossing a cacheline + boundary. All this is necessary to make sure the trampoline code can + be changed atomically. */ + } + + ASM_OUTPUT_LABEL (asm_out_file, fname); + + /* Output a four-byte nop if hotpatching is enabled. This can be overwritten + atomically with a relative backwards jump to the trampoline area. */ + if (hotpatch_trampoline_halfwords >= 0) + asm_fprintf (asm_out_file, "\tnop\t0\n"); +} + /* Output machine-dependent UNSPECs occurring in address constant X in assembler syntax to stdio stream FILE. Returns true if the constant X could be recognized, false otherwise. */ @@ -7846,6 +8048,9 @@ s390_optimize_nonescaping_tx (void) { bb = BASIC_BLOCK (bb_index); + if (!bb) + continue; + FOR_BB_INSNS (bb, insn) { rtx ite, cc, pat, target; @@ -7959,7 +8164,10 @@ s390_optimize_nonescaping_tx (void) if (!result) return; - PATTERN (tbegin_insn) = XVECEXP (PATTERN (tbegin_insn), 0, 0); + PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, + XVECEXP (PATTERN (tbegin_insn), 0, 0), + XVECEXP (PATTERN (tbegin_insn), 0, 1))); INSN_CODE (tbegin_insn) = -1; df_insn_rescan (tbegin_insn); @@ -9568,61 +9776,47 @@ s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, void s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) { - const int CC0 = 1 << 3; - const int CC1 = 1 << 2; - const int CC3 = 1 << 0; - rtx abort_label = gen_label_rtx (); - rtx leave_label = gen_label_rtx (); + rtx retry_plus_two = gen_reg_rtx (SImode); rtx retry_reg = gen_reg_rtx (SImode); rtx retry_label = NULL_RTX; - rtx jump; - rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1); if (retry != NULL_RTX) { emit_move_insn (retry_reg, retry); + emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx)); + emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx)); retry_label = gen_label_rtx (); emit_label (retry_label); } if (clobber_fprs_p) - emit_insn (gen_tbegin_1 (tdb, - gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK))); + emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb)); else - emit_insn (gen_tbegin_nofloat_1 (tdb, - gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK))); - - jump = s390_emit_jump (abort_label, - gen_rtx_NE (VOIDmode, - gen_rtx_REG (CCRAWmode, CC_REGNUM), - gen_rtx_CONST_INT (VOIDmode, CC0))); - - JUMP_LABEL (jump) = abort_label; - LABEL_NUSES (abort_label) = 1; - add_reg_note (jump, REG_BR_PROB, very_unlikely); + emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), + tdb)); - /* Initialize CC return value. */ - emit_move_insn (dest, const0_rtx); - - s390_emit_jump (leave_label, NULL_RTX); - LABEL_NUSES (leave_label) = 1; - emit_barrier (); - - /* Abort handler code. */ - - emit_label (abort_label); + emit_move_insn (dest, gen_rtx_UNSPEC (SImode, + gen_rtvec (1, gen_rtx_REG (CCRAWmode, + CC_REGNUM)), + UNSPEC_CC_TO_INT)); if (retry != NULL_RTX) { + const int CC0 = 1 << 3; + const int CC1 = 1 << 2; + const int CC3 = 1 << 0; + rtx jump; rtx count = gen_reg_rtx (SImode); + rtx leave_label = gen_label_rtx (); + + /* Exit for success and permanent failures. */ jump = s390_emit_jump (leave_label, gen_rtx_EQ (VOIDmode, gen_rtx_REG (CCRAWmode, CC_REGNUM), - gen_rtx_CONST_INT (VOIDmode, CC1 | CC3))); - LABEL_NUSES (leave_label) = 2; - add_reg_note (jump, REG_BR_PROB, very_unlikely); + gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3))); + LABEL_NUSES (leave_label) = 1; /* CC2 - transient failure. Perform retry with ppa. */ - emit_move_insn (count, retry); + emit_move_insn (count, retry_plus_two); emit_insn (gen_subsi3 (count, count, retry_reg)); emit_insn (gen_tx_assist (count)); jump = emit_jump_insn (gen_doloop_si64 (retry_label, @@ -9630,13 +9824,8 @@ s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) retry_reg)); JUMP_LABEL (jump) = retry_label; LABEL_NUSES (retry_label) = 1; - } - - emit_move_insn (dest, gen_rtx_UNSPEC (SImode, - gen_rtvec (1, gen_rtx_REG (CCRAWmode, - CC_REGNUM)), - UNSPEC_CC_TO_INT)); emit_label (leave_label); + } } /* Builtins. */ @@ -9674,6 +9863,9 @@ static void s390_init_builtins (void) { tree ftype, uint64_type; + tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"), + NULL, NULL); + tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL); /* void foo (void) */ ftype = build_function_type_list (void_type_node, NULL_TREE); @@ -9684,17 +9876,17 @@ s390_init_builtins (void) ftype = build_function_type_list (void_type_node, integer_type_node, NULL_TREE); add_builtin_function ("__builtin_tabort", ftype, - S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, NULL_TREE); + S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr); add_builtin_function ("__builtin_tx_assist", ftype, S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE); /* int foo (void *) */ ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE); add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN, - BUILT_IN_MD, NULL, NULL_TREE); + BUILT_IN_MD, NULL, returns_twice_attr); add_builtin_function ("__builtin_tbegin_nofloat", ftype, S390_BUILTIN_TBEGIN_NOFLOAT, - BUILT_IN_MD, NULL, NULL_TREE); + BUILT_IN_MD, NULL, returns_twice_attr); /* int foo (void *, int) */ ftype = build_function_type_list (integer_type_node, ptr_type_node, @@ -9702,11 +9894,11 @@ s390_init_builtins (void) add_builtin_function ("__builtin_tbegin_retry", ftype, S390_BUILTIN_TBEGIN_RETRY, BUILT_IN_MD, - NULL, NULL_TREE); + NULL, returns_twice_attr); add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype, S390_BUILTIN_TBEGIN_RETRY_NOFLOAT, BUILT_IN_MD, - NULL, NULL_TREE); + NULL, returns_twice_attr); /* int foo (void) */ ftype = build_function_type_list (integer_type_node, NULL_TREE); @@ -11622,6 +11814,12 @@ s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) #undef TARGET_CANONICALIZE_COMPARISON #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison +#undef TARGET_ATTRIBUTE_TABLE +#define TARGET_ATTRIBUTE_TABLE s390_attribute_table + +#undef TARGET_CAN_INLINE_P +#define TARGET_CAN_INLINE_P s390_can_inline_p + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-s390.h" diff --git a/gcc-4.8/gcc/config/s390/s390.h b/gcc-4.8/gcc/config/s390/s390.h index 03ab89000..a937c30d2 100644 --- a/gcc-4.8/gcc/config/s390/s390.h +++ b/gcc-4.8/gcc/config/s390/s390.h @@ -217,7 +217,7 @@ enum processor_flags #define STACK_BOUNDARY 64 /* Allocation boundary (in *bits*) for the code of a function. */ -#define FUNCTION_BOUNDARY 32 +#define FUNCTION_BOUNDARY 64 /* There is no point aligning anything to a rounder boundary than this. */ #define BIGGEST_ALIGNMENT 64 @@ -878,6 +878,9 @@ do { \ fputc ('\n', (FILE)); \ } while (0) +#undef ASM_OUTPUT_FUNCTION_LABEL +#define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ + s390_asm_output_function_label (FILE, NAME, DECL) /* Miscellaneous parameters. */ diff --git a/gcc-4.8/gcc/config/s390/s390.md b/gcc-4.8/gcc/config/s390/s390.md index ad3ba27c5..fab189843 100644 --- a/gcc-4.8/gcc/config/s390/s390.md +++ b/gcc-4.8/gcc/config/s390/s390.md @@ -147,6 +147,7 @@ ; Transactional Execution support UNSPECV_TBEGIN + UNSPECV_TBEGIN_TDB UNSPECV_TBEGINC UNSPECV_TEND UNSPECV_TABORT @@ -9896,9 +9897,10 @@ (define_insn "tbegin_1" [(set (reg:CCRAW CC_REGNUM) - (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q") - (match_operand 1 "const_int_operand" " D")] + (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] UNSPECV_TBEGIN)) + (set (match_operand:BLK 1 "memory_operand" "=Q") + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) (clobber (reg:DF 16)) (clobber (reg:DF 17)) (clobber (reg:DF 18)) @@ -9917,18 +9919,19 @@ (clobber (reg:DF 31))] ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is ; not supposed to be used for immediates (see genpreds.c). - "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff" - "tbegin\t%0,%x1" + "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" + "tbegin\t%1,%x0" [(set_attr "op_type" "SIL")]) ; Same as above but without the FPR clobbers (define_insn "tbegin_nofloat_1" [(set (reg:CCRAW CC_REGNUM) - (unspec_volatile:CCRAW [(match_operand:BLK 0 "memory_operand" "=Q") - (match_operand 1 "const_int_operand" " D")] - UNSPECV_TBEGIN))] - "TARGET_HTM && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 0xffff" - "tbegin\t%0,%x1" + (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] + UNSPECV_TBEGIN)) + (set (match_operand:BLK 1 "memory_operand" "=Q") + (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] + "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" + "tbegin\t%1,%x0" [(set_attr "op_type" "SIL")]) @@ -10012,15 +10015,12 @@ ; Transaction perform processor assist (define_expand "tx_assist" - [(set (match_dup 1) (const_int 0)) - (unspec_volatile [(match_operand:SI 0 "register_operand" "") - (match_dup 1) + [(unspec_volatile [(match_operand:SI 0 "register_operand" "") + (reg:SI GPR0_REGNUM) (const_int 1)] UNSPECV_PPA)] "TARGET_HTM" -{ - operands[1] = gen_reg_rtx (SImode); -}) + "") (define_insn "*ppa" [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") @@ -10028,5 +10028,5 @@ (match_operand 2 "const_int_operand" "I")] UNSPECV_PPA)] "TARGET_HTM && INTVAL (operands[2]) < 16" - "ppa\t%0,%1,1" + "ppa\t%0,%1,%2" [(set_attr "op_type" "RRF")]) diff --git a/gcc-4.8/gcc/config/s390/s390.opt b/gcc-4.8/gcc/config/s390/s390.opt index a4e6ef25d..65d17c334 100644 --- a/gcc-4.8/gcc/config/s390/s390.opt +++ b/gcc-4.8/gcc/config/s390/s390.opt @@ -96,6 +96,14 @@ mhard-float Target Report RejectNegative Negative(msoft-float) InverseMask(SOFT_FLOAT, HARD_FLOAT) Enable hardware floating point +mhotpatch +Target Report Var(s390_deferred_options) Defer +Prepend the function label with 12 two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching. + +mhotpatch= +Target RejectNegative Report Joined Var(s390_deferred_options) Defer +Prepend the function label with the given number of two-byte Nop instructions, and add a four byte Nop instruction after the label for hotpatching. + mlong-double-128 Target Report RejectNegative Negative(mlong-double-64) Mask(LONG_DOUBLE_128) Use 128-bit long double diff --git a/gcc-4.8/gcc/config/sh/constraints.md b/gcc-4.8/gcc/config/sh/constraints.md index 59bf6b5ad..df7823764 100644 --- a/gcc-4.8/gcc/config/sh/constraints.md +++ b/gcc-4.8/gcc/config/sh/constraints.md @@ -221,6 +221,7 @@ (define_constraint "Q" "A pc relative load operand." (and (match_code "mem") + (match_test "GET_MODE (op) != QImode") (match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))"))) (define_constraint "Bsc" @@ -295,13 +296,15 @@ (define_memory_constraint "Sdd" "A memory reference that uses displacement addressing." - (and (match_test "MEM_P (op) && GET_CODE (XEXP (op, 0)) == PLUS") + (and (match_code "mem") + (match_test "GET_CODE (XEXP (op, 0)) == PLUS") (match_test "REG_P (XEXP (XEXP (op, 0), 0))") (match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))"))) (define_memory_constraint "Snd" "A memory reference that excludes displacement addressing." - (match_test "! satisfies_constraint_Sdd (op)")) + (and (match_code "mem") + (match_test "! satisfies_constraint_Sdd (op)"))) (define_memory_constraint "Sbv" "A memory reference, as used in SH2A bclr.b, bset.b, etc." diff --git a/gcc-4.8/gcc/config/sh/predicates.md b/gcc-4.8/gcc/config/sh/predicates.md index dcbd75bb8..b1905fa0d 100644 --- a/gcc-4.8/gcc/config/sh/predicates.md +++ b/gcc-4.8/gcc/config/sh/predicates.md @@ -389,6 +389,12 @@ XEXP (XEXP (op, 0), 1), TARGET_SH2A, true)"))) +;; Returns true if OP is a displacement address that can fit into a +;; 16 bit (non-SH2A) memory load / store insn. +(define_predicate "short_displacement_mem_operand" + (match_test "sh_disp_addr_displacement (op) + <= sh_max_mov_insn_displacement (GET_MODE (op), false)")) + ;; Returns 1 if the operand can be used in an SH2A movu.{b|w} insn. (define_predicate "zero_extend_movu_operand" (and (match_operand 0 "displacement_mem_operand") @@ -413,6 +419,11 @@ if (t_reg_operand (op, mode)) return 0; + /* Disallow PC relative QImode loads, since these is no insn to do that + and an imm8 load should be used instead. */ + if (IS_PC_RELATIVE_LOAD_ADDR_P (op) && GET_MODE (op) == QImode) + return false; + if (MEM_P (op)) { rtx inside = XEXP (op, 0); diff --git a/gcc-4.8/gcc/config/sh/sh-protos.h b/gcc-4.8/gcc/config/sh/sh-protos.h index 4671c5499..8f99caac0 100644 --- a/gcc-4.8/gcc/config/sh/sh-protos.h +++ b/gcc-4.8/gcc/config/sh/sh-protos.h @@ -159,6 +159,8 @@ extern bool sh_vector_mode_supported_p (enum machine_mode); extern bool sh_cfun_trap_exit_p (void); extern rtx sh_find_equiv_gbr_addr (rtx cur_insn, rtx mem); extern int sh_eval_treg_value (rtx op); +extern HOST_WIDE_INT sh_disp_addr_displacement (rtx mem_op); +extern int sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a); /* Result value of sh_find_set_of_reg. */ struct set_of_reg diff --git a/gcc-4.8/gcc/config/sh/sh.c b/gcc-4.8/gcc/config/sh/sh.c index 44e1e4ce3..9ecaa926d 100644 --- a/gcc-4.8/gcc/config/sh/sh.c +++ b/gcc-4.8/gcc/config/sh/sh.c @@ -24,6 +24,9 @@ along with GCC; see the file COPYING3. If not see malloc & co, which are poisoned by "system.h". The proper solution is to include in "system.h" instead of . */ #include +#include +#include +#include #include "config.h" #include "system.h" @@ -60,10 +63,6 @@ along with GCC; see the file COPYING3. If not see #include "tm-constrs.h" #include "opts.h" -#include -#include -#include - int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch; #define MSW (TARGET_LITTLE_ENDIAN ? 1 : 0) @@ -310,9 +309,7 @@ static rtx sh_trampoline_adjust_address (rtx); static void sh_conditional_register_usage (void); static bool sh_legitimate_constant_p (enum machine_mode, rtx); static int mov_insn_size (enum machine_mode, bool); -static int max_mov_insn_displacement (enum machine_mode, bool); static int mov_insn_alignment_mask (enum machine_mode, bool); -static HOST_WIDE_INT disp_addr_displacement (rtx); static bool sequence_insn_p (rtx); static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool); static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&, @@ -3628,8 +3625,8 @@ mov_insn_size (enum machine_mode mode, bool consider_sh2a) /* Determine the maximum possible displacement for a move insn for the specified mode. */ -static int -max_mov_insn_displacement (enum machine_mode mode, bool consider_sh2a) +int +sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a) { /* The 4 byte displacement move insns are the same as the 2 byte versions but take a 12 bit displacement. All we need to do is to @@ -3665,8 +3662,8 @@ mov_insn_alignment_mask (enum machine_mode mode, bool consider_sh2a) } /* Return the displacement value of a displacement address. */ -static inline HOST_WIDE_INT -disp_addr_displacement (rtx x) +HOST_WIDE_INT +sh_disp_addr_displacement (rtx x) { gcc_assert (satisfies_constraint_Sdd (x)); return INTVAL (XEXP (XEXP (x, 0), 1)); @@ -3703,12 +3700,12 @@ sh_address_cost (rtx x, enum machine_mode mode, HImode and QImode loads/stores with displacement put pressure on R0 which will most likely require another reg copy. Thus account a higher cost for that. */ - if (offset > 0 && offset <= max_mov_insn_displacement (mode, false)) + if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false)) return (mode == HImode || mode == QImode) ? 2 : 1; /* The displacement would fit into a 4 byte move insn (SH2A). */ if (TARGET_SH2A - && offset > 0 && offset <= max_mov_insn_displacement (mode, true)) + && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true)) return 2; /* The displacement is probably out of range and will require extra @@ -10218,7 +10215,7 @@ sh_legitimate_index_p (enum machine_mode mode, rtx op, bool consider_sh2a, else { const HOST_WIDE_INT offset = INTVAL (op); - const int max_disp = max_mov_insn_displacement (mode, consider_sh2a); + const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a); const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a); /* If the mode does not support any displacement always return false. @@ -10404,7 +10401,7 @@ sh_find_mov_disp_adjust (enum machine_mode mode, HOST_WIDE_INT offset) effectively disable the small displacement insns. */ const int mode_sz = GET_MODE_SIZE (mode); const int mov_insn_sz = mov_insn_size (mode, false); - const int max_disp = max_mov_insn_displacement (mode, false); + const int max_disp = sh_max_mov_insn_displacement (mode, false); const int max_disp_next = max_disp + mov_insn_sz; HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0; HOST_WIDE_INT offset_adjust; @@ -13165,7 +13162,8 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, the insns must have the appropriate alternatives. */ if ((mode == QImode || mode == HImode) && rclass != R0_REGS && satisfies_constraint_Sdd (x) - && disp_addr_displacement (x) <= max_mov_insn_displacement (mode, false)) + && sh_disp_addr_displacement (x) + <= sh_max_mov_insn_displacement (mode, false)) return R0_REGS; /* When reload is trying to address a QImode or HImode subreg on the stack, diff --git a/gcc-4.8/gcc/config/sh/sh.md b/gcc-4.8/gcc/config/sh/sh.md index 8ae9cea76..300f99018 100644 --- a/gcc-4.8/gcc/config/sh/sh.md +++ b/gcc-4.8/gcc/config/sh/sh.md @@ -2152,6 +2152,7 @@ (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG))) (clobber (reg:SI T_REG)) (clobber (reg:SI PR_REG)) + (clobber (reg:SI R1_REG)) (clobber (reg:SI R4_REG)) (use (match_operand:SI 1 "arith_reg_operand" "r"))] "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1" @@ -6831,34 +6832,9 @@ label: prepare_move_operands (operands, QImode); }) -;; If movqi_reg_reg is specified as an alternative of movqi, movqi will be -;; selected to copy QImode regs. If one of them happens to be allocated -;; on the stack, reload will stick to movqi insn and generate wrong -;; displacement addressing because of the generic m alternatives. -;; With the movqi_reg_reg being specified before movqi it will be initially -;; picked to load/store regs. If the regs regs are on the stack reload -;; try other insns and not stick to movqi_reg_reg, unless there were spilled -;; pseudos in which case 'm' constraints pertain. -;; The same applies to the movhi variants. -;; -;; Notice, that T bit is not allowed as a mov src operand here. This is to -;; avoid things like (set (reg:QI) (subreg:QI (reg:SI T_REG) 0)), which -;; introduces zero extensions after T bit stores and redundant reg copies. -;; -;; FIXME: We can't use 'arith_reg_operand' (which disallows T_REG) as a -;; predicate for the mov src operand because reload will have trouble -;; reloading MAC subregs otherwise. For that probably special patterns -;; would be required. -(define_insn "*mov_reg_reg" - [(set (match_operand:QIHI 0 "arith_reg_dest" "=r,m,*z") - (match_operand:QIHI 1 "register_operand" "r,*z,m"))] - "TARGET_SH1 && !t_reg_operand (operands[1], VOIDmode)" - "@ - mov %1,%0 - mov. %1,%0 - mov. %1,%0" - [(set_attr "type" "move,store,load")]) - +;; Specifying the displacement addressing load / store patterns separately +;; before the generic movqi / movhi pattern allows controlling the order +;; in which load / store insns are selected in a more fine grained way. ;; FIXME: The non-SH2A and SH2A variants should be combined by adding ;; "enabled" attribute as it is done in other targets. (define_insn "*mov_store_mem_disp04" @@ -6908,38 +6884,44 @@ label: [(set_attr "type" "load") (set_attr "length" "2,2,4")]) -;; The m constraints basically allow any kind of addresses to be used with any -;; source/target register as the other operand. This is not true for -;; displacement addressing modes on anything but SH2A. That's why the -;; specialized load/store insns are specified above. -(define_insn "*movqi" - [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,m,r,l") - (match_operand:QI 1 "general_movsrc_operand" "i,m,r,l,r"))] +;; The order of the constraint alternatives is important here. +;; Q/r has to come first, otherwise PC relative loads might wrongly get +;; placed into delay slots. Since there is no QImode PC relative load, the +;; Q constraint and general_movsrc_operand will reject it for QImode. +;; The Snd alternatives should come before Sdd in order to avoid a preference +;; of using r0 als the register operand for addressing modes other than +;; displacement addressing. +;; The Sdd alternatives allow only r0 as register operand, even though on +;; SH2A any register could be allowed by switching to a 32 bit insn. +;; Generally sticking to the r0 is preferrable, since it generates smaller +;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A. +(define_insn "*mov" + [(set (match_operand:QIHI 0 "general_movdst_operand" + "=r,r,r,Snd,r, Sdd,z, r,l") + (match_operand:QIHI 1 "general_movsrc_operand" + "Q,r,i,r, Snd,z, Sdd,l,r"))] "TARGET_SH1 - && (arith_reg_operand (operands[0], QImode) - || arith_reg_operand (operands[1], QImode))" + && (arith_reg_operand (operands[0], mode) + || arith_reg_operand (operands[1], mode))" "@ + mov. %1,%0 mov %1,%0 - mov.b %1,%0 - mov.b %1,%0 - sts %1,%0 - lds %1,%0" - [(set_attr "type" "movi8,load,store,prget,prset")]) - -(define_insn "*movhi" - [(set (match_operand:HI 0 "general_movdst_operand" "=r,r,r,m,r,l") - (match_operand:HI 1 "general_movsrc_operand" "Q,i,m,r,l,r"))] - "TARGET_SH1 - && (arith_reg_operand (operands[0], HImode) - || arith_reg_operand (operands[1], HImode))" - "@ - mov.w %1,%0 mov %1,%0 - mov.w %1,%0 - mov.w %1,%0 + mov. %1,%0 + mov. %1,%0 + mov. %1,%0 + mov. %1,%0 sts %1,%0 lds %1,%0" - [(set_attr "type" "pcload,movi8,load,store,prget,prset")]) + [(set_attr "type" "pcload,move,movi8,store,load,store,load,prget,prset") + (set (attr "length") + (cond [(and (match_operand 0 "displacement_mem_operand") + (not (match_operand 0 "short_displacement_mem_operand"))) + (const_int 4) + (and (match_operand 1 "displacement_mem_operand") + (not (match_operand 1 "short_displacement_mem_operand"))) + (const_int 4)] + (const_int 2)))]) (define_insn "*movqi_media" [(set (match_operand:QI 0 "general_movdst_operand" "=r,r,r,m") @@ -8427,11 +8409,9 @@ label: while (true) { - /* It's not safe to go beyond the current basic block after reload. */ set_of_reg s1 = sh_find_set_of_reg (tested_reg, s0.insn, - reload_completed - ? prev_nonnote_insn_bb - : prev_nonnote_insn); + prev_nonnote_insn); + if (s1.set_src == NULL_RTX) break; @@ -8454,8 +8434,18 @@ label: T bit. Notice that some T bit stores such as negc also modify the T bit. */ if (modified_between_p (get_t_reg_rtx (), s1.insn, testing_insn) - || modified_in_p (get_t_reg_rtx (), s1.insn)) + || modified_in_p (get_t_reg_rtx (), s1.insn) + || !no_labels_between_p (s1.insn, testing_insn)) operands[2] = NULL_RTX; + else + { + /* If the insn that sets the tested reg has a REG_DEAD note on + the T bit remove that note since we're extending the usage + of the T bit. */ + rtx n = find_regno_note (s1.insn, REG_DEAD, T_REG); + if (n != NULL_RTX) + remove_note (s1.insn, n); + } break; } diff --git a/gcc-4.8/gcc/config/sh/sh.opt b/gcc-4.8/gcc/config/sh/sh.opt index c314e144c..8a6788eb3 100644 --- a/gcc-4.8/gcc/config/sh/sh.opt +++ b/gcc-4.8/gcc/config/sh/sh.opt @@ -21,7 +21,7 @@ ;; Used for various architecture options. Mask(SH_E) -;; Set if the default precision of th FPU is single. +;; Set if the default precision of the FPU is single. Mask(FPU_SINGLE) ;; Set if the a double-precision FPU is present but is restricted to diff --git a/gcc-4.8/gcc/config/sparc/leon.md b/gcc-4.8/gcc/config/sparc/leon.md index 60815079d..b511397fe 100644 --- a/gcc-4.8/gcc/config/sparc/leon.md +++ b/gcc-4.8/gcc/config/sparc/leon.md @@ -17,40 +17,48 @@ ;; along with GCC; see the file COPYING3. If not see ;; . +;; Leon is a single-issue processor. (define_automaton "leon") -(define_cpu_unit "leon_memory, leon_fpalu" "leon") -(define_cpu_unit "leon_fpmds" "leon") -(define_cpu_unit "write_buf" "leon") +(define_cpu_unit "leon_memory" "leon") (define_insn_reservation "leon_load" 1 - (and (eq_attr "cpu" "leon") - (eq_attr "type" "load,sload,fpload")) + (and (eq_attr "cpu" "leon") (eq_attr "type" "load,sload")) "leon_memory") -(define_insn_reservation "leon_store" 1 - (and (eq_attr "cpu" "leon") - (eq_attr "type" "store,fpstore")) - "leon_memory+write_buf") - -(define_insn_reservation "leon_fp_alu" 1 - (and (eq_attr "cpu" "leon") - (eq_attr "type" "fp,fpmove")) - "leon_fpalu, nothing") - -(define_insn_reservation "leon_fp_mult" 1 - (and (eq_attr "cpu" "leon") - (eq_attr "type" "fpmul")) - "leon_fpmds, nothing") - -(define_insn_reservation "leon_fp_div" 16 - (and (eq_attr "cpu" "leon") - (eq_attr "type" "fpdivs,fpdivd")) - "leon_fpmds, nothing*15") - -(define_insn_reservation "leon_fp_sqrt" 23 - (and (eq_attr "cpu" "leon") - (eq_attr "type" "fpsqrts,fpsqrtd")) - "leon_fpmds, nothing*21") +;; Use a double reservation to work around the load pipeline hazard on UT699. +(define_insn_reservation "leon3_load" 1 + (and (eq_attr "cpu" "leon3") (eq_attr "type" "load,sload")) + "leon_memory*2") +(define_insn_reservation "leon_store" 2 + (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "store")) + "leon_memory*2") + +;; This describes Gaisler Research's FPU + +(define_automaton "grfpu") + +(define_cpu_unit "grfpu_alu" "grfpu") +(define_cpu_unit "grfpu_ds" "grfpu") + +(define_insn_reservation "leon_fp_alu" 4 + (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fp,fpcmp,fpmul")) + "grfpu_alu, nothing*3") + +(define_insn_reservation "leon_fp_divs" 16 + (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivs")) + "grfpu_ds*14, nothing*2") + +(define_insn_reservation "leon_fp_divd" 17 + (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpdivd")) + "grfpu_ds*15, nothing*2") + +(define_insn_reservation "leon_fp_sqrts" 24 + (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrts")) + "grfpu_ds*22, nothing*2") + +(define_insn_reservation "leon_fp_sqrtd" 25 + (and (eq_attr "cpu" "leon,leon3") (eq_attr "type" "fpsqrtd")) + "grfpu_ds*23, nothing*2") diff --git a/gcc-4.8/gcc/config/sparc/sparc-opts.h b/gcc-4.8/gcc/config/sparc/sparc-opts.h index 72791772e..b5e9761af 100644 --- a/gcc-4.8/gcc/config/sparc/sparc-opts.h +++ b/gcc-4.8/gcc/config/sparc/sparc-opts.h @@ -30,6 +30,7 @@ enum processor_type { PROCESSOR_SUPERSPARC, PROCESSOR_HYPERSPARC, PROCESSOR_LEON, + PROCESSOR_LEON3, PROCESSOR_SPARCLITE, PROCESSOR_F930, PROCESSOR_F934, diff --git a/gcc-4.8/gcc/config/sparc/sparc-protos.h b/gcc-4.8/gcc/config/sparc/sparc-protos.h index a0c1a7a05..adaeb6d9d 100644 --- a/gcc-4.8/gcc/config/sparc/sparc-protos.h +++ b/gcc-4.8/gcc/config/sparc/sparc-protos.h @@ -69,7 +69,6 @@ extern bool sparc_expand_move (enum machine_mode, rtx *); extern void sparc_emit_set_symbolic_const64 (rtx, rtx, rtx); extern int sparc_splitdi_legitimate (rtx, rtx); extern int sparc_split_regreg_legitimate (rtx, rtx); -extern int sparc_absnegfloat_split_legitimate (rtx, rtx); extern const char *output_ubranch (rtx, rtx); extern const char *output_cbranch (rtx, rtx, int, int, int, rtx); extern const char *output_return (rtx); @@ -84,9 +83,9 @@ extern void emit_conditional_branch_insn (rtx []); extern int mems_ok_for_ldd_peep (rtx, rtx, rtx); extern int empty_delay_slot (rtx); extern int emit_cbcond_nop (rtx); +extern int eligible_for_call_delay (rtx); extern int eligible_for_return_delay (rtx); extern int eligible_for_sibcall_delay (rtx); -extern int tls_call_delay (rtx); extern int emit_move_sequence (rtx, enum machine_mode); extern int fp_sethi_p (rtx); extern int fp_mov_p (rtx); diff --git a/gcc-4.8/gcc/config/sparc/sparc.c b/gcc-4.8/gcc/config/sparc/sparc.c index 7e87b4716..25b7e53f2 100644 --- a/gcc-4.8/gcc/config/sparc/sparc.c +++ b/gcc-4.8/gcc/config/sparc/sparc.c @@ -52,6 +52,7 @@ along with GCC; see the file COPYING3. If not see #include "params.h" #include "df.h" #include "opts.h" +#include "tree-pass.h" /* Processor costs */ @@ -225,6 +226,30 @@ struct processor_costs leon_costs = { 0, /* shift penalty */ }; +static const +struct processor_costs leon3_costs = { + COSTS_N_INSNS (1), /* int load */ + COSTS_N_INSNS (1), /* int signed load */ + COSTS_N_INSNS (1), /* int zeroed load */ + COSTS_N_INSNS (1), /* float load */ + COSTS_N_INSNS (1), /* fmov, fneg, fabs */ + COSTS_N_INSNS (1), /* fadd, fsub */ + COSTS_N_INSNS (1), /* fcmp */ + COSTS_N_INSNS (1), /* fmov, fmovr */ + COSTS_N_INSNS (1), /* fmul */ + COSTS_N_INSNS (14), /* fdivs */ + COSTS_N_INSNS (15), /* fdivd */ + COSTS_N_INSNS (22), /* fsqrts */ + COSTS_N_INSNS (23), /* fsqrtd */ + COSTS_N_INSNS (5), /* imul */ + COSTS_N_INSNS (5), /* imulX */ + 0, /* imul bit factor */ + COSTS_N_INSNS (35), /* idiv */ + COSTS_N_INSNS (35), /* idivX */ + COSTS_N_INSNS (1), /* movcc/movr */ + 0, /* shift penalty */ +}; + static const struct processor_costs sparclet_costs = { COSTS_N_INSNS (3), /* int load */ @@ -538,7 +563,6 @@ static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree); static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); -static void sparc_reorg (void); static struct machine_function * sparc_init_machine_status (void); static bool sparc_cannot_force_const_mem (enum machine_mode, rtx); static rtx sparc_tls_get_addr (void); @@ -680,9 +704,6 @@ char sparc_hard_reg_printed[8]; #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk -#undef TARGET_MACHINE_DEPENDENT_REORG -#define TARGET_MACHINE_DEPENDENT_REORG sparc_reorg - #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS sparc_rtx_costs #undef TARGET_ADDRESS_COST @@ -804,6 +825,306 @@ char sparc_hard_reg_printed[8]; struct gcc_target targetm = TARGET_INITIALIZER; +/* Return the memory reference contained in X if any, zero otherwise. */ + +static rtx +mem_ref (rtx x) +{ + if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND) + x = XEXP (x, 0); + + if (MEM_P (x)) + return x; + + return NULL_RTX; +} + +/* We use a machine specific pass to enable workarounds for errata. + We need to have the (essentially) final form of the insn stream in order + to properly detect the various hazards. Therefore, this machine specific + pass runs as late as possible. The pass is inserted in the pass pipeline + at the end of sparc_option_override. */ + +static bool +sparc_gate_work_around_errata (void) +{ + /* The only errata we handle are those of the AT697F and UT699. */ + return sparc_fix_at697f != 0 || sparc_fix_ut699 != 0; +} + +static unsigned int +sparc_do_work_around_errata (void) +{ + rtx insn, next; + + /* Force all instructions to be split into their final form. */ + split_all_insns_noflow (); + + /* Now look for specific patterns in the insn stream. */ + for (insn = get_insns (); insn; insn = next) + { + bool insert_nop = false; + rtx set; + + /* Look into the instruction in a delay slot. */ + if (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) + insn = XVECEXP (PATTERN (insn), 0, 1); + + /* Look for a single-word load into an odd-numbered FP register. */ + if (sparc_fix_at697f + && NONJUMP_INSN_P (insn) + && (set = single_set (insn)) != NULL_RTX + && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 + && MEM_P (SET_SRC (set)) + && REG_P (SET_DEST (set)) + && REGNO (SET_DEST (set)) > 31 + && REGNO (SET_DEST (set)) % 2 != 0) + { + /* The wrong dependency is on the enclosing double register. */ + const unsigned int x = REGNO (SET_DEST (set)) - 1; + unsigned int src1, src2, dest; + int code; + + next = next_active_insn (insn); + if (!next) + break; + /* If the insn is a branch, then it cannot be problematic. */ + if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) + continue; + + extract_insn (next); + code = INSN_CODE (next); + + switch (code) + { + case CODE_FOR_adddf3: + case CODE_FOR_subdf3: + case CODE_FOR_muldf3: + case CODE_FOR_divdf3: + dest = REGNO (recog_data.operand[0]); + src1 = REGNO (recog_data.operand[1]); + src2 = REGNO (recog_data.operand[2]); + if (src1 != src2) + { + /* Case [1-4]: + ld [address], %fx+1 + FPOPd %f{x,y}, %f{y,x}, %f{x,y} */ + if ((src1 == x || src2 == x) + && (dest == src1 || dest == src2)) + insert_nop = true; + } + else + { + /* Case 5: + ld [address], %fx+1 + FPOPd %fx, %fx, %fx */ + if (src1 == x + && dest == src1 + && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3)) + insert_nop = true; + } + break; + + case CODE_FOR_sqrtdf2: + dest = REGNO (recog_data.operand[0]); + src1 = REGNO (recog_data.operand[1]); + /* Case 6: + ld [address], %fx+1 + fsqrtd %fx, %fx */ + if (src1 == x && dest == src1) + insert_nop = true; + break; + + default: + break; + } + } + + /* Look for a single-word load into an integer register. */ + else if (sparc_fix_ut699 + && NONJUMP_INSN_P (insn) + && (set = single_set (insn)) != NULL_RTX + && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4 + && mem_ref (SET_SRC (set)) != NULL_RTX + && REG_P (SET_DEST (set)) + && REGNO (SET_DEST (set)) < 32) + { + /* There is no problem if the second memory access has a data + dependency on the first single-cycle load. */ + rtx x = SET_DEST (set); + + next = next_active_insn (insn); + if (!next) + break; + /* If the insn is a branch, then it cannot be problematic. */ + if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) + continue; + + /* Look for a second memory access to/from an integer register. */ + if ((set = single_set (next)) != NULL_RTX) + { + rtx src = SET_SRC (set); + rtx dest = SET_DEST (set); + rtx mem; + + /* LDD is affected. */ + if ((mem = mem_ref (src)) != NULL_RTX + && REG_P (dest) + && REGNO (dest) < 32 + && !reg_mentioned_p (x, XEXP (mem, 0))) + insert_nop = true; + + /* STD is *not* affected. */ + else if (MEM_P (dest) + && GET_MODE_SIZE (GET_MODE (dest)) <= 4 + && (src == CONST0_RTX (GET_MODE (dest)) + || (REG_P (src) + && REGNO (src) < 32 + && REGNO (src) != REGNO (x))) + && !reg_mentioned_p (x, XEXP (dest, 0))) + insert_nop = true; + } + } + + /* Look for a single-word load/operation into an FP register. */ + else if (sparc_fix_ut699 + && NONJUMP_INSN_P (insn) + && (set = single_set (insn)) != NULL_RTX + && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 + && REG_P (SET_DEST (set)) + && REGNO (SET_DEST (set)) > 31) + { + /* Number of instructions in the problematic window. */ + const int n_insns = 4; + /* The problematic combination is with the sibling FP register. */ + const unsigned int x = REGNO (SET_DEST (set)); + const unsigned int y = x ^ 1; + rtx after; + int i; + + next = next_active_insn (insn); + if (!next) + break; + /* If the insn is a branch, then it cannot be problematic. */ + if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) + continue; + + /* Look for a second load/operation into the sibling FP register. */ + if (!((set = single_set (next)) != NULL_RTX + && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 + && REG_P (SET_DEST (set)) + && REGNO (SET_DEST (set)) == y)) + continue; + + /* Look for a (possible) store from the FP register in the next N + instructions, but bail out if it is again modified or if there + is a store from the sibling FP register before this store. */ + for (after = next, i = 0; i < n_insns; i++) + { + bool branch_p; + + after = next_active_insn (after); + if (!after) + break; + + /* This is a branch with an empty delay slot. */ + if (!NONJUMP_INSN_P (after)) + { + if (++i == n_insns) + break; + branch_p = true; + after = NULL_RTX; + } + /* This is a branch with a filled delay slot. */ + else if (GET_CODE (PATTERN (after)) == SEQUENCE) + { + if (++i == n_insns) + break; + branch_p = true; + after = XVECEXP (PATTERN (after), 0, 1); + } + /* This is a regular instruction. */ + else + branch_p = false; + + if (after && (set = single_set (after)) != NULL_RTX) + { + const rtx src = SET_SRC (set); + const rtx dest = SET_DEST (set); + const unsigned int size = GET_MODE_SIZE (GET_MODE (dest)); + + /* If the FP register is again modified before the store, + then the store isn't affected. */ + if (REG_P (dest) + && (REGNO (dest) == x + || (REGNO (dest) == y && size == 8))) + break; + + if (MEM_P (dest) && REG_P (src)) + { + /* If there is a store from the sibling FP register + before the store, then the store is not affected. */ + if (REGNO (src) == y || (REGNO (src) == x && size == 8)) + break; + + /* Otherwise, the store is affected. */ + if (REGNO (src) == x && size == 4) + { + insert_nop = true; + break; + } + } + } + + /* If we have a branch in the first M instructions, then we + cannot see the (M+2)th instruction so we play safe. */ + if (branch_p && i <= (n_insns - 2)) + { + insert_nop = true; + break; + } + } + } + + else + next = NEXT_INSN (insn); + + if (insert_nop) + emit_insn_before (gen_nop (), next); + } + + return 0; +} + +struct rtl_opt_pass pass_work_around_errata = +{ + { + RTL_PASS, + "errata", /* name */ + OPTGROUP_NONE, /* optinfo_flags */ + sparc_gate_work_around_errata, /* gate */ + sparc_do_work_around_errata, /* execute */ + NULL, /* sub */ + NULL, /* next */ + 0, /* static_pass_number */ + TV_MACH_DEP, /* tv_id */ + 0, /* properties_required */ + 0, /* properties_provided */ + 0, /* properties_destroyed */ + 0, /* todo_flags_start */ + TODO_verify_rtl_sharing, /* todo_flags_finish */ + } +}; + +struct register_pass_info insert_pass_work_around_errata = +{ + &pass_work_around_errata.pass, /* pass */ + "dbr", /* reference_pass_name */ + 1, /* ref_pass_instance_number */ + PASS_POS_INSERT_AFTER /* po_op */ +}; + +/* Helpers for TARGET_DEBUG_OPTIONS. */ static void dump_target_flag_bits (const int flags) { @@ -888,6 +1209,7 @@ sparc_option_override (void) { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC }, { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC }, { TARGET_CPU_leon, PROCESSOR_LEON }, + { TARGET_CPU_leon3, PROCESSOR_LEON3 }, { TARGET_CPU_sparclite, PROCESSOR_F930 }, { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X }, { TARGET_CPU_sparclet, PROCESSOR_TSC701 }, @@ -902,7 +1224,7 @@ sparc_option_override (void) }; const struct cpu_default *def; /* Table of values for -m{cpu,tune}=. This must match the order of - the PROCESSOR_* enumeration. */ + the enum processor_type in sparc-opts.h. */ static struct cpu_table { const char *const name; const int disable; @@ -914,8 +1236,8 @@ sparc_option_override (void) /* TI TMS390Z55 supersparc */ { "supersparc", MASK_ISA, MASK_V8 }, { "hypersparc", MASK_ISA, MASK_V8|MASK_FPU }, - /* LEON */ - { "leon", MASK_ISA, MASK_V8|MASK_FPU }, + { "leon", MASK_ISA, MASK_V8|MASK_LEON|MASK_FPU }, + { "leon3", MASK_ISA, MASK_V8|MASK_LEON3|MASK_FPU }, { "sparclite", MASK_ISA, MASK_SPARCLITE }, /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, @@ -1074,6 +1396,9 @@ sparc_option_override (void) #endif #ifndef HAVE_AS_SPARC4 & ~MASK_CBCOND +#endif +#ifndef HAVE_AS_LEON + & ~(MASK_LEON | MASK_LEON3) #endif ); @@ -1164,6 +1489,9 @@ sparc_option_override (void) case PROCESSOR_LEON: sparc_costs = &leon_costs; break; + case PROCESSOR_LEON3: + sparc_costs = &leon3_costs; + break; case PROCESSOR_SPARCLET: case PROCESSOR_TSC701: sparc_costs = &sparclet_costs; @@ -1200,6 +1528,10 @@ sparc_option_override (void) /* Choose the most relaxed model for the processor. */ else if (TARGET_V9) sparc_memory_model = SMM_RMO; + else if (TARGET_LEON3) + sparc_memory_model = SMM_TSO; + else if (TARGET_LEON) + sparc_memory_model = SMM_SC; else if (TARGET_V8) sparc_memory_model = SMM_PSO; else @@ -1241,6 +1573,13 @@ sparc_option_override (void) pessimizes for double floating-point registers. */ if (!global_options_set.x_flag_ira_share_save_slots) flag_ira_share_save_slots = 0; + + /* We register a machine specific pass to work around errata, if any. + The pass mut be scheduled as late as possible so that we have the + (essentially) final form of the insn stream to work on. + Registering the pass must be done at start up. It's convenient to + do it here. */ + register_pass (&insert_pass_work_around_errata); } /* Miscellaneous utilities. */ @@ -3090,10 +3429,13 @@ emit_cbcond_nop (rtx insn) /* Return nonzero if TRIAL can go into the call delay slot. */ int -tls_call_delay (rtx trial) +eligible_for_call_delay (rtx trial) { rtx pat; + if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) + return 0; + /* Binutils allows call __tls_get_addr, %tgd_call (foo) add %l7, %o0, %o0, %tgd_add (foo) @@ -3175,11 +3517,7 @@ eligible_for_restore_insn (rtx trial, bool return_p) /* If we have the 'return' instruction, anything that does not use local or output registers and can go into a delay slot wins. */ - else if (return_p - && TARGET_V9 - && !epilogue_renumber (&pat, 1) - && get_attr_in_uncond_branch_delay (trial) - == IN_UNCOND_BRANCH_DELAY_TRUE) + else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1)) return 1; /* The 'restore src1,src2,dest' pattern for SImode. */ @@ -3222,21 +3560,20 @@ eligible_for_return_delay (rtx trial) int regno; rtx pat; - if (GET_CODE (trial) != INSN) - return 0; - - if (get_attr_length (trial) != 1) - return 0; - /* If the function uses __builtin_eh_return, the eh_return machinery occupies the delay slot. */ if (crtl->calls_eh_return) return 0; + if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) + return 0; + /* In the case of a leaf or flat function, anything can go into the slot. */ if (sparc_leaf_function_p || TARGET_FLAT) - return - get_attr_in_uncond_branch_delay (trial) == IN_UNCOND_BRANCH_DELAY_TRUE; + return 1; + + if (!NONJUMP_INSN_P (trial)) + return 0; pat = PATTERN (trial); if (GET_CODE (pat) == PARALLEL) @@ -3256,9 +3593,7 @@ eligible_for_return_delay (rtx trial) if (regno >= 8 && regno < 24) return 0; } - return !epilogue_renumber (&pat, 1) - && (get_attr_in_uncond_branch_delay (trial) - == IN_UNCOND_BRANCH_DELAY_TRUE); + return !epilogue_renumber (&pat, 1); } if (GET_CODE (pat) != SET) @@ -3278,10 +3613,7 @@ eligible_for_return_delay (rtx trial) instruction, it can probably go in. But restore will not work with FP_REGS. */ if (! SPARC_INT_REG_P (regno)) - return (TARGET_V9 - && !epilogue_renumber (&pat, 1) - && get_attr_in_uncond_branch_delay (trial) - == IN_UNCOND_BRANCH_DELAY_TRUE); + return TARGET_V9 && !epilogue_renumber (&pat, 1); return eligible_for_restore_insn (trial, true); } @@ -3293,10 +3625,10 @@ eligible_for_sibcall_delay (rtx trial) { rtx pat; - if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET) + if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) return 0; - if (get_attr_length (trial) != 1) + if (!NONJUMP_INSN_P (trial)) return 0; pat = PATTERN (trial); @@ -3315,6 +3647,9 @@ eligible_for_sibcall_delay (rtx trial) return 1; } + if (GET_CODE (pat) != SET) + return 0; + /* Otherwise, only operations which can be done in tandem with a `restore' insn can go into the delay slot. */ if (GET_CODE (SET_DEST (pat)) != REG @@ -8134,22 +8469,6 @@ sparc_split_regreg_legitimate (rtx reg1, rtx reg2) return 0; } -/* Return 1 if x and y are some kind of REG and they refer to - different hard registers. This test is guaranteed to be - run after reload. */ - -int -sparc_absnegfloat_split_legitimate (rtx x, rtx y) -{ - if (GET_CODE (x) != REG) - return 0; - if (GET_CODE (y) != REG) - return 0; - if (REGNO (x) == REGNO (y)) - return 0; - return 1; -} - /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. This makes them candidates for using ldd and std insns. @@ -10355,7 +10674,8 @@ sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tmp = e0.add_with_sign (tmp, false, &add1_ovf); if (tmp.is_negative ()) tmp = tmp.neg_with_overflow (&neg2_ovf); - + else + neg2_ovf = false; result = result.add_with_sign (tmp, false, &add2_ovf); overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf; } @@ -10897,107 +11217,6 @@ sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, return (vcall_offset >= -32768 || ! fixed_regs[5]); } -/* We use the machine specific reorg pass to enable workarounds for errata. */ - -static void -sparc_reorg (void) -{ - rtx insn, next; - - /* The only erratum we handle for now is that of the AT697F processor. */ - if (!sparc_fix_at697f) - return; - - /* We need to have the (essentially) final form of the insn stream in order - to properly detect the various hazards. Run delay slot scheduling. */ - if (optimize > 0 && flag_delayed_branch) - { - cleanup_barriers (); - dbr_schedule (get_insns ()); - } - - /* Now look for specific patterns in the insn stream. */ - for (insn = get_insns (); insn; insn = next) - { - bool insert_nop = false; - rtx set; - - /* Look for a single-word load into an odd-numbered FP register. */ - if (NONJUMP_INSN_P (insn) - && (set = single_set (insn)) != NULL_RTX - && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 - && MEM_P (SET_SRC (set)) - && REG_P (SET_DEST (set)) - && REGNO (SET_DEST (set)) > 31 - && REGNO (SET_DEST (set)) % 2 != 0) - { - /* The wrong dependency is on the enclosing double register. */ - unsigned int x = REGNO (SET_DEST (set)) - 1; - unsigned int src1, src2, dest; - int code; - - /* If the insn has a delay slot, then it cannot be problematic. */ - next = next_active_insn (insn); - if (NONJUMP_INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE) - code = -1; - else - { - extract_insn (next); - code = INSN_CODE (next); - } - - switch (code) - { - case CODE_FOR_adddf3: - case CODE_FOR_subdf3: - case CODE_FOR_muldf3: - case CODE_FOR_divdf3: - dest = REGNO (recog_data.operand[0]); - src1 = REGNO (recog_data.operand[1]); - src2 = REGNO (recog_data.operand[2]); - if (src1 != src2) - { - /* Case [1-4]: - ld [address], %fx+1 - FPOPd %f{x,y}, %f{y,x}, %f{x,y} */ - if ((src1 == x || src2 == x) - && (dest == src1 || dest == src2)) - insert_nop = true; - } - else - { - /* Case 5: - ld [address], %fx+1 - FPOPd %fx, %fx, %fx */ - if (src1 == x - && dest == src1 - && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3)) - insert_nop = true; - } - break; - - case CODE_FOR_sqrtdf2: - dest = REGNO (recog_data.operand[0]); - src1 = REGNO (recog_data.operand[1]); - /* Case 6: - ld [address], %fx+1 - fsqrtd %fx, %fx */ - if (src1 == x && dest == src1) - insert_nop = true; - break; - - default: - break; - } - } - else - next = NEXT_INSN (insn); - - if (insert_nop) - emit_insn_after (gen_nop (), insn); - } -} - /* How to allocate a 'struct machine_function'. */ static struct machine_function * diff --git a/gcc-4.8/gcc/config/sparc/sparc.h b/gcc-4.8/gcc/config/sparc/sparc.h index c6122c115..d96c1b6b4 100644 --- a/gcc-4.8/gcc/config/sparc/sparc.h +++ b/gcc-4.8/gcc/config/sparc/sparc.h @@ -136,21 +136,22 @@ extern enum cmodel sparc_cmodel; #define TARGET_CPU_supersparc 2 #define TARGET_CPU_hypersparc 3 #define TARGET_CPU_leon 4 -#define TARGET_CPU_sparclite 5 -#define TARGET_CPU_f930 5 /* alias */ -#define TARGET_CPU_f934 5 /* alias */ -#define TARGET_CPU_sparclite86x 6 -#define TARGET_CPU_sparclet 7 -#define TARGET_CPU_tsc701 7 /* alias */ -#define TARGET_CPU_v9 8 /* generic v9 implementation */ -#define TARGET_CPU_sparcv9 8 /* alias */ -#define TARGET_CPU_sparc64 8 /* alias */ -#define TARGET_CPU_ultrasparc 9 -#define TARGET_CPU_ultrasparc3 10 -#define TARGET_CPU_niagara 11 -#define TARGET_CPU_niagara2 12 -#define TARGET_CPU_niagara3 13 -#define TARGET_CPU_niagara4 14 +#define TARGET_CPU_leon3 5 +#define TARGET_CPU_sparclite 6 +#define TARGET_CPU_f930 6 /* alias */ +#define TARGET_CPU_f934 6 /* alias */ +#define TARGET_CPU_sparclite86x 7 +#define TARGET_CPU_sparclet 8 +#define TARGET_CPU_tsc701 8 /* alias */ +#define TARGET_CPU_v9 9 /* generic v9 implementation */ +#define TARGET_CPU_sparcv9 9 /* alias */ +#define TARGET_CPU_sparc64 9 /* alias */ +#define TARGET_CPU_ultrasparc 10 +#define TARGET_CPU_ultrasparc3 11 +#define TARGET_CPU_niagara 12 +#define TARGET_CPU_niagara2 13 +#define TARGET_CPU_niagara3 14 +#define TARGET_CPU_niagara4 15 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ @@ -232,9 +233,10 @@ extern enum cmodel sparc_cmodel; #define ASM_CPU32_DEFAULT_SPEC "" #endif -#if TARGET_CPU_DEFAULT == TARGET_CPU_leon +#if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ + || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" -#define ASM_CPU32_DEFAULT_SPEC "" +#define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG #endif #endif @@ -282,6 +284,7 @@ extern enum cmodel sparc_cmodel; %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ +%{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ %{mcpu=v9:-D__sparc_v9__} \ %{mcpu=ultrasparc:-D__sparc_v9__} \ %{mcpu=ultrasparc3:-D__sparc_v9__} \ @@ -329,7 +332,8 @@ extern enum cmodel sparc_cmodel; %{mcpu=v8:-Av8} \ %{mcpu=supersparc:-Av8} \ %{mcpu=hypersparc:-Av8} \ -%{mcpu=leon:-Av8} \ +%{mcpu=leon:" AS_LEON_FLAG "} \ +%{mcpu=leon3:" AS_LEON_FLAG "} \ %{mv8plus:-Av8plus} \ %{mcpu=v9:-Av9} \ %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ @@ -1754,6 +1758,12 @@ extern int sparc_indent_opcode; #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG #endif +#ifdef HAVE_AS_LEON +#define AS_LEON_FLAG "-Aleon" +#else +#define AS_LEON_FLAG "-Av8" +#endif + /* We use gcc _mcount for profiling. */ #define NO_PROFILE_COUNTERS 0 diff --git a/gcc-4.8/gcc/config/sparc/sparc.md b/gcc-4.8/gcc/config/sparc/sparc.md index b60af4333..f380a414f 100644 --- a/gcc-4.8/gcc/config/sparc/sparc.md +++ b/gcc-4.8/gcc/config/sparc/sparc.md @@ -206,7 +206,7 @@ ;; 'f' for all DF/TFmode values, including those that are specific to the v8. ;; Attribute for cpu type. -;; These must match the values for enum processor_type in sparc.h. +;; These must match the values of the enum processor_type in sparc-opts.h. (define_attr "cpu" "v7, cypress, @@ -214,6 +214,7 @@ supersparc, hypersparc, leon, + leon3, sparclite, f930, f934, @@ -284,7 +285,8 @@ (const_string "none")) (define_attr "pic" "false,true" - (symbol_ref "(flag_pic != 0 ? PIC_TRUE : PIC_FALSE)")) + (symbol_ref "(flag_pic != 0 + ? PIC_TRUE : PIC_FALSE)")) (define_attr "calls_alloca" "false,true" (symbol_ref "(cfun->calls_alloca != 0 @@ -306,6 +308,10 @@ (symbol_ref "(TARGET_FLAT != 0 ? FLAT_TRUE : FLAT_FALSE)")) +(define_attr "fix_ut699" "false,true" + (symbol_ref "(sparc_fix_ut699 != 0 + ? FIX_UT699_TRUE : FIX_UT699_FALSE)")) + ;; Length (in # of insns). ;; Beware that setting a length greater or equal to 3 for conditional branches ;; has a side-effect (see output_cbranch and output_v9branch). @@ -412,6 +418,10 @@ (define_attr "fptype" "single,double" (const_string "single")) +;; FP precision specific to the UT699. +(define_attr "fptype_ut699" "none,single" + (const_string "none")) + ;; UltraSPARC-III integer load type. (define_attr "us3load_type" "2cycle,3cycle" (const_string "2cycle")) @@ -420,32 +430,18 @@ [(set_attr "length" "2") (set_attr "type" "multi")]) -;; Attributes for instruction and branch scheduling -(define_attr "tls_call_delay" "false,true" - (symbol_ref "(tls_call_delay (insn) - ? TLS_CALL_DELAY_TRUE : TLS_CALL_DELAY_FALSE)")) - +;; Attributes for branch scheduling (define_attr "in_call_delay" "false,true" - (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi") - (const_string "false") - (eq_attr "type" "load,fpload,store,fpstore") - (if_then_else (eq_attr "length" "1") - (const_string "true") - (const_string "false"))] - (if_then_else (and (eq_attr "length" "1") - (eq_attr "tls_call_delay" "true")) - (const_string "true") - (const_string "false")))) - -(define_attr "eligible_for_sibcall_delay" "false,true" + (symbol_ref "(eligible_for_call_delay (insn) + ? IN_CALL_DELAY_TRUE : IN_CALL_DELAY_FALSE)")) + +(define_attr "in_sibcall_delay" "false,true" (symbol_ref "(eligible_for_sibcall_delay (insn) - ? ELIGIBLE_FOR_SIBCALL_DELAY_TRUE - : ELIGIBLE_FOR_SIBCALL_DELAY_FALSE)")) + ? IN_SIBCALL_DELAY_TRUE : IN_SIBCALL_DELAY_FALSE)")) -(define_attr "eligible_for_return_delay" "false,true" +(define_attr "in_return_delay" "false,true" (symbol_ref "(eligible_for_return_delay (insn) - ? ELIGIBLE_FOR_RETURN_DELAY_TRUE - : ELIGIBLE_FOR_RETURN_DELAY_FALSE)")) + ? IN_RETURN_DELAY_TRUE : IN_RETURN_DELAY_FALSE)")) ;; ??? !v9: Should implement the notion of predelay slots for floating-point ;; branches. This would allow us to remove the nop always inserted before @@ -460,39 +456,33 @@ ;; because it prevents us from moving back the final store of inner loops. (define_attr "in_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi") - (eq_attr "length" "1")) - (const_string "true") - (const_string "false"))) - -(define_attr "in_uncond_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi") - (eq_attr "length" "1")) - (const_string "true") - (const_string "false"))) - -(define_attr "in_annul_branch_delay" "false,true" - (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi") - (eq_attr "length" "1")) + (cond [(eq_attr "type" "uncond_branch,branch,cbcond,uncond_cbcond,call,sibcall,call_no_delay_slot,multi") + (const_string "false") + (and (eq_attr "fix_ut699" "true") (eq_attr "type" "load,sload")) + (const_string "false") + (and (eq_attr "fix_ut699" "true") + (and (eq_attr "type" "fpload,fp,fpmove,fpmul,fpdivs,fpsqrts") + (ior (eq_attr "fptype" "single") + (eq_attr "fptype_ut699" "single")))) + (const_string "false") + (eq_attr "length" "1") (const_string "true") - (const_string "false"))) + ] (const_string "false"))) (define_delay (eq_attr "type" "call") [(eq_attr "in_call_delay" "true") (nil) (nil)]) (define_delay (eq_attr "type" "sibcall") - [(eq_attr "eligible_for_sibcall_delay" "true") (nil) (nil)]) + [(eq_attr "in_sibcall_delay" "true") (nil) (nil)]) + +(define_delay (eq_attr "type" "return") + [(eq_attr "in_return_delay" "true") (nil) (nil)]) (define_delay (eq_attr "type" "branch") - [(eq_attr "in_branch_delay" "true") - (nil) (eq_attr "in_annul_branch_delay" "true")]) + [(eq_attr "in_branch_delay" "true") (nil) (eq_attr "in_branch_delay" "true")]) (define_delay (eq_attr "type" "uncond_branch") - [(eq_attr "in_uncond_branch_delay" "true") - (nil) (nil)]) - -(define_delay (eq_attr "type" "return") - [(eq_attr "eligible_for_return_delay" "true") (nil) (nil)]) + [(eq_attr "in_branch_delay" "true") (nil) (nil)]) ;; Include SPARC DFA schedulers @@ -3513,7 +3503,8 @@ "TARGET_FPU" "fdtos\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "fptype_ut699" "single")]) (define_expand "trunctfsf2" [(set (match_operand:SF 0 "register_operand" "") @@ -3554,7 +3545,7 @@ "TARGET_FPU" "fitos\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "single")]) (define_insn "floatsidf2" [(set (match_operand:DF 0 "register_operand" "=e") @@ -3641,7 +3632,7 @@ "TARGET_FPU" "fstoi\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "single")]) (define_insn "fix_truncdfsi2" [(set (match_operand:SI 0 "register_operand" "=f") @@ -3649,7 +3640,8 @@ "TARGET_FPU" "fdtoi\t%1, %0" [(set_attr "type" "fp") - (set_attr "fptype" "double")]) + (set_attr "fptype" "double") + (set_attr "fptype_ut699" "single")]) (define_expand "fix_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "") @@ -5548,7 +5540,7 @@ [(set (match_operand:DF 0 "register_operand" "=e") (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "f")) (float_extend:DF (match_operand:SF 2 "register_operand" "f"))))] - "(TARGET_V8 || TARGET_V9) && TARGET_FPU" + "(TARGET_V8 || TARGET_V9) && TARGET_FPU && !sparc_fix_ut699" "fsmuld\t%1, %2, %0" [(set_attr "type" "fpmul") (set_attr "fptype" "double")]) @@ -5575,73 +5567,89 @@ (match_operand:TF 2 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fdivq\t%1, %2, %0" - [(set_attr "type" "fpdivd")]) + [(set_attr "type" "fpdivs")]) -(define_insn "divdf3" +(define_expand "divdf3" [(set (match_operand:DF 0 "register_operand" "=e") (div:DF (match_operand:DF 1 "register_operand" "e") (match_operand:DF 2 "register_operand" "e")))] "TARGET_FPU" + "") + +(define_insn "*divdf3_nofix" + [(set (match_operand:DF 0 "register_operand" "=e") + (div:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU && !sparc_fix_ut699" "fdivd\t%1, %2, %0" [(set_attr "type" "fpdivd") (set_attr "fptype" "double")]) +(define_insn "*divdf3_fix" + [(set (match_operand:DF 0 "register_operand" "=e") + (div:DF (match_operand:DF 1 "register_operand" "e") + (match_operand:DF 2 "register_operand" "e")))] + "TARGET_FPU && sparc_fix_ut699" + "fdivd\t%1, %2, %0\n\tstd\t%0, [%%sp-8]" + [(set_attr "type" "fpdivd") + (set_attr "fptype" "double") + (set_attr "length" "2")]) + (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f") (div:SF (match_operand:SF 1 "register_operand" "f") (match_operand:SF 2 "register_operand" "f")))] - "TARGET_FPU" + "TARGET_FPU && !sparc_fix_ut699" "fdivs\t%1, %2, %0" [(set_attr "type" "fpdivs")]) (define_expand "negtf2" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] + [(set (match_operand:TF 0 "register_operand" "") + (neg:TF (match_operand:TF 1 "register_operand" "")))] "TARGET_FPU" "") -(define_insn_and_split "*negtf2_notv9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU - && ! TARGET_V9" - "@ - fnegs\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); - operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_insn_and_split "*negtf2_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (neg:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU && TARGET_V9" - "@ - fnegd\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:DF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double")]) +(define_insn "*negtf2_hq" + [(set (match_operand:TF 0 "register_operand" "=e") + (neg:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fnegq\t%1, %0" + [(set_attr "type" "fpmove")]) + +(define_insn_and_split "*negtf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (neg:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_HARD_QUAD" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_df_reg (set_dest, 0); + dest2 = gen_df_reg (set_dest, 1); + src1 = gen_df_reg (set_src, 0); + src2 = gen_df_reg (set_src, 1); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_negdf2 (dest1, src1)); + } + else + { + emit_insn (gen_negdf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_expand "negdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -5650,22 +5658,39 @@ "") (define_insn_and_split "*negdf2_notv9" - [(set (match_operand:DF 0 "register_operand" "=e,e") - (neg:DF (match_operand:DF 1 "register_operand" "0,e")))] - "TARGET_FPU && ! TARGET_V9" - "@ - fnegs\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (neg:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) + [(set (match_operand:DF 0 "register_operand" "=e") + (neg:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_V9" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_negsf2 (dest1, src1)); + } + else + { + emit_insn (gen_negsf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_insn "*negdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5688,56 +5713,47 @@ "TARGET_FPU" "") -(define_insn_and_split "*abstf2_notv9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - ; We don't use quad float insns here so we don't need TARGET_HARD_QUAD. - "TARGET_FPU && ! TARGET_V9" - "@ - fabss\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5)) - (set (match_dup 6) (match_dup 7))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1); - operands[6] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[7] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) - -(define_insn "*abstf2_hq_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - "TARGET_FPU && TARGET_V9 && TARGET_HARD_QUAD" - "@ - fabsd\t%0, %0 - fabsq\t%1, %0" - [(set_attr "type" "fpmove") - (set_attr "fptype" "double,*")]) +(define_insn "*abstf2_hq" + [(set (match_operand:TF 0 "register_operand" "=e") + (abs:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && TARGET_HARD_QUAD" + "fabsq\t%1, %0" + [(set_attr "type" "fpmove")]) -(define_insn_and_split "*abstf2_v9" - [(set (match_operand:TF 0 "register_operand" "=e,e") - (abs:TF (match_operand:TF 1 "register_operand" "0,e")))] - "TARGET_FPU && TARGET_V9 && !TARGET_HARD_QUAD" - "@ - fabsd\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:DF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (DFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (DFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (DFmode, REGNO (operands[0]) + 2); - operands[5] = gen_rtx_raw_REG (DFmode, REGNO (operands[1]) + 2);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2") - (set_attr "fptype" "double,*")]) +(define_insn_and_split "*abstf2" + [(set (match_operand:TF 0 "register_operand" "=e") + (abs:TF (match_operand:TF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_HARD_QUAD" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_df_reg (set_dest, 0); + dest2 = gen_df_reg (set_dest, 1); + src1 = gen_df_reg (set_src, 0); + src2 = gen_df_reg (set_src, 1); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movdf (dest2, src2)); + emit_insn (gen_absdf2 (dest1, src1)); + } + else + { + emit_insn (gen_absdf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movdf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_expand "absdf2" [(set (match_operand:DF 0 "register_operand" "") @@ -5746,22 +5762,39 @@ "") (define_insn_and_split "*absdf2_notv9" - [(set (match_operand:DF 0 "register_operand" "=e,e") - (abs:DF (match_operand:DF 1 "register_operand" "0,e")))] - "TARGET_FPU && ! TARGET_V9" - "@ - fabss\t%0, %0 - #" - "&& reload_completed - && sparc_absnegfloat_split_legitimate (operands[0], operands[1])" - [(set (match_dup 2) (abs:SF (match_dup 3))) - (set (match_dup 4) (match_dup 5))] - "operands[2] = gen_rtx_raw_REG (SFmode, REGNO (operands[0])); - operands[3] = gen_rtx_raw_REG (SFmode, REGNO (operands[1])); - operands[4] = gen_rtx_raw_REG (SFmode, REGNO (operands[0]) + 1); - operands[5] = gen_rtx_raw_REG (SFmode, REGNO (operands[1]) + 1);" - [(set_attr "type" "fpmove,*") - (set_attr "length" "*,2")]) + [(set (match_operand:DF 0 "register_operand" "=e") + (abs:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !TARGET_V9" + "#" + "&& reload_completed" + [(clobber (const_int 0))] +{ + rtx set_dest = operands[0]; + rtx set_src = operands[1]; + rtx dest1, dest2; + rtx src1, src2; + + dest1 = gen_highpart (SFmode, set_dest); + dest2 = gen_lowpart (SFmode, set_dest); + src1 = gen_highpart (SFmode, set_src); + src2 = gen_lowpart (SFmode, set_src); + + /* Now emit using the real source and destination we found, swapping + the order if we detect overlap. */ + if (reg_overlap_mentioned_p (dest1, src2)) + { + emit_insn (gen_movsf (dest2, src2)); + emit_insn (gen_abssf2 (dest1, src1)); + } + else + { + emit_insn (gen_abssf2 (dest1, src1)); + if (REGNO (dest2) != REGNO (src2)) + emit_insn (gen_movsf (dest2, src2)); + } + DONE; +} + [(set_attr "length" "2")]) (define_insn "*absdf2_v9" [(set (match_operand:DF 0 "register_operand" "=e") @@ -5789,20 +5822,35 @@ (sqrt:TF (match_operand:TF 1 "register_operand" "e")))] "TARGET_FPU && TARGET_HARD_QUAD" "fsqrtq\t%1, %0" - [(set_attr "type" "fpsqrtd")]) + [(set_attr "type" "fpsqrts")]) -(define_insn "sqrtdf2" +(define_expand "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=e") (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] "TARGET_FPU" + "") + +(define_insn "*sqrtdf2_nofix" + [(set (match_operand:DF 0 "register_operand" "=e") + (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && !sparc_fix_ut699" "fsqrtd\t%1, %0" [(set_attr "type" "fpsqrtd") (set_attr "fptype" "double")]) +(define_insn "*sqrtdf2_fix" + [(set (match_operand:DF 0 "register_operand" "=e") + (sqrt:DF (match_operand:DF 1 "register_operand" "e")))] + "TARGET_FPU && sparc_fix_ut699" + "fsqrtd\t%1, %0\n\tstd\t%0, [%%sp-8]" + [(set_attr "type" "fpsqrtd") + (set_attr "fptype" "double") + (set_attr "length" "2")]) + (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") (sqrt:SF (match_operand:SF 1 "register_operand" "f")))] - "TARGET_FPU" + "TARGET_FPU && !sparc_fix_ut699" "fsqrts\t%1, %0" [(set_attr "type" "fpsqrts")]) @@ -5821,19 +5869,6 @@ } [(set_attr "type" "shift")]) -(define_insn "*ashlsi3_extend" - [(set (match_operand:DI 0 "register_operand" "=r") - (zero_extend:DI - (ashift:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "rI"))))] - "TARGET_ARCH64" -{ - if (GET_CODE (operands[2]) == CONST_INT) - operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); - return "sll\t%1, %2, %0"; -} - [(set_attr "type" "shift")]) - (define_expand "ashldi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashift:DI (match_operand:DI 1 "register_operand" "r") diff --git a/gcc-4.8/gcc/config/sparc/sparc.opt b/gcc-4.8/gcc/config/sparc/sparc.opt index 764c652e8..9de981b85 100644 --- a/gcc-4.8/gcc/config/sparc/sparc.opt +++ b/gcc-4.8/gcc/config/sparc/sparc.opt @@ -113,6 +113,10 @@ mrelax Target Optimize tail call instructions in assembler and linker +muser-mode +Target Report Mask(USER_MODE) +Do not generate code that can only run in supervisor mode + mcpu= Target RejectNegative Joined Var(sparc_cpu_and_features) Enum(sparc_processor_type) Init(PROCESSOR_V7) Use features of and schedule code for given CPU @@ -145,6 +149,9 @@ Enum(sparc_processor_type) String(hypersparc) Value(PROCESSOR_HYPERSPARC) EnumValue Enum(sparc_processor_type) String(leon) Value(PROCESSOR_LEON) +EnumValue +Enum(sparc_processor_type) String(leon3) Value(PROCESSOR_LEON3) + EnumValue Enum(sparc_processor_type) String(sparclite) Value(PROCESSOR_SPARCLITE) @@ -201,9 +208,19 @@ Target Report RejectNegative Var(sparc_fix_at697f) Enable workaround for single erratum of AT697F processor (corresponding to erratum #13 of AT697E processor) +mfix-ut699 +Target Report RejectNegative Var(sparc_fix_ut699) +Enable workarounds for the errata of the UT699 processor + Mask(LONG_DOUBLE_128) ;; Use 128-bit long double +Mask(LEON) +;; Generate code for LEON + +Mask(LEON3) +;; Generate code for LEON3 + Mask(SPARCLITE) ;; Generate code for SPARClite diff --git a/gcc-4.8/gcc/config/sparc/sync.md b/gcc-4.8/gcc/config/sparc/sync.md index 1c1b9774b..cf909853b 100644 --- a/gcc-4.8/gcc/config/sparc/sync.md +++ b/gcc-4.8/gcc/config/sparc/sync.md @@ -161,7 +161,8 @@ (match_operand:SI 5 "const_int_operand" "") ;; is_weak (match_operand:SI 6 "const_int_operand" "") ;; mod_s (match_operand:SI 7 "const_int_operand" "")] ;; mod_f - "TARGET_V9 && (mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)" + "(TARGET_V9 || TARGET_LEON3) + && (mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)" { sparc_expand_compare_and_swap (operands); DONE; @@ -176,7 +177,7 @@ [(match_operand:I48MODE 2 "register_operand" "") (match_operand:I48MODE 3 "register_operand" "")] UNSPECV_CAS))])] - "TARGET_V9" + "TARGET_V9 || TARGET_LEON3" "") (define_insn "*atomic_compare_and_swap_1" @@ -187,10 +188,27 @@ [(match_operand:I48MODE 2 "register_operand" "r") (match_operand:I48MODE 3 "register_operand" "0")] UNSPECV_CAS))] - "TARGET_V9 && (mode == SImode || TARGET_ARCH64)" + "TARGET_V9 && (mode != DImode || TARGET_ARCH64)" "cas\t%1, %2, %0" [(set_attr "type" "multi")]) +(define_insn "*atomic_compare_and_swap_leon3_1" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:SI 1 "mem_noofs_operand" "+w")) + (set (match_dup 1) + (unspec_volatile:SI + [(match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "register_operand" "0")] + UNSPECV_CAS))] + "TARGET_LEON3" +{ + if (TARGET_USER_MODE) + return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ + else + return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ +} + [(set_attr "type" "multi")]) + (define_insn "*atomic_compare_and_swapdi_v8plus" [(set (match_operand:DI 0 "register_operand" "=h") (match_operand:DI 1 "mem_noofs_operand" "+w")) @@ -220,7 +238,7 @@ (match_operand:SI 1 "memory_operand" "") (match_operand:SI 2 "register_operand" "") (match_operand:SI 3 "const_int_operand" "")] - "TARGET_V8 || TARGET_V9" + "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" { enum memmodel model = (enum memmodel) INTVAL (operands[3]); @@ -236,7 +254,7 @@ UNSPECV_SWAP)) (set (match_dup 1) (match_operand:SI 2 "register_operand" "0"))] - "TARGET_V8 || TARGET_V9" + "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" "swap\t%1, %0" [(set_attr "type" "multi")]) @@ -244,7 +262,7 @@ [(match_operand:QI 0 "register_operand" "") (match_operand:QI 1 "memory_operand" "") (match_operand:SI 2 "const_int_operand" "")] - "" + "!sparc_fix_ut699" { enum memmodel model = (enum memmodel) INTVAL (operands[2]); rtx ret; @@ -268,6 +286,6 @@ (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")] UNSPECV_LDSTUB)) (set (match_dup 1) (const_int -1))] - "" + "!sparc_fix_ut699" "ldstub\t%1, %0" [(set_attr "type" "multi")]) diff --git a/gcc-4.8/gcc/config/sparc/t-rtems b/gcc-4.8/gcc/config/sparc/t-rtems index 63d021770..f1a3d845e 100644 --- a/gcc-4.8/gcc/config/sparc/t-rtems +++ b/gcc-4.8/gcc/config/sparc/t-rtems @@ -17,6 +17,6 @@ # . # -MULTILIB_OPTIONS = msoft-float mcpu=v8 -MULTILIB_DIRNAMES = soft v8 +MULTILIB_OPTIONS = msoft-float mcpu=v8/mcpu=leon3 +MULTILIB_DIRNAMES = soft v8 leon3 MULTILIB_MATCHES = msoft-float=mno-fpu diff --git a/gcc-4.8/gcc/config/sparc/t-sparc b/gcc-4.8/gcc/config/sparc/t-sparc index d7b17fbd0..664f4a424 100644 --- a/gcc-4.8/gcc/config/sparc/t-sparc +++ b/gcc-4.8/gcc/config/sparc/t-sparc @@ -23,7 +23,7 @@ sparc.o: $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ insn-codes.h conditions.h output.h $(INSN_ATTR_H) $(FLAGS_H) \ $(FUNCTION_H) $(EXCEPT_H) $(EXPR_H) $(OPTABS_H) $(RECOG_H) \ $(DIAGNOSTIC_CORE_H) $(GGC_H) $(TM_P_H) debug.h $(TARGET_H) \ - $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) \ + $(TARGET_DEF_H) $(COMMON_TARGET_H) $(GIMPLE_H) $(TREE_PASS_H) \ langhooks.h reload.h $(PARAMS_H) $(DF_H) $(OPTS_H) \ gt-sparc.h diff --git a/gcc-4.8/gcc/config/tilegx/sync.md b/gcc-4.8/gcc/config/tilegx/sync.md index a4bea6b68..16f18922f 100644 --- a/gcc-4.8/gcc/config/tilegx/sync.md +++ b/gcc-4.8/gcc/config/tilegx/sync.md @@ -150,15 +150,22 @@ (match_operand:SI 3 "const_int_operand" "")] ;; model "" { + rtx addend; enum memmodel model = (enum memmodel) INTVAL (operands[3]); if (operands[2] != const0_rtx) - emit_move_insn (operands[2], gen_rtx_NEG (mode, operands[2])); + { + addend = gen_reg_rtx (mode); + emit_move_insn (addend, + gen_rtx_MINUS (mode, const0_rtx, operands[2])); + } + else + addend = operands[2]; tilegx_pre_atomic_barrier (model); emit_insn (gen_atomic_fetch_add_bare (operands[0], operands[1], - operands[2])); + addend)); tilegx_post_atomic_barrier (model); DONE; }) diff --git a/gcc-4.8/gcc/config/tilegx/tilegx-c.c b/gcc-4.8/gcc/config/tilegx/tilegx-c.c index 3ecec6e04..8d19d20f7 100644 --- a/gcc-4.8/gcc/config/tilegx/tilegx-c.c +++ b/gcc-4.8/gcc/config/tilegx/tilegx-c.c @@ -47,6 +47,9 @@ tilegx_cpu_cpp_builtins (struct cpp_reader *pfile) if (TARGET_32BIT) builtin_define ("__tilegx32__"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + TILEGX_CPU_CPP_ENDIAN_BUILTINS (); GNU_USER_TARGET_OS_CPP_BUILTINS (); } diff --git a/gcc-4.8/gcc/config/tilegx/tilegx.c b/gcc-4.8/gcc/config/tilegx/tilegx.c index beb1012cf..502b953cf 100644 --- a/gcc-4.8/gcc/config/tilegx/tilegx.c +++ b/gcc-4.8/gcc/config/tilegx/tilegx.c @@ -702,6 +702,16 @@ tilegx_init_expanders (void) } +/* Implement TARGET_EXPAND_TO_RTL_HOOK. */ +static void +tilegx_expand_to_rtl_hook (void) +{ + /* Exclude earlier sets of crtl->uses_pic_offset_table, because we + only care about uses actually emitted. */ + crtl->uses_pic_offset_table = 0; +} + + /* Implement TARGET_SHIFT_TRUNCATION_MASK. DImode shifts use the mode matching insns and therefore guarantee that the shift count is modulo 64. SImode shifts sometimes use the 64 bit version so do @@ -3543,6 +3553,12 @@ tilegx_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) + PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid) @@ -4368,10 +4384,12 @@ tilegx_gen_bundles (void) basic_block bb; FOR_EACH_BB (bb) { - rtx insn, next; + rtx insn, next, prev; rtx end = NEXT_INSN (BB_END (bb)); - for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; insn = next) + prev = NULL_RTX; + for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn; + prev = insn, insn = next) { next = next_insn_to_bundle (NEXT_INSN (insn), end); @@ -4396,6 +4414,18 @@ tilegx_gen_bundles (void) PUT_MODE (insn, SImode); } } + + /* Delete barrier insns, because they can mess up the + emitting of bundle braces. If it is end-of-bundle, then + the previous insn must be marked end-of-bundle. */ + if (get_attr_type (insn) == TYPE_NOTHING) { + if (GET_MODE (insn) == QImode && prev != NULL + && GET_MODE (prev) == SImode) + { + PUT_MODE (prev, QImode); + } + delete_insn (insn); + } } } } @@ -5498,6 +5528,9 @@ tilegx_file_end (void) #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS tilegx_rtx_costs +#undef TARGET_EXPAND_TO_RTL_HOOK +#define TARGET_EXPAND_TO_RTL_HOOK tilegx_expand_to_rtl_hook + #undef TARGET_SHIFT_TRUNCATION_MASK #define TARGET_SHIFT_TRUNCATION_MASK tilegx_shift_truncation_mask diff --git a/gcc-4.8/gcc/config/tilegx/tilegx.md b/gcc-4.8/gcc/config/tilegx/tilegx.md index 8dfcff603..5fe177619 100644 --- a/gcc-4.8/gcc/config/tilegx/tilegx.md +++ b/gcc-4.8/gcc/config/tilegx/tilegx.md @@ -5076,10 +5076,8 @@ ;; Network intrinsics -;; Note the "pseudo" text is handled specially by the -;; asm_output_opcode routine. If the output is an empty string, the -;; instruction would bypass the asm_output_opcode routine, bypassing -;; the bundle handling code. +;; Note the this barrier is of type "nothing," which is deleted after +;; the final scheduling pass so that nothing is emitted for it. (define_insn "tilegx_network_barrier" [(unspec_volatile:SI [(const_int 0)] UNSPEC_NETWORK_BARRIER)] "" diff --git a/gcc-4.8/gcc/config/tilepro/tilepro-c.c b/gcc-4.8/gcc/config/tilepro/tilepro-c.c index 8f7aa00d7..b9bf24ab2 100644 --- a/gcc-4.8/gcc/config/tilepro/tilepro-c.c +++ b/gcc-4.8/gcc/config/tilepro/tilepro-c.c @@ -44,6 +44,11 @@ tilepro_cpu_cpp_builtins (struct cpp_reader *pfile) builtin_define ("__tile_chip__=1"); builtin_define ("__tile_chip_rev__=0"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); + builtin_define ("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); + TILEPRO_CPU_CPP_ENDIAN_BUILTINS (); GNU_USER_TARGET_OS_CPP_BUILTINS (); } diff --git a/gcc-4.8/gcc/config/tilepro/tilepro.c b/gcc-4.8/gcc/config/tilepro/tilepro.c index 59618e438..957146dd5 100644 --- a/gcc-4.8/gcc/config/tilepro/tilepro.c +++ b/gcc-4.8/gcc/config/tilepro/tilepro.c @@ -3167,6 +3167,12 @@ tilepro_expand_builtin (tree exp, } if (!pat) return NULL_RTX; + + /* If we are generating a prefetch, tell the scheduler not to move + it around. */ + if (GET_CODE (pat) == PREFETCH) + PREFETCH_SCHEDULE_BARRIER_P (pat) = true; + emit_insn (pat); if (nonvoid) diff --git a/gcc-4.8/gcc/config/tilepro/tilepro.md b/gcc-4.8/gcc/config/tilepro/tilepro.md index ca8cf80ca..ba9bc76d4 100644 --- a/gcc-4.8/gcc/config/tilepro/tilepro.md +++ b/gcc-4.8/gcc/config/tilepro/tilepro.md @@ -795,7 +795,7 @@ (define_expand "ctzdi2" [(set (match_operand:DI 0 "register_operand" "") - (ctz:DI (match_operand:DI 1 "reg_or_0_operand" "")))] + (ctz:DI (match_operand:DI 1 "register_operand" "")))] "" { rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, result; @@ -823,7 +823,7 @@ (define_expand "clzdi2" [(set (match_operand:DI 0 "register_operand" "") - (clz:DI (match_operand:DI 1 "reg_or_0_operand" "")))] + (clz:DI (match_operand:DI 1 "register_operand" "")))] "" { rtx lo, hi, clz_lo, clz_hi, clz_lo_plus_32, result; @@ -851,7 +851,7 @@ (define_expand "ffsdi2" [(set (match_operand:DI 0 "register_operand" "") - (ffs:DI (match_operand:DI 1 "reg_or_0_operand" "")))] + (ffs:DI (match_operand:DI 1 "register_operand" "")))] "" { rtx lo, hi, ctz_lo, ctz_hi, ctz_hi_plus_32, ctz, ctz_plus_1,ctz_cond; diff --git a/gcc-4.8/gcc/configure b/gcc-4.8/gcc/configure index 624b807a1..a8e67d1d0 100755 --- a/gcc-4.8/gcc/configure +++ b/gcc-4.8/gcc/configure @@ -11206,13 +11206,16 @@ else /* | A-Za-z:\\/* ) realsrcdir=${srcdir};; *) realsrcdir=../${srcdir};; esac - saved_CFLAGS="${CFLAGS}" + # Clearing GMPINC is necessary to prevent host headers being + # used by the build compiler. Defining GENERATOR_FILE stops + # system.h from including gmp.h. CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \ - LDFLAGS="${LDFLAGS_FOR_BUILD}" \ + CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \ + LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \ + GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \ ${realsrcdir}/configure \ --enable-languages=${enable_languages-all} \ --target=$target_alias --host=$build_alias --build=$build_alias - CFLAGS="${saved_CFLAGS}" # We just finished tests for the build machine, so rename # the file auto-build.h in the gcc directory. @@ -11707,6 +11710,7 @@ STMP_FIXINC=stmp-fixinc if test x$build != x$host || test "x$coverage_flags" != x then BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)' + BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)' BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)' fi @@ -13594,7 +13598,7 @@ ia64-*-hpux*) rm -rf conftest* ;; -x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ +x86_64-*kfreebsd*-gnu|x86_64-*linux*|powerpc*-*linux*| \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext @@ -13619,7 +13623,10 @@ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) ;; esac ;; - ppc64-*linux*|powerpc64-*linux*) + powerpc64le-*linux*) + LD="${LD-ld} -m elf32lppclinux" + ;; + powerpc64-*linux*) LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) @@ -13638,7 +13645,10 @@ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; - ppc*-*linux*|powerpc*-*linux*) + powerpcle-*linux*) + LD="${LD-ld} -m elf64lppc" + ;; + powerpc-*linux*) LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) @@ -17832,7 +17842,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 17831 "configure" +#line 17841 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -17938,7 +17948,7 @@ else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF -#line 17937 "configure" +#line 17947 "configure" #include "confdefs.h" #if HAVE_DLFCN_H @@ -24268,6 +24278,43 @@ if test $gcc_cv_as_sparc_sparc4 = yes; then $as_echo "#define HAVE_AS_SPARC4 1" >>confdefs.h +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for LEON instructions" >&5 +$as_echo_n "checking assembler for LEON instructions... " >&6; } +if test "${gcc_cv_as_sparc_leon+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_sparc_leon=no + if test x$gcc_cv_as != x; then + $as_echo '.text + .register %g2, #scratch + .register %g3, #scratch + .align 4 + smac %g2, %g3, %g1 + umac %g2, %g3, %g1 + casa [%g2] 0xb, %g3, %g1' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags -Aleon -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + gcc_cv_as_sparc_leon=yes + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_sparc_leon" >&5 +$as_echo "$gcc_cv_as_sparc_leon" >&6; } +if test $gcc_cv_as_sparc_leon = yes; then + +$as_echo "#define HAVE_AS_LEON 1" >>confdefs.h + fi ;; @@ -24751,6 +24798,10 @@ fi # These two are used unconditionally by i386.[ch]; it is to be defined # to 1 if the feature is present, 0 otherwise. + as_ix86_gotoff_in_data_opt= + if test x$gas = xyes; then + as_ix86_gotoff_in_data_opt="--32" + fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for GOTOFF in data" >&5 $as_echo_n "checking assembler for GOTOFF in data... " >&6; } if test "${gcc_cv_as_ix86_gotoff_in_data+set}" = set; then : @@ -24767,7 +24818,7 @@ fi nop .data .long .L0@GOTOFF' > conftest.s - if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' + if { ac_try='$gcc_cv_as $gcc_cv_as_flags $as_ix86_gotoff_in_data_opt -o conftest.o conftest.s >&5' { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 (eval $ac_try) 2>&5 ac_status=$? @@ -24826,6 +24877,37 @@ if test $gcc_cv_as_ix86_rep_lock_prefix = yes; then $as_echo "#define HAVE_AS_IX86_REP_LOCK_PREFIX 1" >>confdefs.h +fi + + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for ud2 mnemonic" >&5 +$as_echo_n "checking assembler for ud2 mnemonic... " >&6; } +if test "${gcc_cv_as_ix86_ud2+set}" = set; then : + $as_echo_n "(cached) " >&6 +else + gcc_cv_as_ix86_ud2=no + if test x$gcc_cv_as != x; then + $as_echo 'ud2' > conftest.s + if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' + { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 + (eval $ac_try) 2>&5 + ac_status=$? + $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 + test $ac_status = 0; }; } + then + gcc_cv_as_ix86_ud2=yes + else + echo "configure: failed program was" >&5 + cat conftest.s >&5 + fi + rm -f conftest.o conftest.s + fi +fi +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_ix86_ud2" >&5 +$as_echo "$gcc_cv_as_ix86_ud2" >&6; } +if test $gcc_cv_as_ix86_ud2 = yes; then + +$as_echo "#define HAVE_AS_IX86_UD2 1" >>confdefs.h + fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for R_386_TLS_GD_PLT reloc" >&5 @@ -27277,8 +27359,8 @@ if test x"$enable_plugin" = x"yes"; then $as_echo_n "checking for exported symbols... " >&6; } if test "x$export_sym_check" != x; then echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c - ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1 - if $export_sym_check conftest | grep foobar > /dev/null; then + ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1 + if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then : # No need to use a flag { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } @@ -27287,8 +27369,8 @@ $as_echo "yes" >&6; } $as_echo "yes" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -rdynamic" >&5 $as_echo_n "checking for -rdynamic... " >&6; } - ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1 - if $export_sym_check conftest | grep foobar > /dev/null; then + ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1 + if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then plugin_rdynamic=yes pluginlibs="-rdynamic" else diff --git a/gcc-4.8/gcc/configure.ac b/gcc-4.8/gcc/configure.ac index f070a7f4b..9b67ee27f 100644 --- a/gcc-4.8/gcc/configure.ac +++ b/gcc-4.8/gcc/configure.ac @@ -1516,13 +1516,16 @@ else /* | [A-Za-z]:[\\/]* ) realsrcdir=${srcdir};; *) realsrcdir=../${srcdir};; esac - saved_CFLAGS="${CFLAGS}" + # Clearing GMPINC is necessary to prevent host headers being + # used by the build compiler. Defining GENERATOR_FILE stops + # system.h from including gmp.h. CC="${CC_FOR_BUILD}" CFLAGS="${CFLAGS_FOR_BUILD}" \ - LDFLAGS="${LDFLAGS_FOR_BUILD}" \ + CXX="${CXX_FOR_BUILD}" CXXFLAGS="${CXXFLAGS_FOR_BUILD}" \ + LD="${LD_FOR_BUILD}" LDFLAGS="${LDFLAGS_FOR_BUILD}" \ + GMPINC="" CPPFLAGS="${CPPFLAGS} -DGENERATOR_FILE" \ ${realsrcdir}/configure \ --enable-languages=${enable_languages-all} \ --target=$target_alias --host=$build_alias --build=$build_alias - CFLAGS="${saved_CFLAGS}" # We just finished tests for the build machine, so rename # the file auto-build.h in the gcc directory. @@ -1887,6 +1890,7 @@ STMP_FIXINC=stmp-fixinc AC_SUBST(STMP_FIXINC) if test x$build != x$host || test "x$coverage_flags" != x then BUILD_CFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CFLAGS_FOR_BUILD)' + BUILD_CXXFLAGS='$(INTERNAL_CFLAGS) $(T_CFLAGS) $(CXXFLAGS_FOR_BUILD)' BUILD_LDFLAGS='$(LDFLAGS_FOR_BUILD)' fi @@ -3613,6 +3617,19 @@ foo: kasumi_fi_xor %f46, %f48, %f50, %f52],, [AC_DEFINE(HAVE_AS_SPARC4, 1, [Define if your assembler supports SPARC4 instructions.])]) + + gcc_GAS_CHECK_FEATURE([LEON instructions], + gcc_cv_as_sparc_leon,, + [-Aleon], + [.text + .register %g2, #scratch + .register %g3, #scratch + .align 4 + smac %g2, %g3, %g1 + umac %g2, %g3, %g1 + casa [[%g2]] 0xb, %g3, %g1],, + [AC_DEFINE(HAVE_AS_LEON, 1, + [Define if your assembler supports LEON instructions.])]) ;; changequote(,)dnl @@ -3751,8 +3768,13 @@ foo: nop # These two are used unconditionally by i386.[ch]; it is to be defined # to 1 if the feature is present, 0 otherwise. + as_ix86_gotoff_in_data_opt= + if test x$gas = xyes; then + as_ix86_gotoff_in_data_opt="--32" + fi gcc_GAS_CHECK_FEATURE([GOTOFF in data], - gcc_cv_as_ix86_gotoff_in_data, [2,11,0],, + gcc_cv_as_ix86_gotoff_in_data, [2,11,0], + [$as_ix86_gotoff_in_data_opt], [ .text .L0: nop @@ -3774,6 +3796,12 @@ foo: nop [AC_DEFINE(HAVE_AS_IX86_REP_LOCK_PREFIX, 1, [Define if the assembler supports 'rep , lock '.])]) + gcc_GAS_CHECK_FEATURE([ud2 mnemonic], + gcc_cv_as_ix86_ud2,,, + [ud2],, + [AC_DEFINE(HAVE_AS_IX86_UD2, 1, + [Define if your assembler supports the 'ud2' mnemonic.])]) + gcc_GAS_CHECK_FEATURE([R_386_TLS_GD_PLT reloc], gcc_cv_as_ix86_tlsgdplt,,, [call tls_gd@tlsgdplt], @@ -5224,15 +5252,15 @@ if test x"$enable_plugin" = x"yes"; then AC_MSG_CHECKING([for exported symbols]) if test "x$export_sym_check" != x; then echo "int main() {return 0;} int foobar() {return 0;}" > conftest.c - ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest > /dev/null 2>&1 - if $export_sym_check conftest | grep foobar > /dev/null; then + ${CC} ${CFLAGS} ${LDFLAGS} conftest.c -o conftest$ac_exeext > /dev/null 2>&1 + if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then : # No need to use a flag AC_MSG_RESULT([yes]) else AC_MSG_RESULT([yes]) AC_MSG_CHECKING([for -rdynamic]) - ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest > /dev/null 2>&1 - if $export_sym_check conftest | grep foobar > /dev/null; then + ${CC} ${CFLAGS} ${LDFLAGS} -rdynamic conftest.c -o conftest$ac_exeext > /dev/null 2>&1 + if $export_sym_check conftest$ac_exeext | grep -q foobar > /dev/null; then plugin_rdynamic=yes pluginlibs="-rdynamic" else diff --git a/gcc-4.8/gcc/cp/ChangeLog b/gcc-4.8/gcc/cp/ChangeLog index 2ee24e21e..c4d2dee85 100644 --- a/gcc-4.8/gcc/cp/ChangeLog +++ b/gcc-4.8/gcc/cp/ChangeLog @@ -1,3 +1,197 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-05-13 Jason Merrill + + PR c++/60708 + * call.c (build_array_conv): Call complete_type. + + PR c++/60713 + * typeck2.c (PICFLAG_SIDE_EFFECTS): New. + (picflag_from_initializer): Return it. + (process_init_constructor): Handle it. + + PR c++/60628 + * decl.c (create_array_type_for_decl): Complain about array of auto. + + PR c++/60367 + * call.c (convert_default_arg): Remove special handling for + CONSTRUCTOR. + +2014-04-28 Daniel Gutson + + * typeck.c (build_reinterpret_cast_1): Pass proper argument to + warn() in pedantic. + +2014-02-28 Jason Merrill + + PR c++/58845 + * typeck.c (cp_build_binary_op): Sorry on vector&&vector. + +2014-02-26 Jason Merrill + + PR c++/60182 + * pt.c (unify): Ignore alias templates when deducing a template + template parameter. + +2014-02-24 Jason Merrill + + PR c++/60146 + * pt.c (tsubst_omp_for_iterator): Don't let substitution of the + DECL_EXPR initialize a non-class iterator. + +2014-02-24 Fabien Chêne + PR c++/37140 + * parser.c (cp_parser_nonclass_name): Call strip_using_decl and + move the code handling dependent USING_DECLs... + * name-lookup.c (strip_using_decl): ...Here. + +2014-02-21 Jason Merrill + + PR c++/60108 + * semantics.c (expand_or_defer_fn_1): Check DECL_DEFAULTED_FN. + + PR c++/60187 + * parser.c (cp_parser_enum_specifier): Call + check_for_bare_parameter_packs. + + PR c++/60216 + * pt.c (register_specialization): Copy DECL_DELETED_FN to clones. + + PR c++/60219 + * pt.c (coerce_template_parms): Bail if argument packing fails. + + PR c++/60248 + * mangle.c (mangle_decl): Don't make an alias for a TYPE_DECL. + +2014-02-20 Jason Merrill + + PR c++/60274 + Revert: + PR c++/58606 + * pt.c (template_parm_to_arg): Call convert_from_reference. + (tsubst_template_arg): Don't strip reference refs. + +2014-02-20 Kai Tietz + + PR c++/58873 + * parser.c (cp_parser_functional_cast): Treat NULL_TREE + valued type argument as error_mark_node. + + PR c++/58835 + * semantics.c (finish_fname): Handle error_mark_node. + +2014-02-19 Jason Merrill + + PR c++/60046 + * pt.c (maybe_instantiate_noexcept): Don't instantiate exception + spec from template context. + +2014-01-31 Jason Merrill + + PR c++/58672 + * decl2.c (handle_tls_init): Handle null init fn. + + PR c++/55800 + * decl2.c (get_tls_init_fn): Copy DECL_EXTERNAL from the variable. + + PR c++/59646 + * call.c (convert_like_real) [ck_aggr]: Set TARGET_EXPR_LIST_INIT_P. + [ck_list]: Check for error_mark_node. + + PR c++/57043 + * pt.c (fn_type_unification): Don't do DEDUCE_EXACT check + during partial ordering. + +2014-01-30 Jason Merrill + + PR c++/57899 + * pt.c (instantiate_template_1): Save/restore local_specializations. + +2014-01-29 Jason Merrill + + PR c++/59989 + * pt.c (expand_template_argument_pack): Correct + non_default_args_count calculation. + + PR c++/58466 + * pt.c (unify_pack_expansion): Call expand_template_argument_pack. + +2014-01-28 Jason Merrill + + PR c++/58632 + * decl.c (lookup_and_check_tag): Ignore template parameters if + scope == ts_current. + * pt.c (check_template_shadow): Don't complain about the injected + class name. + +2014-01-27 Jason Merrill + + PR c++/54652 + * decl.c (duplicate_decls): Always use oldtype for TYPE_DECL. + + PR c++/58504 + * pt.c (tsubst_copy_and_build) [TRAIT_EXPR]: Use tsubst for + types. + + PR c++/58606 + * pt.c (template_parm_to_arg): Call convert_from_reference. + (tsubst_template_arg): Don't strip reference refs. + + PR c++/58639 + * call.c (build_aggr_conv): Reject value-initialization of reference. + + PR c++/58812 + * call.c (convert_like_real): Give helpful error about excess braces + for reference binding, too. + + PR c++/58814 + * typeck.c (cp_build_modify_expr): Make the RHS an rvalue before + stabilizing. + + PR c++/58837 + * typeck.c (cp_truthvalue_conversion): Use explicit comparison for + FUNCTION_DECL. + + PR c++/59097 + * decl.c (compute_array_index_type): Don't call + maybe_constant_value for a non-integral expression. + + PR c++/58965 + * mangle.c (write_guarded_var_name): Handle null DECL_NAME. + +2014-01-24 Paolo Carlini + + PR c++/57524 + * name-lookup.c (push_using_directive): Use timevar_cond_start. + +2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * semantics.c (finish_omp_clauses): Reject MIN_EXPR, MAX_EXPR, + BIT_AND_EXPR, BIT_IOR_EXPR and BIT_XOR_EXPR on COMPLEX_TYPEs. + +2014-01-20 Marek Polacek + + Backported from mainline + 2014-01-17 Marek Polacek + + PR c++/59838 + * cvt.c (ocp_convert): Don't segfault on non-existing + ENUM_UNDERLYING_TYPE. + +2014-01-10 Paolo Carlini + + PR c++/56060 + PR c++/59730 + * pt.c (type_dependent_expression_p): Handle EXPR_PACK_EXPANSION. + +2013-12-12 Jason Merrill + + PR c++/58954 + * pt.c (resolve_overloaded_unification): Discard access checks. + 2013-12-05 Jason Merrill PR c++/59044 @@ -5,6 +199,74 @@ * pt.c (most_specialized_class): Use the partially instantiated template for deduction. Drop the TMPL parameter. +2013-12-04 Jakub Jelinek + + PR c++/59268 + * pt.c (tsubst_copy_and_build): Handle POINTER_PLUS_EXPR. + +2013-11-27 Tom de Vries + Marc Glisse + + PR c++/59032 + * typeck.c (cp_build_unary_op): Allow vector increment and decrement. + +2013-11-27 Tom de Vries + Marc Glisse + + PR middle-end/59037 + * semantics.c (cxx_fold_indirect_ref): Don't create out-of-bounds + BIT_FIELD_REF. + +2013-11-28 Jakub Jelinek + + PR c++/59297 + * semantics.c (finish_omp_atomic): Call finish_expr_stmt + rather than add_stmt. + +2013-11-23 Easwaran Raman + + PR c++/59031 + * call.c (build_new_method_call_1): Comnpare function context + with BASELINK_BINFO type rather than instance type before + marking the call with LOOKUP_NONVIRTUAL. + +2013-10-31 Jason Merrill + + PR c++/58162 + * parser.c (cp_parser_late_parse_one_default_arg): Set + TARGET_EXPR_DIRECT_INIT_P. + +2013-11-11 Paolo Carlini + + * cvt.c (cp_convert_to_pointer): Call build_ptrmemfunc before + maybe_warn_zero_as_null_pointer_constant to avoid duplicate + -Wzero-as-null-pointer-constant diagnostics. + + * typeck.c (build_ptrmemfunc): Use cp_build_c_cast. + +2013-10-25 Tom de Vries + + PR c++/58282 + * except.c (build_must_not_throw_expr): Handle + flag_exceptions. + +2013-10-17 Paolo Carlini + + PR c++/58596 + * semantics.c (lambda_expr_this_capture): Handle NSDMIs in the + cp_unevaluated_operand case. + +2013-10-16 Paolo Carlini + + PR c++/58633 + * parser.c (cp_parser_pseudo_destructor_name): Revert r174385 changes. + +2013-10-16 Jason Merrill + + PR c++/57850 + * decl2.c (dump_tu): Split out from... + (cp_write_global_declarations): ...here. Call it in PCH mode. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/cp/call.c b/gcc-4.8/gcc/cp/call.c index a5be421fe..7c46cb5f4 100644 --- a/gcc-4.8/gcc/cp/call.c +++ b/gcc-4.8/gcc/cp/call.c @@ -892,6 +892,9 @@ build_aggr_conv (tree type, tree ctor, int flags, tsubst_flags_t complain) if (i < CONSTRUCTOR_NELTS (ctor)) val = CONSTRUCTOR_ELT (ctor, i)->value; + else if (TREE_CODE (ftype) == REFERENCE_TYPE) + /* Value-initialization of reference is ill-formed. */ + return NULL; else { if (empty_ctor == NULL_TREE) @@ -940,6 +943,9 @@ build_array_conv (tree type, tree ctor, int flags, tsubst_flags_t complain) bool user = false; enum conversion_rank rank = cr_exact; + /* We might need to propagate the size from the element to the array. */ + complete_type (type); + if (TYPE_DOMAIN (type)) { unsigned HOST_WIDE_INT alen = tree_low_cst (array_type_nelts_top (type), 1); @@ -5806,9 +5812,11 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, && convs->kind != ck_ambig && (convs->kind != ck_ref_bind || convs->user_conv_p) - && convs->kind != ck_rvalue + && (convs->kind != ck_rvalue + || SCALAR_TYPE_P (totype)) && convs->kind != ck_base) { + bool complained = false; conversion *t = convs; /* Give a helpful error if this is bad because of excess braces. */ @@ -5816,7 +5824,14 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, && SCALAR_TYPE_P (totype) && CONSTRUCTOR_NELTS (expr) > 0 && BRACE_ENCLOSED_INITIALIZER_P (CONSTRUCTOR_ELT (expr, 0)->value)) - permerror (loc, "too many braces around initializer for %qT", totype); + { + complained = true; + permerror (loc, "too many braces around initializer " + "for %qT", totype); + while (BRACE_ENCLOSED_INITIALIZER_P (expr) + && CONSTRUCTOR_NELTS (expr) == 1) + expr = CONSTRUCTOR_ELT (expr, 0)->value; + } for (; t ; t = next_conversion (t)) { @@ -5853,6 +5868,7 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, break; } + if (!complained) permerror (loc, "invalid conversion from %qT to %qT", TREE_TYPE (expr), totype); if (fn) @@ -5999,6 +6015,8 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, to avoid the error about taking the address of a temporary. */ array = cp_build_addr_expr (array, complain); array = cp_convert (build_pointer_type (elttype), array, complain); + if (array == error_mark_node) + return error_mark_node; /* Build up the initializer_list object. */ totype = complete_type (totype); @@ -6023,8 +6041,11 @@ convert_like_real (conversion *convs, tree expr, tree fn, int argnum, return fold_if_not_in_template (expr); } expr = reshape_init (totype, expr, complain); - return get_target_expr_sfinae (digest_init (totype, expr, complain), + expr = get_target_expr_sfinae (digest_init (totype, expr, complain), complain); + if (expr != error_mark_node) + TARGET_EXPR_LIST_INIT_P (expr) = true; + return expr; default: break; @@ -6405,20 +6426,10 @@ convert_default_arg (tree type, tree arg, tree fn, int parmnum, /* We must make a copy of ARG, in case subsequent processing alters any part of it. */ arg = break_out_target_exprs (arg); - if (TREE_CODE (arg) == CONSTRUCTOR) - { - arg = digest_init (type, arg, complain); - arg = convert_for_initialization (0, type, arg, LOOKUP_IMPLICIT, - ICR_DEFAULT_ARGUMENT, fn, parmnum, - complain); - } - else - { arg = convert_for_initialization (0, type, arg, LOOKUP_IMPLICIT, ICR_DEFAULT_ARGUMENT, fn, parmnum, complain); arg = convert_for_arg_passing (type, arg, complain); - } pop_deferring_access_checks(); pop_defarg_context (); @@ -7414,7 +7425,7 @@ build_new_method_call_1 (tree instance, tree fns, vec **args, struct z_candidate *candidates = 0, *cand; tree explicit_targs = NULL_TREE; tree basetype = NULL_TREE; - tree access_binfo; + tree access_binfo, binfo; tree optype; tree first_mem_arg = NULL_TREE; tree instance_ptr; @@ -7454,6 +7465,7 @@ build_new_method_call_1 (tree instance, tree fns, vec **args, if (!conversion_path) conversion_path = BASELINK_BINFO (fns); access_binfo = BASELINK_ACCESS_BINFO (fns); + binfo = BASELINK_BINFO (fns); optype = BASELINK_OPTYPE (fns); fns = BASELINK_FUNCTIONS (fns); if (TREE_CODE (fns) == TEMPLATE_ID_EXPR) @@ -7697,13 +7709,13 @@ build_new_method_call_1 (tree instance, tree fns, vec **args, { /* Optimize away vtable lookup if we know that this function can't be overridden. We need to check if - the context and the instance type are the same, + the context and the type where we found fn are the same, actually FN might be defined in a different class type because of a using-declaration. In this case, we do not want to perform a non-virtual call. */ if (DECL_VINDEX (fn) && ! (flags & LOOKUP_NONVIRTUAL) && same_type_ignoring_top_level_qualifiers_p - (DECL_CONTEXT (fn), TREE_TYPE (instance)) + (DECL_CONTEXT (fn), BINFO_TYPE (binfo)) && resolves_to_fixed_type_p (instance, 0)) flags |= LOOKUP_NONVIRTUAL; if (explicit_targs) diff --git a/gcc-4.8/gcc/cp/cvt.c b/gcc-4.8/gcc/cp/cvt.c index 8c03e2086..179650711 100644 --- a/gcc-4.8/gcc/cp/cvt.c +++ b/gcc-4.8/gcc/cp/cvt.c @@ -203,13 +203,13 @@ cp_convert_to_pointer (tree type, tree expr, tsubst_flags_t complain) if (null_ptr_cst_p (expr)) { - if (complain & tf_warning) - maybe_warn_zero_as_null_pointer_constant (expr, loc); - if (TYPE_PTRMEMFUNC_P (type)) return build_ptrmemfunc (TYPE_PTRMEMFUNC_FN_TYPE (type), expr, 0, /*c_cast_p=*/false, complain); + if (complain & tf_warning) + maybe_warn_zero_as_null_pointer_constant (expr, loc); + /* A NULL pointer-to-data-member is represented by -1, not by zero. */ tree val = (TYPE_PTRDATAMEM_P (type) @@ -743,6 +743,7 @@ ocp_convert (tree type, tree expr, int convtype, int flags, unspecified. */ if ((complain & tf_warning) && TREE_CODE (e) == INTEGER_CST + && ENUM_UNDERLYING_TYPE (type) && !int_fits_type_p (e, ENUM_UNDERLYING_TYPE (type))) warning_at (loc, OPT_Wconversion, "the result of the conversion is unspecified because " diff --git a/gcc-4.8/gcc/cp/decl.c b/gcc-4.8/gcc/cp/decl.c index 893fbd161..e487f887d 100644 --- a/gcc-4.8/gcc/cp/decl.c +++ b/gcc-4.8/gcc/cp/decl.c @@ -1867,9 +1867,9 @@ duplicate_decls (tree newdecl, tree olddecl, bool newdecl_is_friend) /* Merge the data types specified in the two decls. */ newtype = merge_types (TREE_TYPE (newdecl), TREE_TYPE (olddecl)); - /* If merge_types produces a non-typedef type, just use the old type. */ - if (TREE_CODE (newdecl) == TYPE_DECL - && newtype == DECL_ORIGINAL_TYPE (newdecl)) + /* For typedefs use the old type, as the new type's DECL_NAME points + at newdecl, which will be ggc_freed. */ + if (TREE_CODE (newdecl) == TYPE_DECL) newtype = oldtype; if (TREE_CODE (newdecl) == VAR_DECL) @@ -8193,7 +8193,9 @@ compute_array_index_type (tree name, tree size, tsubst_flags_t complain) abi_1_itype = error_mark_node; } + if (INTEGRAL_OR_UNSCOPED_ENUMERATION_TYPE_P (type)) size = maybe_constant_value (size); + if (!TREE_CONSTANT (size)) size = osize; } @@ -8473,6 +8475,14 @@ create_array_type_for_decl (tree name, tree type, tree size) return error_mark_node; } + /* 8.3.4p1: ...if the type of the identifier of D contains the auto + type-specifier, the program is ill-formed. */ + if (type_uses_auto (type)) + { + error ("%qD declared as array of %qT", name, type); + return error_mark_node; + } + /* Figure out the index type for the array. */ if (size) itype = compute_array_index_type (name, size, tf_warning_or_error); @@ -11891,7 +11901,10 @@ lookup_and_check_tag (enum tag_types tag_code, tree name, if (decl && (DECL_CLASS_TEMPLATE_P (decl) - || DECL_TEMPLATE_TEMPLATE_PARM_P (decl))) + /* If scope is ts_current we're defining a class, so ignore a + template template parameter. */ + || (scope != ts_current + && DECL_TEMPLATE_TEMPLATE_PARM_P (decl)))) decl = DECL_TEMPLATE_RESULT (decl); if (decl && TREE_CODE (decl) == TYPE_DECL) diff --git a/gcc-4.8/gcc/cp/decl2.c b/gcc-4.8/gcc/cp/decl2.c index 628be934b..7dd98c07e 100644 --- a/gcc-4.8/gcc/cp/decl2.c +++ b/gcc-4.8/gcc/cp/decl2.c @@ -2884,7 +2884,7 @@ get_tls_init_fn (tree var) TREE_PUBLIC (fn) = TREE_PUBLIC (var); DECL_ARTIFICIAL (fn) = true; DECL_COMDAT (fn) = DECL_COMDAT (var); - DECL_EXTERNAL (fn) = true; + DECL_EXTERNAL (fn) = DECL_EXTERNAL (var); if (DECL_ONE_ONLY (var)) make_decl_one_only (fn, cxx_comdat_group (fn)); if (TREE_PUBLIC (var)) @@ -3946,6 +3946,8 @@ handle_tls_init (void) if (TREE_PUBLIC (var)) { tree single_init_fn = get_tls_init_fn (var); + if (single_init_fn == NULL_TREE) + continue; cgraph_node *alias = cgraph_same_body_alias (cgraph_get_create_node (fn), single_init_fn, fn); @@ -3960,6 +3962,22 @@ handle_tls_init (void) expand_or_defer_fn (finish_function (0)); } +/* The entire file is now complete. If requested, dump everything + to a file. */ + +static void +dump_tu (void) +{ + int flags; + FILE *stream = dump_begin (TDI_tu, &flags); + + if (stream) + { + dump_node (global_namespace, flags & ~TDF_SLIM, stream); + dump_end (TDI_tu, stream); + } +} + /* This routine is called at the end of compilation. Its job is to create all the code needed to initialize and destroy the global aggregates. We do the destruction @@ -3990,6 +4008,7 @@ cp_write_global_declarations (void) if (pch_file) { c_common_write_pch (); + dump_tu (); return; } @@ -4359,16 +4378,7 @@ cp_write_global_declarations (void) /* The entire file is now complete. If requested, dump everything to a file. */ - { - int flags; - FILE *stream = dump_begin (TDI_tu, &flags); - - if (stream) - { - dump_node (global_namespace, flags & ~TDF_SLIM, stream); - dump_end (TDI_tu, stream); - } - } + dump_tu (); if (flag_detailed_statistics) { diff --git a/gcc-4.8/gcc/cp/except.c b/gcc-4.8/gcc/cp/except.c index 216ec103f..604f274fb 100644 --- a/gcc-4.8/gcc/cp/except.c +++ b/gcc-4.8/gcc/cp/except.c @@ -380,6 +380,9 @@ build_must_not_throw_expr (tree body, tree cond) { tree type = body ? TREE_TYPE (body) : void_type_node; + if (!flag_exceptions) + return body; + if (cond && !value_dependent_expression_p (cond)) { cond = cxx_constant_value (cond); diff --git a/gcc-4.8/gcc/cp/mangle.c b/gcc-4.8/gcc/cp/mangle.c index dd5ed8d0d..26d360396 100644 --- a/gcc-4.8/gcc/cp/mangle.c +++ b/gcc-4.8/gcc/cp/mangle.c @@ -3480,6 +3480,7 @@ mangle_decl (const tree decl) if (G.need_abi_warning /* Don't do this for a fake symbol we aren't going to emit anyway. */ + && TREE_CODE (decl) != TYPE_DECL && !DECL_MAYBE_IN_CHARGE_CONSTRUCTOR_P (decl) && !DECL_MAYBE_IN_CHARGE_DESTRUCTOR_P (decl)) { @@ -3775,7 +3776,8 @@ mangle_conv_op_name_for_type (const tree type) static void write_guarded_var_name (const tree variable) { - if (strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0) + if (DECL_NAME (variable) + && strncmp (IDENTIFIER_POINTER (DECL_NAME (variable)), "_ZGR", 4) == 0) /* The name of a guard variable for a reference temporary should refer to the reference, not the temporary. */ write_string (IDENTIFIER_POINTER (DECL_NAME (variable)) + 4); diff --git a/gcc-4.8/gcc/cp/name-lookup.c b/gcc-4.8/gcc/cp/name-lookup.c index c121a4163..da167ec41 100644 --- a/gcc-4.8/gcc/cp/name-lookup.c +++ b/gcc-4.8/gcc/cp/name-lookup.c @@ -394,7 +394,8 @@ pop_binding (tree id, tree decl) } } -/* Strip non dependent using declarations. */ +/* Strip non dependent using declarations. If DECL is dependent, + surreptitiously create a typename_type and return it. */ tree strip_using_decl (tree decl) @@ -404,6 +405,23 @@ strip_using_decl (tree decl) while (TREE_CODE (decl) == USING_DECL && !DECL_DEPENDENT_P (decl)) decl = USING_DECL_DECLS (decl); + + if (TREE_CODE (decl) == USING_DECL && DECL_DEPENDENT_P (decl) + && USING_DECL_TYPENAME_P (decl)) + { + /* We have found a type introduced by a using + declaration at class scope that refers to a dependent + type. + + using typename :: [opt] nested-name-specifier unqualified-id ; + */ + decl = make_typename_type (TREE_TYPE (decl), + DECL_NAME (decl), + typename_type, tf_error); + if (decl != error_mark_node) + decl = TYPE_NAME (decl); + } + return decl; } @@ -5605,9 +5623,9 @@ static tree push_using_directive (tree used) { tree ret; - timevar_start (TV_NAME_LOOKUP); + bool subtime = timevar_cond_start (TV_NAME_LOOKUP); ret = push_using_directive_1 (used); - timevar_stop (TV_NAME_LOOKUP); + timevar_cond_stop (TV_NAME_LOOKUP, subtime); return ret; } diff --git a/gcc-4.8/gcc/cp/parser.c b/gcc-4.8/gcc/cp/parser.c index b6322788f..3c1dec529 100644 --- a/gcc-4.8/gcc/cp/parser.c +++ b/gcc-4.8/gcc/cp/parser.c @@ -6421,10 +6421,6 @@ cp_parser_pseudo_destructor_name (cp_parser* parser, /* Look for the `~'. */ cp_parser_require (parser, CPP_COMPL, RT_COMPL); - /* Once we see the ~, this has to be a pseudo-destructor. */ - if (!processing_template_decl && !cp_parser_error_occurred (parser)) - cp_parser_commit_to_tentative_parse (parser); - /* Look for the type-name again. We are not responsible for checking that it matches the first type-name. */ *type = cp_parser_nonclass_name (parser); @@ -14168,25 +14164,7 @@ cp_parser_nonclass_name (cp_parser* parser) /* Look up the type-name. */ type_decl = cp_parser_lookup_name_simple (parser, identifier, token->location); - if (TREE_CODE (type_decl) == USING_DECL) - { - if (!DECL_DEPENDENT_P (type_decl)) type_decl = strip_using_decl (type_decl); - else if (USING_DECL_TYPENAME_P (type_decl)) - { - /* We have found a type introduced by a using - declaration at class scope that refers to a dependent - type. - - using typename :: [opt] nested-name-specifier unqualified-id ; - */ - type_decl = make_typename_type (TREE_TYPE (type_decl), - DECL_NAME (type_decl), - typename_type, tf_error); - if (type_decl != error_mark_node) - type_decl = TYPE_NAME (type_decl); - } - } if (TREE_CODE (type_decl) != TYPE_DECL && (objc_is_id (identifier) || objc_is_class_name (identifier))) @@ -14742,7 +14720,8 @@ cp_parser_enum_specifier (cp_parser* parser) { underlying_type = grokdeclarator (NULL, &type_specifiers, TYPENAME, /*initialized=*/0, NULL); - if (underlying_type == error_mark_node) + if (underlying_type == error_mark_node + || check_for_bare_parameter_packs (underlying_type)) underlying_type = NULL_TREE; } } @@ -22209,6 +22188,9 @@ cp_parser_functional_cast (cp_parser* parser, tree type) tree cast; bool nonconst_p; + if (!type) + type = error_mark_node; + if (cp_lexer_next_token_is (parser->lexer, CPP_OPEN_BRACE)) { maybe_warn_cpp0x (CPP0X_INITIALIZER_LISTS); @@ -22576,6 +22558,9 @@ cp_parser_late_parse_one_default_arg (cp_parser *parser, tree decl, && CONSTRUCTOR_IS_DIRECT_INIT (parsed_arg)) flags = LOOKUP_NORMAL; parsed_arg = digest_init_flags (TREE_TYPE (decl), parsed_arg, flags); + if (TREE_CODE (parsed_arg) == TARGET_EXPR) + /* This represents the whole initialization. */ + TARGET_EXPR_DIRECT_INIT_P (parsed_arg) = true; } } diff --git a/gcc-4.8/gcc/cp/pt.c b/gcc-4.8/gcc/cp/pt.c index 5885021a4..c44e3d0b2 100644 --- a/gcc-4.8/gcc/cp/pt.c +++ b/gcc-4.8/gcc/cp/pt.c @@ -1419,6 +1419,8 @@ register_specialization (tree spec, tree tmpl, tree args, bool is_friend, = DECL_DECLARED_INLINE_P (fn); DECL_SOURCE_LOCATION (clone) = DECL_SOURCE_LOCATION (fn); + DECL_DELETED_FN (clone) + = DECL_DELETED_FN (fn); } check_specialization_namespace (tmpl); @@ -3436,7 +3438,7 @@ expand_template_argument_pack (tree args) for (i = 0; i < num_packed; ++i, ++out_arg) TREE_VEC_ELT (result_args, out_arg) = TREE_VEC_ELT(packed, i); if (non_default_args_count > 0) - non_default_args_count += num_packed; + non_default_args_count += num_packed - 1; } else { @@ -3491,6 +3493,11 @@ check_template_shadow (tree decl) || TEMPLATE_PARMS_FOR_INLINE (current_template_parms)) return true; + /* Don't complain about the injected class name, as we've already + complained about the class itself. */ + if (DECL_SELF_REFERENCE_P (decl)) + return false; + error ("declaration of %q+#D", decl); error (" shadows template parm %q+#D", olddecl); return false; @@ -6672,6 +6679,8 @@ coerce_template_parms (tree parms, /* Store this argument. */ if (arg == error_mark_node) lost++; + if (lost) + break; TREE_VEC_ELT (new_inner_args, parm_idx) = arg; /* We are done with all of the arguments. */ @@ -12694,27 +12703,43 @@ tsubst_omp_for_iterator (tree t, int i, tree declv, tree initv, tsubst_expr ((NODE), args, complain, in_decl, \ integral_constant_expression_p) tree decl, init, cond, incr; - bool init_decl; init = TREE_VEC_ELT (OMP_FOR_INIT (t), i); gcc_assert (TREE_CODE (init) == MODIFY_EXPR); decl = TREE_OPERAND (init, 0); init = TREE_OPERAND (init, 1); - /* Do this before substituting into decl to handle 'auto'. */ - init_decl = (init && TREE_CODE (init) == DECL_EXPR); - init = RECUR (init); - decl = RECUR (decl); - if (init_decl) + tree decl_expr = NULL_TREE; + if (init && TREE_CODE (init) == DECL_EXPR) { - gcc_assert (!processing_template_decl); - init = DECL_INITIAL (decl); - DECL_INITIAL (decl) = NULL_TREE; + /* We need to jump through some hoops to handle declarations in the + for-init-statement, since we might need to handle auto deduction, + but we need to keep control of initialization. */ + decl_expr = init; + init = DECL_INITIAL (DECL_EXPR_DECL (init)); + decl = tsubst_decl (decl, args, complain); } + else + decl = RECUR (decl); + init = RECUR (init); + + tree auto_node = type_uses_auto (TREE_TYPE (decl)); + if (auto_node && init) + TREE_TYPE (decl) + = do_auto_deduction (TREE_TYPE (decl), init, auto_node); gcc_assert (!type_dependent_expression_p (decl)); if (!CLASS_TYPE_P (TREE_TYPE (decl))) { + if (decl_expr) + { + /* Declare the variable, but don't let that initialize it. */ + tree init_sav = DECL_INITIAL (DECL_EXPR_DECL (decl_expr)); + DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = NULL_TREE; + RECUR (decl_expr); + DECL_INITIAL (DECL_EXPR_DECL (decl_expr)) = init_sav; + } + cond = RECUR (TREE_VEC_ELT (OMP_FOR_COND (t), i)); incr = TREE_VEC_ELT (OMP_FOR_INCR (t), i); if (TREE_CODE (incr) == MODIFY_EXPR) @@ -12731,7 +12756,13 @@ tsubst_omp_for_iterator (tree t, int i, tree declv, tree initv, return; } - if (init && !init_decl) + if (decl_expr) + { + /* Declare and initialize the variable. */ + RECUR (decl_expr); + init = NULL_TREE; + } + else if (init) { tree c; for (c = *clauses; c ; c = OMP_CLAUSE_CHAIN (c)) @@ -13710,6 +13741,10 @@ tsubst_copy_and_build (tree t, RETURN (r); } + case POINTER_PLUS_EXPR: + return fold_build_pointer_plus (RECUR (TREE_OPERAND (t, 0)), + RECUR (TREE_OPERAND (t, 1))); + case SCOPE_REF: RETURN (tsubst_qualified_id (t, args, complain, in_decl, /*done=*/true, /*address_p=*/false)); @@ -14471,12 +14506,12 @@ tsubst_copy_and_build (tree t, case TRAIT_EXPR: { - tree type1 = tsubst_copy (TRAIT_EXPR_TYPE1 (t), args, + tree type1 = tsubst (TRAIT_EXPR_TYPE1 (t), args, complain, in_decl); tree type2 = TRAIT_EXPR_TYPE2 (t); if (type2) - type2 = tsubst_copy (type2, args, complain, in_decl); + type2 = tsubst (type2, args, complain, in_decl); RETURN (finish_trait_expr (TRAIT_EXPR_KIND (t), type1, type2)); } @@ -14778,6 +14813,8 @@ instantiate_template_1 (tree tmpl, tree orig_args, tsubst_flags_t complain) /* Instantiation of the function happens in the context of the function template, not the context of the overload resolution we're doing. */ push_to_top_level (); + struct pointer_map_t *saved_local_specializations = local_specializations; + local_specializations = NULL; /* If there are dependent arguments, e.g. because we're doing partial ordering, make sure processing_template_decl stays set. */ if (uses_template_parms (targ_ptr)) @@ -14793,6 +14830,7 @@ instantiate_template_1 (tree tmpl, tree orig_args, tsubst_flags_t complain) targ_ptr, complain, gen_tmpl); if (DECL_CLASS_SCOPE_P (gen_tmpl)) pop_nested_class (); + local_specializations = saved_local_specializations; pop_from_top_level (); if (fndecl == error_mark_node) @@ -15192,8 +15230,11 @@ fn_type_unification (tree fn, /* If we're looking for an exact match, check that what we got is indeed an exact match. It might not be if some template - parameters are used in non-deduced contexts. */ - if (strict == DEDUCE_EXACT) + parameters are used in non-deduced contexts. But don't check + for an exact match if we have dependent template arguments; + in that case we're doing partial ordering, and we already know + that we have two candidates that will provide the actual type. */ + if (strict == DEDUCE_EXACT && !any_dependent_template_arguments_p (targs)) { tree substed = TREE_TYPE (decl); unsigned int i; @@ -15749,7 +15790,7 @@ resolve_overloaded_unification (tree tparms, if (subargs != error_mark_node && !any_dependent_template_arguments_p (subargs)) { - elem = tsubst (TREE_TYPE (fn), subargs, tf_none, NULL_TREE); + elem = TREE_TYPE (instantiate_template (fn, subargs, tf_none)); if (try_one_overload (tparms, targs, tempargs, parm, elem, strict, sub_strict, addr_p, explain_p) && (!goodfn || !same_type_p (goodfn, elem))) @@ -16207,6 +16248,9 @@ unify_pack_expansion (tree tparms, tree targs, tree packed_parms, tree pattern = PACK_EXPANSION_PATTERN (parm); tree pack, packs = NULL_TREE; int i, start = TREE_VEC_LENGTH (packed_parms) - 1; + + packed_args = expand_template_argument_pack (packed_args); + int len = TREE_VEC_LENGTH (packed_args); /* Determine the parameter packs we will be deducing from the @@ -16574,9 +16618,11 @@ unify (tree tparms, tree targs, tree parm, tree arg, int strict, if (TREE_CODE (arg) != BOUND_TEMPLATE_TEMPLATE_PARM && !CLASSTYPE_SPECIALIZATION_OF_PRIMARY_TEMPLATE_P (arg)) return unify_template_deduction_failure (explain_p, parm, arg); - { tree parmvec = TYPE_TI_ARGS (parm); + /* An alias template name is never deduced. */ + if (TYPE_ALIAS_P (arg)) + arg = strip_typedefs (arg); tree argvec = INNERMOST_TEMPLATE_ARGS (TYPE_TI_ARGS (arg)); tree full_argvec = add_to_template_args (targs, argvec); tree parm_parms @@ -18552,6 +18598,10 @@ maybe_instantiate_noexcept (tree fn) { tree fntype, spec, noex, clone; + /* Don't instantiate a noexcept-specification from template context. */ + if (processing_template_decl) + return; + if (DECL_CLONED_FUNCTION_P (fn)) fn = DECL_CLONED_FUNCTION (fn); fntype = TREE_TYPE (fn); @@ -19954,6 +20004,10 @@ type_dependent_expression_p (tree expression) if (TREE_CODE (expression) == SCOPE_REF) return false; + /* Always dependent, on the number of arguments if nothing else. */ + if (TREE_CODE (expression) == EXPR_PACK_EXPANSION) + return true; + if (BASELINK_P (expression)) expression = BASELINK_FUNCTIONS (expression); diff --git a/gcc-4.8/gcc/cp/semantics.c b/gcc-4.8/gcc/cp/semantics.c index 580c609ac..0debc78e8 100644 --- a/gcc-4.8/gcc/cp/semantics.c +++ b/gcc-4.8/gcc/cp/semantics.c @@ -2501,7 +2501,8 @@ finish_fname (tree id) tree decl; decl = fname_decl (input_location, C_RID_CODE (id), id); - if (processing_template_decl && current_function_decl) + if (processing_template_decl && current_function_decl + && decl != error_mark_node) decl = DECL_NAME (decl); return decl; } @@ -3853,7 +3854,7 @@ expand_or_defer_fn_1 (tree fn) linkage of all functions, and as that causes writes to the data mapped in from the PCH file, it's advantageous to mark the functions at this point. */ - if (!DECL_IMPLICIT_INSTANTIATION (fn)) + if (!DECL_IMPLICIT_INSTANTIATION (fn) || DECL_DEFAULTED_FN (fn)) { /* This function must have external linkage, as otherwise DECL_INTERFACE_KNOWN would have been @@ -4291,7 +4292,8 @@ finish_omp_clauses (tree clauses) error ("%qE has invalid type for %", t); remove = true; } - else if (FLOAT_TYPE_P (TREE_TYPE (t))) + else if (FLOAT_TYPE_P (TREE_TYPE (t)) + || TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) { enum tree_code r_code = OMP_CLAUSE_REDUCTION_CODE (c); switch (r_code) @@ -4299,10 +4301,26 @@ finish_omp_clauses (tree clauses) case PLUS_EXPR: case MULT_EXPR: case MINUS_EXPR: + break; case MIN_EXPR: case MAX_EXPR: + if (TREE_CODE (TREE_TYPE (t)) == COMPLEX_TYPE) + r_code = ERROR_MARK; break; + case BIT_AND_EXPR: + case BIT_XOR_EXPR: + case BIT_IOR_EXPR: default: + r_code = ERROR_MARK; + break; + case TRUTH_ANDIF_EXPR: + case TRUTH_ORIF_EXPR: + if (FLOAT_TYPE_P (TREE_TYPE (t))) + r_code = ERROR_MARK; + break; + } + if (r_code == ERROR_MARK) + { error ("%qE has invalid type for %", t, operator_name_info[r_code].name); remove = true; @@ -5059,7 +5077,7 @@ finish_omp_atomic (enum tree_code code, enum tree_code opcode, tree lhs, } stmt = build2 (OMP_ATOMIC, void_type_node, integer_zero_node, stmt); } - add_stmt (stmt); + finish_expr_stmt (stmt); } void @@ -7543,7 +7561,7 @@ cxx_fold_indirect_ref (location_t loc, tree type, tree op0, bool *empty_base) unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT; tree index = bitsize_int (indexi); - if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type)) + if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type)) return fold_build3_loc (loc, BIT_FIELD_REF, type, op00, part_width, index); @@ -9481,7 +9499,14 @@ lambda_expr_this_capture (tree lambda) /* In unevaluated context this isn't an odr-use, so just return the nearest 'this'. */ if (cp_unevaluated_operand) + { + /* In an NSDMI the fake 'this' pointer that we're using for + parsing is in scope_chain. */ + if (LAMBDA_EXPR_EXTRA_SCOPE (lambda) + && TREE_CODE (LAMBDA_EXPR_EXTRA_SCOPE (lambda)) == FIELD_DECL) + return scope_chain->x_current_class_ptr; return lookup_name (this_identifier); + } /* Try to default capture 'this' if we can. */ if (!this_capture diff --git a/gcc-4.8/gcc/cp/typeck.c b/gcc-4.8/gcc/cp/typeck.c index 1a64b6890..2fa47025b 100644 --- a/gcc-4.8/gcc/cp/typeck.c +++ b/gcc-4.8/gcc/cp/typeck.c @@ -4103,6 +4103,11 @@ cp_build_binary_op (location_t location, case TRUTH_ORIF_EXPR: case TRUTH_AND_EXPR: case TRUTH_OR_EXPR: + if (TREE_CODE (type0) == VECTOR_TYPE || TREE_CODE (type1) == VECTOR_TYPE) + { + sorry ("logical operation on vector type"); + return error_mark_node; + } result_type = boolean_type_node; break; @@ -5010,7 +5015,10 @@ tree cp_truthvalue_conversion (tree expr) { tree type = TREE_TYPE (expr); - if (TYPE_PTRDATAMEM_P (type)) + if (TYPE_PTRDATAMEM_P (type) + /* Avoid ICE on invalid use of non-static member function. */ + || (TREE_CODE (expr) == FUNCTION_DECL + && DECL_NONSTATIC_MEMBER_FUNCTION_P (expr))) return build_binary_op (EXPR_LOCATION (expr), NE_EXPR, expr, nullptr_node, 1); else if (TYPE_PTR_P (type) || TYPE_PTRMEMFUNC_P (type)) @@ -5588,7 +5596,9 @@ cp_build_unary_op (enum tree_code code, tree xarg, int noconvert, inc = cxx_sizeof_nowarn (TREE_TYPE (argtype)); } else - inc = integer_one_node; + inc = (TREE_CODE (argtype) == VECTOR_TYPE + ? build_one_cst (argtype) + : integer_one_node); inc = cp_convert (argtype, inc, complain); @@ -6639,7 +6649,7 @@ build_reinterpret_cast_1 (tree type, tree expr, bool c_cast_p, where possible, and it is necessary in some cases. DR 195 addresses this issue, but as of 2004/10/26 is still in drafting. */ - warning (0, "ISO C++ forbids casting between pointer-to-function and pointer-to-object"); + warning (OPT_Wpedantic, "ISO C++ forbids casting between pointer-to-function and pointer-to-object"); return fold_if_not_in_template (build_nop (type, expr)); } else if (TREE_CODE (type) == VECTOR_TYPE) @@ -7194,8 +7204,7 @@ cp_build_modify_expr (tree lhs, enum tree_code modifycode, tree rhs, side effect associated with any single compound assignment operator. -- end note ] */ lhs = stabilize_reference (lhs); - if (TREE_SIDE_EFFECTS (rhs)) - rhs = mark_rvalue_use (rhs); + rhs = rvalue (rhs); rhs = stabilize_expr (rhs, &init); newrhs = cp_build_binary_op (input_location, modifycode, lhs, rhs, @@ -7611,7 +7620,7 @@ build_ptrmemfunc (tree type, tree pfn, int force, bool c_cast_p, /* Handle null pointer to member function conversions. */ if (null_ptr_cst_p (pfn)) { - pfn = build_c_cast (input_location, type, pfn); + pfn = cp_build_c_cast (type, pfn, complain); return build_ptrmemfunc1 (to_type, integer_zero_node, pfn); diff --git a/gcc-4.8/gcc/cp/typeck2.c b/gcc-4.8/gcc/cp/typeck2.c index 9c9f0751f..e7e1246e1 100644 --- a/gcc-4.8/gcc/cp/typeck2.c +++ b/gcc-4.8/gcc/cp/typeck2.c @@ -1015,6 +1015,7 @@ digest_init_flags (tree type, tree init, int flags) #define PICFLAG_ERRONEOUS 1 #define PICFLAG_NOT_ALL_CONSTANT 2 #define PICFLAG_NOT_ALL_SIMPLE 4 +#define PICFLAG_SIDE_EFFECTS 8 /* Given an initializer INIT, return the flag (PICFLAG_*) which better describe it. */ @@ -1025,7 +1026,12 @@ picflag_from_initializer (tree init) if (init == error_mark_node) return PICFLAG_ERRONEOUS; else if (!TREE_CONSTANT (init)) + { + if (TREE_SIDE_EFFECTS (init)) + return PICFLAG_SIDE_EFFECTS; + else return PICFLAG_NOT_ALL_CONSTANT; + } else if (!initializer_constant_valid_p (init, TREE_TYPE (init))) return PICFLAG_NOT_ALL_SIMPLE; return 0; @@ -1392,7 +1398,12 @@ process_init_constructor (tree type, tree init, tsubst_flags_t complain) TREE_TYPE (init) = type; if (TREE_CODE (type) == ARRAY_TYPE && TYPE_DOMAIN (type) == NULL_TREE) cp_complete_array_type (&TREE_TYPE (init), init, /*do_default=*/0); - if (flags & PICFLAG_NOT_ALL_CONSTANT) + if (flags & PICFLAG_SIDE_EFFECTS) + { + TREE_CONSTANT (init) = false; + TREE_SIDE_EFFECTS (init) = true; + } + else if (flags & PICFLAG_NOT_ALL_CONSTANT) /* Make sure TREE_CONSTANT isn't set from build_constructor. */ TREE_CONSTANT (init) = false; else diff --git a/gcc-4.8/gcc/cse.c b/gcc-4.8/gcc/cse.c index b200fef4d..eb17f6979 100644 --- a/gcc-4.8/gcc/cse.c +++ b/gcc-4.8/gcc/cse.c @@ -1824,7 +1824,7 @@ flush_hash_table (void) } } -/* Function called for each rtx to check whether true dependence exist. */ +/* Function called for each rtx to check whether an anti dependence exist. */ struct check_dependence_data { enum machine_mode mode; @@ -1837,7 +1837,7 @@ check_dependence (rtx *x, void *data) { struct check_dependence_data *d = (struct check_dependence_data *) data; if (*x && MEM_P (*x)) - return canon_true_dependence (d->exp, d->mode, d->addr, *x, NULL_RTX); + return canon_anti_dependence (*x, true, d->exp, d->mode, d->addr); else return 0; } @@ -5659,9 +5659,10 @@ cse_insn (rtx insn) invalidate (XEXP (dest, 0), GET_MODE (dest)); } - /* A volatile ASM or an UNSPEC_VOLATILE invalidates everything. */ + /* A volatile ASM invalidates everything. */ if (NONJUMP_INSN_P (insn) - && volatile_insn_p (PATTERN (insn))) + && GET_CODE (PATTERN (insn)) == ASM_OPERANDS + && MEM_VOLATILE_P (PATTERN (insn))) flush_hash_table (); /* Don't cse over a call to setjmp; on some machines (eg VAX) @@ -6082,6 +6083,18 @@ cse_process_notes_1 (rtx x, rtx object, bool *changed) return x; } + case UNSIGNED_FLOAT: + { + rtx new_rtx = cse_process_notes (XEXP (x, 0), object, changed); + /* We don't substitute negative VOIDmode constants into these rtx, + since they would impede folding. */ + if (GET_MODE (new_rtx) != VOIDmode + || (CONST_INT_P (new_rtx) && INTVAL (new_rtx) >= 0) + || (CONST_DOUBLE_P (new_rtx) && CONST_DOUBLE_HIGH (new_rtx) >= 0)) + validate_change (object, &XEXP (x, 0), new_rtx, 0); + return x; + } + case REG: i = REG_QTY (REGNO (x)); diff --git a/gcc-4.8/gcc/cselib.c b/gcc-4.8/gcc/cselib.c index f2021b985..1e59f3a1b 100644 --- a/gcc-4.8/gcc/cselib.c +++ b/gcc-4.8/gcc/cselib.c @@ -2260,8 +2260,8 @@ cselib_invalidate_mem (rtx mem_rtx) continue; } if (num_mems < PARAM_VALUE (PARAM_MAX_CSELIB_MEMORY_LOCATIONS) - && ! canon_true_dependence (mem_rtx, GET_MODE (mem_rtx), - mem_addr, x, NULL_RTX)) + && ! canon_anti_dependence (x, false, mem_rtx, + GET_MODE (mem_rtx), mem_addr)) { has_mem = true; num_mems++; @@ -2623,12 +2623,13 @@ cselib_process_insn (rtx insn) cselib_current_insn = insn; - /* Forget everything at a CODE_LABEL, a volatile insn, or a setjmp. */ + /* Forget everything at a CODE_LABEL, a volatile asm, or a setjmp. */ if ((LABEL_P (insn) || (CALL_P (insn) && find_reg_note (insn, REG_SETJMP, NULL)) || (NONJUMP_INSN_P (insn) - && volatile_insn_p (PATTERN (insn)))) + && GET_CODE (PATTERN (insn)) == ASM_OPERANDS + && MEM_VOLATILE_P (PATTERN (insn)))) && !cselib_preserve_constants) { cselib_reset_table (next_uid); diff --git a/gcc-4.8/gcc/doc/aot-compile.1 b/gcc-4.8/gcc/doc/aot-compile.1 index c5ee9a688..9c0f0fee9 100644 --- a/gcc-4.8/gcc/doc/aot-compile.1 +++ b/gcc-4.8/gcc/doc/aot-compile.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "AOT-COMPILE 1" -.TH AOT-COMPILE 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH AOT-COMPILE 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/cpp.1 b/gcc-4.8/gcc/doc/cpp.1 index c6e5d4f3a..8eb660f30 100644 --- a/gcc-4.8/gcc/doc/cpp.1 +++ b/gcc-4.8/gcc/doc/cpp.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "CPP 1" -.TH CPP 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH CPP 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/cpp.info b/gcc-4.8/gcc/doc/cpp.info index bcf62824b..36327d348 100644 --- a/gcc-4.8/gcc/doc/cpp.info +++ b/gcc-4.8/gcc/doc/cpp.info @@ -1,5 +1,5 @@ -This is doc/cpp.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/cpp.texi. +This is doc/cpp.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/cpp.texi. Copyright (C) 1987-2013 Free Software Foundation, Inc. @@ -1734,11 +1734,10 @@ with `__FILE__' and `__LINE__', though. This macro is defined when the C++ compiler is in use. You can use `__cplusplus' to test whether a header is compiled by a C compiler or a C++ compiler. This macro is similar to `__STDC_VERSION__', in - that it expands to a version number. A fully conforming - implementation of the 1998 C++ standard will define this macro to - `199711L'. The GNU C++ compiler is not yet fully conforming, so - it uses `1' instead. It is hoped to complete the implementation - of standard C++ in the near future. + that it expands to a version number. Depending on the language + standard selected, the value of the macro is `199711L', as + mandated by the 1998 C++ standard, or `201103L', per the 2011 C++ + standard. `__OBJC__' This macro is defined, with value 1, when the Objective-C compiler @@ -2112,7 +2111,7 @@ double underscores. `__GXX_EXPERIMENTAL_CXX0X__' This macro is defined when compiling a C++ source file with the option `-std=c++0x' or `-std=gnu++0x'. It indicates that some - features likely to be included in C++0x are available. Note that + features likely to be included in C++0x are available. Note that these features are experimental, and may change or be removed in future versions of GCC. @@ -4510,9 +4509,9 @@ single-letter options may _not_ be grouped: `-dM' is very different from When used without `-E', this option has no effect. `-ftrack-macro-expansion[=LEVEL]' - Track locations of tokens across macro expansions. This allows the + Track locations of tokens across macro expansions. This allows the compiler to emit diagnostic about the current macro expansion stack - when a compilation error occurs in a macro expansion. Using this + when a compilation error occurs in a macro expansion. Using this option makes the preprocessor and the compiler consume more memory. The LEVEL parameter can be used to choose the level of precision of token location tracking thus decreasing the memory @@ -5156,7 +5155,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -5177,7 +5176,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -5224,7 +5223,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -5519,79 +5518,79 @@ Concept Index  Tag Table: -Node: Top982 -Node: Overview3587 -Node: Character sets6420 -Ref: Character sets-Footnote-18603 -Node: Initial processing8784 -Ref: trigraphs10343 -Node: Tokenization14545 -Ref: Tokenization-Footnote-121681 -Node: The preprocessing language21792 -Node: Header Files24670 -Node: Include Syntax26586 -Node: Include Operation28223 -Node: Search Path30071 -Node: Once-Only Headers33272 -Node: Alternatives to Wrapper #ifndef34931 -Node: Computed Includes36674 -Node: Wrapper Headers39832 -Node: System Headers42258 -Node: Macros44308 -Node: Object-like Macros45449 -Node: Function-like Macros49039 -Node: Macro Arguments50655 -Node: Stringification54800 -Node: Concatenation58006 -Node: Variadic Macros61114 -Node: Predefined Macros65901 -Node: Standard Predefined Macros66489 -Node: Common Predefined Macros72426 -Node: System-specific Predefined Macros90049 -Node: C++ Named Operators92072 -Node: Undefining and Redefining Macros93036 -Node: Directives Within Macro Arguments95140 -Node: Macro Pitfalls96688 -Node: Misnesting97221 -Node: Operator Precedence Problems98333 -Node: Swallowing the Semicolon100199 -Node: Duplication of Side Effects102222 -Node: Self-Referential Macros104405 -Node: Argument Prescan106814 -Node: Newlines in Arguments110568 -Node: Conditionals111519 -Node: Conditional Uses113349 -Node: Conditional Syntax114707 -Node: Ifdef115027 -Node: If118188 -Node: Defined120492 -Node: Else121775 -Node: Elif122345 -Node: Deleted Code123634 -Node: Diagnostics124881 -Node: Line Control126428 -Node: Pragmas130232 -Node: Other Directives134988 -Node: Preprocessor Output136038 -Node: Traditional Mode139239 -Node: Traditional lexical analysis140297 -Node: Traditional macros142800 -Node: Traditional miscellany146602 -Node: Traditional warnings147599 -Node: Implementation Details149796 -Node: Implementation-defined behavior150417 -Ref: Identifier characters151169 -Node: Implementation limits154247 -Node: Obsolete Features156921 -Node: Differences from previous versions159809 -Node: Invocation164017 -Ref: Wtrigraphs168469 -Ref: dashMF173244 -Ref: fdollars-in-identifiers182975 -Node: Environment Variables192844 -Node: GNU Free Documentation License195810 -Node: Index of Directives220974 -Node: Option Index223054 -Node: Concept Index229457 +Node: Top996 +Node: Overview3601 +Node: Character sets6434 +Ref: Character sets-Footnote-18617 +Node: Initial processing8798 +Ref: trigraphs10357 +Node: Tokenization14559 +Ref: Tokenization-Footnote-121695 +Node: The preprocessing language21806 +Node: Header Files24684 +Node: Include Syntax26600 +Node: Include Operation28237 +Node: Search Path30085 +Node: Once-Only Headers33286 +Node: Alternatives to Wrapper #ifndef34945 +Node: Computed Includes36688 +Node: Wrapper Headers39846 +Node: System Headers42272 +Node: Macros44322 +Node: Object-like Macros45463 +Node: Function-like Macros49053 +Node: Macro Arguments50669 +Node: Stringification54814 +Node: Concatenation58020 +Node: Variadic Macros61128 +Node: Predefined Macros65915 +Node: Standard Predefined Macros66503 +Node: Common Predefined Macros72345 +Node: System-specific Predefined Macros89968 +Node: C++ Named Operators91991 +Node: Undefining and Redefining Macros92955 +Node: Directives Within Macro Arguments95059 +Node: Macro Pitfalls96607 +Node: Misnesting97140 +Node: Operator Precedence Problems98252 +Node: Swallowing the Semicolon100118 +Node: Duplication of Side Effects102141 +Node: Self-Referential Macros104324 +Node: Argument Prescan106733 +Node: Newlines in Arguments110487 +Node: Conditionals111438 +Node: Conditional Uses113268 +Node: Conditional Syntax114626 +Node: Ifdef114946 +Node: If118107 +Node: Defined120411 +Node: Else121694 +Node: Elif122264 +Node: Deleted Code123553 +Node: Diagnostics124800 +Node: Line Control126347 +Node: Pragmas130151 +Node: Other Directives134907 +Node: Preprocessor Output135957 +Node: Traditional Mode139158 +Node: Traditional lexical analysis140216 +Node: Traditional macros142719 +Node: Traditional miscellany146521 +Node: Traditional warnings147518 +Node: Implementation Details149715 +Node: Implementation-defined behavior150336 +Ref: Identifier characters151088 +Node: Implementation limits154166 +Node: Obsolete Features156840 +Node: Differences from previous versions159728 +Node: Invocation163936 +Ref: Wtrigraphs168388 +Ref: dashMF173163 +Ref: fdollars-in-identifiers182894 +Node: Environment Variables192763 +Node: GNU Free Documentation License195729 +Node: Index of Directives220893 +Node: Option Index222973 +Node: Concept Index229376  End Tag Table diff --git a/gcc-4.8/gcc/doc/cppinternals.info b/gcc-4.8/gcc/doc/cppinternals.info index 3336fb002..aed69bac7 100644 --- a/gcc-4.8/gcc/doc/cppinternals.info +++ b/gcc-4.8/gcc/doc/cppinternals.info @@ -1,5 +1,5 @@ -This is doc/cppinternals.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/cppinternals.texi. +This is doc/cppinternals.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/cppinternals.texi. INFO-DIR-SECTION Software development START-INFO-DIR-ENTRY @@ -1019,17 +1019,17 @@ Concept Index  Tag Table: -Node: Top944 -Node: Conventions2629 -Node: Lexer3571 -Ref: Invalid identifiers11484 -Ref: Lexing a line13433 -Node: Hash Nodes18206 -Node: Macro Expansion21085 -Node: Token Spacing30032 -Node: Line Numbering35892 -Node: Guard Macros39977 -Node: Files44768 -Node: Concept Index48234 +Node: Top958 +Node: Conventions2643 +Node: Lexer3585 +Ref: Invalid identifiers11498 +Ref: Lexing a line13447 +Node: Hash Nodes18220 +Node: Macro Expansion21099 +Node: Token Spacing30046 +Node: Line Numbering35906 +Node: Guard Macros39991 +Node: Files44782 +Node: Concept Index48248  End Tag Table diff --git a/gcc-4.8/gcc/doc/extend.texi b/gcc-4.8/gcc/doc/extend.texi index b6075b7cb..860f2e83f 100644 --- a/gcc-4.8/gcc/doc/extend.texi +++ b/gcc-4.8/gcc/doc/extend.texi @@ -3121,6 +3121,17 @@ this function attribute to make GCC generate the ``hot-patching'' function prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2 and newer. +@item hotpatch [(@var{prologue-halfwords})] +@cindex @code{hotpatch} attribute + +On S/390 System z targets, you can use this function attribute to +make GCC generate a ``hot-patching'' function prologue. The +@code{hotpatch} has no effect on funtions that are explicitly +inline. If the @option{-mhotpatch} or @option{-mno-hotpatch} +command-line option is used at the same time, the @code{hotpatch} +attribute takes precedence. If an argument is given, the maximum +allowed value is 1000000. + @item naked @cindex function without a prologue/epilogue code Use this attribute on the ARM, AVR, MCORE, RX and SPU ports to indicate that @@ -8793,6 +8804,7 @@ instructions, but allow the compiler to schedule those calls. * picoChip Built-in Functions:: * PowerPC Built-in Functions:: * PowerPC AltiVec/VSX Built-in Functions:: +* PowerPC Hardware Transactional Memory Built-in Functions:: * RX Built-in Functions:: * S/390 System z Built-in Functions:: * SH Built-in Functions:: @@ -11840,9 +11852,12 @@ float __builtin_recipdivf (float, float); float __builtin_rsqrtf (float); double __builtin_recipdiv (double, double); double __builtin_rsqrt (double); -long __builtin_bpermd (long, long); uint64_t __builtin_ppc_get_timebase (); unsigned long __builtin_ppc_mftb (); +double __builtin_unpack_longdouble (long double, int); +double __builtin_longdouble_dw0 (long double); +double __builtin_longdouble_dw1 (long double); +long double __builtin_pack_longdouble (double, double); @end smallexample The @code{vec_rsqrt}, @code{__builtin_rsqrt}, and @@ -11862,6 +11877,57 @@ The @code{__builtin_ppc_mftb} function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. +The following built-in functions are available for the PowerPC family +of processors, starting with ISA 2.06 or later (@option{-mcpu=power7} +or @option{-mpopcntd}): +@smallexample +long __builtin_bpermd (long, long); +int __builtin_divwe (int, int); +int __builtin_divweo (int, int); +unsigned int __builtin_divweu (unsigned int, unsigned int); +unsigned int __builtin_divweuo (unsigned int, unsigned int); +long __builtin_divde (long, long); +long __builtin_divdeo (long, long); +unsigned long __builtin_divdeu (unsigned long, unsigned long); +unsigned long __builtin_divdeuo (unsigned long, unsigned long); +unsigned int cdtbcd (unsigned int); +unsigned int cbcdtd (unsigned int); +unsigned int addg6s (unsigned int, unsigned int); +@end smallexample + +The @code{__builtin_divde}, @code{__builtin_divdeo}, +@code{__builitin_divdeu}, @code{__builtin_divdeou} functions require a +64-bit environment support ISA 2.06 or later. + +The following built-in functions are available for the PowerPC family +of processors when hardware decimal floating point +(@option{-mhard-dfp}) is available: +@smallexample +_Decimal64 __builtin_dxex (_Decimal64); +_Decimal128 __builtin_dxexq (_Decimal128); +_Decimal64 __builtin_ddedpd (int, _Decimal64); +_Decimal128 __builtin_ddedpdq (int, _Decimal128); +_Decimal64 __builtin_denbcd (int, _Decimal64); +_Decimal128 __builtin_denbcdq (int, _Decimal128); +_Decimal64 __builtin_diex (_Decimal64, _Decimal64); +_Decimal128 _builtin_diexq (_Decimal128, _Decimal128); +_Decimal64 __builtin_dscli (_Decimal64, int); +_Decimal128 __builitn_dscliq (_Decimal128, int); +_Decimal64 __builtin_dscri (_Decimal64, int); +_Decimal128 __builitn_dscriq (_Decimal128, int); +unsigned long long __builtin_unpack_dec128 (_Decimal128, int); +_Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long); +@end smallexample + +The following built-in functions are available for the PowerPC family +of processors when the Vector Scalar (vsx) instruction set is +available: +@smallexample +unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int); +vector __int128_t __builtin_pack_vector_int128 (unsigned long long, + unsigned long long); +@end smallexample + @node PowerPC AltiVec/VSX Built-in Functions @subsection PowerPC AltiVec Built-in Functions @@ -13912,6 +13978,35 @@ void vec_vsx_st (vector unsigned char, int, unsigned char *); void vec_vsx_st (vector bool char, int, vector bool char *); void vec_vsx_st (vector bool char, int, unsigned char *); void vec_vsx_st (vector bool char, int, signed char *); + +vector double vec_xxpermdi (vector double, vector double, int); +vector float vec_xxpermdi (vector float, vector float, int); +vector long long vec_xxpermdi (vector long long, vector long long, int); +vector unsigned long long vec_xxpermdi (vector unsigned long long, + vector unsigned long long, int); +vector int vec_xxpermdi (vector int, vector int, int); +vector unsigned int vec_xxpermdi (vector unsigned int, + vector unsigned int, int); +vector short vec_xxpermdi (vector short, vector short, int); +vector unsigned short vec_xxpermdi (vector unsigned short, + vector unsigned short, int); +vector signed char vec_xxpermdi (vector signed char, vector signed char, int); +vector unsigned char vec_xxpermdi (vector unsigned char, + vector unsigned char, int); + +vector double vec_xxsldi (vector double, vector double, int); +vector float vec_xxsldi (vector float, vector float, int); +vector long long vec_xxsldi (vector long long, vector long long, int); +vector unsigned long long vec_xxsldi (vector unsigned long long, + vector unsigned long long, int); +vector int vec_xxsldi (vector int, vector int, int); +vector unsigned int vec_xxsldi (vector unsigned int, vector unsigned int, int); +vector short vec_xxsldi (vector short, vector short, int); +vector unsigned short vec_xxsldi (vector unsigned short, + vector unsigned short, int); +vector signed char vec_xxsldi (vector signed char, vector signed char, int); +vector unsigned char vec_xxsldi (vector unsigned char, + vector unsigned char, int); @end smallexample Note that the @samp{vec_ld} and @samp{vec_st} built-in functions always @@ -13920,6 +14015,593 @@ if the VSX instruction set is available. The @samp{vec_vsx_ld} and @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X}, @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions. +If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for both 32-bit and 64-bit targets. For 64-bit targets, you +can use @var{vector long} instead of @var{vector long long}, +@var{vector bool long} instead of @var{vector bool long long}, and +@var{vector unsigned long} instead of @var{vector unsigned long long}. + +@smallexample +vector long long vec_abs (vector long long); + +vector long long vec_add (vector long long, vector long long); +vector unsigned long long vec_add (vector unsigned long long, + vector unsigned long long); + +int vec_all_eq (vector long long, vector long long); +int vec_all_ge (vector long long, vector long long); +int vec_all_gt (vector long long, vector long long); +int vec_all_le (vector long long, vector long long); +int vec_all_lt (vector long long, vector long long); +int vec_all_ne (vector long long, vector long long); +int vec_any_eq (vector long long, vector long long); +int vec_any_ge (vector long long, vector long long); +int vec_any_gt (vector long long, vector long long); +int vec_any_le (vector long long, vector long long); +int vec_any_lt (vector long long, vector long long); +int vec_any_ne (vector long long, vector long long); + +vector long long vec_eqv (vector long long, vector long long); +vector long long vec_eqv (vector bool long long, vector long long); +vector long long vec_eqv (vector long long, vector bool long long); +vector unsigned long long vec_eqv (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_eqv (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_eqv (vector unsigned long long, + vector bool long long); +vector int vec_eqv (vector int, vector int); +vector int vec_eqv (vector bool int, vector int); +vector int vec_eqv (vector int, vector bool int); +vector unsigned int vec_eqv (vector unsigned int, vector unsigned int); +vector unsigned int vec_eqv (vector bool unsigned int, + vector unsigned int); +vector unsigned int vec_eqv (vector unsigned int, + vector bool unsigned int); +vector short vec_eqv (vector short, vector short); +vector short vec_eqv (vector bool short, vector short); +vector short vec_eqv (vector short, vector bool short); +vector unsigned short vec_eqv (vector unsigned short, vector unsigned short); +vector unsigned short vec_eqv (vector bool unsigned short, + vector unsigned short); +vector unsigned short vec_eqv (vector unsigned short, + vector bool unsigned short); +vector signed char vec_eqv (vector signed char, vector signed char); +vector signed char vec_eqv (vector bool signed char, vector signed char); +vector signed char vec_eqv (vector signed char, vector bool signed char); +vector unsigned char vec_eqv (vector unsigned char, vector unsigned char); +vector unsigned char vec_eqv (vector bool unsigned char, vector unsigned char); +vector unsigned char vec_eqv (vector unsigned char, vector bool unsigned char); + +vector long long vec_max (vector long long, vector long long); +vector unsigned long long vec_max (vector unsigned long long, + vector unsigned long long); + +vector long long vec_min (vector long long, vector long long); +vector unsigned long long vec_min (vector unsigned long long, + vector unsigned long long); + +vector long long vec_nand (vector long long, vector long long); +vector long long vec_nand (vector bool long long, vector long long); +vector long long vec_nand (vector long long, vector bool long long); +vector unsigned long long vec_nand (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_nand (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_nand (vector unsigned long long, + vector bool long long); +vector int vec_nand (vector int, vector int); +vector int vec_nand (vector bool int, vector int); +vector int vec_nand (vector int, vector bool int); +vector unsigned int vec_nand (vector unsigned int, vector unsigned int); +vector unsigned int vec_nand (vector bool unsigned int, + vector unsigned int); +vector unsigned int vec_nand (vector unsigned int, + vector bool unsigned int); +vector short vec_nand (vector short, vector short); +vector short vec_nand (vector bool short, vector short); +vector short vec_nand (vector short, vector bool short); +vector unsigned short vec_nand (vector unsigned short, vector unsigned short); +vector unsigned short vec_nand (vector bool unsigned short, + vector unsigned short); +vector unsigned short vec_nand (vector unsigned short, + vector bool unsigned short); +vector signed char vec_nand (vector signed char, vector signed char); +vector signed char vec_nand (vector bool signed char, vector signed char); +vector signed char vec_nand (vector signed char, vector bool signed char); +vector unsigned char vec_nand (vector unsigned char, vector unsigned char); +vector unsigned char vec_nand (vector bool unsigned char, vector unsigned char); +vector unsigned char vec_nand (vector unsigned char, vector bool unsigned char); + +vector long long vec_orc (vector long long, vector long long); +vector long long vec_orc (vector bool long long, vector long long); +vector long long vec_orc (vector long long, vector bool long long); +vector unsigned long long vec_orc (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_orc (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_orc (vector unsigned long long, + vector bool long long); +vector int vec_orc (vector int, vector int); +vector int vec_orc (vector bool int, vector int); +vector int vec_orc (vector int, vector bool int); +vector unsigned int vec_orc (vector unsigned int, vector unsigned int); +vector unsigned int vec_orc (vector bool unsigned int, + vector unsigned int); +vector unsigned int vec_orc (vector unsigned int, + vector bool unsigned int); +vector short vec_orc (vector short, vector short); +vector short vec_orc (vector bool short, vector short); +vector short vec_orc (vector short, vector bool short); +vector unsigned short vec_orc (vector unsigned short, vector unsigned short); +vector unsigned short vec_orc (vector bool unsigned short, + vector unsigned short); +vector unsigned short vec_orc (vector unsigned short, + vector bool unsigned short); +vector signed char vec_orc (vector signed char, vector signed char); +vector signed char vec_orc (vector bool signed char, vector signed char); +vector signed char vec_orc (vector signed char, vector bool signed char); +vector unsigned char vec_orc (vector unsigned char, vector unsigned char); +vector unsigned char vec_orc (vector bool unsigned char, vector unsigned char); +vector unsigned char vec_orc (vector unsigned char, vector bool unsigned char); + +vector int vec_pack (vector long long, vector long long); +vector unsigned int vec_pack (vector unsigned long long, + vector unsigned long long); +vector bool int vec_pack (vector bool long long, vector bool long long); + +vector int vec_packs (vector long long, vector long long); +vector unsigned int vec_packs (vector unsigned long long, + vector unsigned long long); + +vector unsigned int vec_packsu (vector long long, vector long long); + +vector long long vec_rl (vector long long, + vector unsigned long long); +vector long long vec_rl (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sl (vector long long, vector unsigned long long); +vector long long vec_sl (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sr (vector long long, vector unsigned long long); +vector unsigned long long char vec_sr (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sra (vector long long, vector unsigned long long); +vector unsigned long long vec_sra (vector unsigned long long, + vector unsigned long long); + +vector long long vec_sub (vector long long, vector long long); +vector unsigned long long vec_sub (vector unsigned long long, + vector unsigned long long); + +vector long long vec_unpackh (vector int); +vector unsigned long long vec_unpackh (vector unsigned int); + +vector long long vec_unpackl (vector int); +vector unsigned long long vec_unpackl (vector unsigned int); + +vector long long vec_vaddudm (vector long long, vector long long); +vector long long vec_vaddudm (vector bool long long, vector long long); +vector long long vec_vaddudm (vector long long, vector bool long long); +vector unsigned long long vec_vaddudm (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vaddudm (vector bool unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vaddudm (vector unsigned long long, + vector bool unsigned long long); + +vector long long vec_vbpermq (vector signed char, vector signed char); +vector long long vec_vbpermq (vector unsigned char, vector unsigned char); + +vector long long vec_vclz (vector long long); +vector unsigned long long vec_vclz (vector unsigned long long); +vector int vec_vclz (vector int); +vector unsigned int vec_vclz (vector int); +vector short vec_vclz (vector short); +vector unsigned short vec_vclz (vector unsigned short); +vector signed char vec_vclz (vector signed char); +vector unsigned char vec_vclz (vector unsigned char); + +vector signed char vec_vclzb (vector signed char); +vector unsigned char vec_vclzb (vector unsigned char); + +vector long long vec_vclzd (vector long long); +vector unsigned long long vec_vclzd (vector unsigned long long); + +vector short vec_vclzh (vector short); +vector unsigned short vec_vclzh (vector unsigned short); + +vector int vec_vclzw (vector int); +vector unsigned int vec_vclzw (vector int); + +vector signed char vec_vgbbd (vector signed char); +vector unsigned char vec_vgbbd (vector unsigned char); + +vector long long vec_vmaxsd (vector long long, vector long long); + +vector unsigned long long vec_vmaxud (vector unsigned long long, + unsigned vector long long); + +vector long long vec_vminsd (vector long long, vector long long); + +vector unsigned long long vec_vminud (vector long long, + vector long long); + +vector int vec_vpksdss (vector long long, vector long long); +vector unsigned int vec_vpksdss (vector long long, vector long long); + +vector unsigned int vec_vpkudus (vector unsigned long long, + vector unsigned long long); + +vector int vec_vpkudum (vector long long, vector long long); +vector unsigned int vec_vpkudum (vector unsigned long long, + vector unsigned long long); +vector bool int vec_vpkudum (vector bool long long, vector bool long long); + +vector long long vec_vpopcnt (vector long long); +vector unsigned long long vec_vpopcnt (vector unsigned long long); +vector int vec_vpopcnt (vector int); +vector unsigned int vec_vpopcnt (vector int); +vector short vec_vpopcnt (vector short); +vector unsigned short vec_vpopcnt (vector unsigned short); +vector signed char vec_vpopcnt (vector signed char); +vector unsigned char vec_vpopcnt (vector unsigned char); + +vector signed char vec_vpopcntb (vector signed char); +vector unsigned char vec_vpopcntb (vector unsigned char); + +vector long long vec_vpopcntd (vector long long); +vector unsigned long long vec_vpopcntd (vector unsigned long long); + +vector short vec_vpopcnth (vector short); +vector unsigned short vec_vpopcnth (vector unsigned short); + +vector int vec_vpopcntw (vector int); +vector unsigned int vec_vpopcntw (vector int); + +vector long long vec_vrld (vector long long, vector unsigned long long); +vector unsigned long long vec_vrld (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsld (vector long long, vector unsigned long long); +vector long long vec_vsld (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsrad (vector long long, vector unsigned long long); +vector unsigned long long vec_vsrad (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsrd (vector long long, vector unsigned long long); +vector unsigned long long char vec_vsrd (vector unsigned long long, + vector unsigned long long); + +vector long long vec_vsubudm (vector long long, vector long long); +vector long long vec_vsubudm (vector bool long long, vector long long); +vector long long vec_vsubudm (vector long long, vector bool long long); +vector unsigned long long vec_vsubudm (vector unsigned long long, + vector unsigned long long); +vector unsigned long long vec_vsubudm (vector bool long long, + vector unsigned long long); +vector unsigned long long vec_vsubudm (vector unsigned long long, + vector bool long long); + +vector long long vec_vupkhsw (vector int); +vector unsigned long long vec_vupkhsw (vector unsigned int); + +vector long long vec_vupklsw (vector int); +vector unsigned long long vec_vupklsw (vector int); +@end smallexample + +If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for 64-bit targets. New vector types +(@var{vector __int128_t} and @var{vector __uint128_t}) are available +to hold the @var{__int128_t} and @var{__uint128_t} types to use these +builtins. + +The normal vector extract, and set operations work on +@var{vector __int128_t} and @var{vector __uint128_t} types, +but the index value must be 0. + +@smallexample +vector __int128_t vec_vaddcuq (vector __int128_t, vector __int128_t); +vector __uint128_t vec_vaddcuq (vector __uint128_t, vector __uint128_t); + +vector __int128_t vec_vadduqm (vector __int128_t, vector __int128_t); +vector __uint128_t vec_vadduqm (vector __uint128_t, vector __uint128_t); + +vector __int128_t vec_vaddecuq (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vaddecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vaddeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vaddeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vsubecuq (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vsubecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vsubeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); +vector __uint128_t vec_vsubeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + +vector __int128_t vec_vsubcuq (vector __int128_t, vector __int128_t); +vector __uint128_t vec_vsubcuq (vector __uint128_t, vector __uint128_t); + +__int128_t vec_vsubuqm (__int128_t, __int128_t); +__uint128_t vec_vsubuqm (__uint128_t, __uint128_t); + +vector __int128_t __builtin_bcdadd (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_lt (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_eq (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_gt (vector __int128_t, vector__int128_t); +int __builtin_bcdadd_ov (vector __int128_t, vector__int128_t); +vector __int128_t bcdsub (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_lt (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_eq (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t); +int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t); +@end smallexample + +If the cryptographic instructions are enabled (@option{-mcrypto} or +@option{-mcpu=power8}), the following builtins are enabled. + +@smallexample +vector unsigned long long __builtin_crypto_vsbox (vector unsigned long long); + +vector unsigned long long __builtin_crypto_vcipher (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vcipherlast + (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vncipher (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vncipherlast + (vector unsigned long long, + vector unsigned long long); + +vector unsigned char __builtin_crypto_vpermxor (vector unsigned char, + vector unsigned char, + vector unsigned char); + +vector unsigned short __builtin_crypto_vpermxor (vector unsigned short, + vector unsigned short, + vector unsigned short); + +vector unsigned int __builtin_crypto_vpermxor (vector unsigned int, + vector unsigned int, + vector unsigned int); + +vector unsigned long long __builtin_crypto_vpermxor (vector unsigned long long, + vector unsigned long long, + vector unsigned long long); + +vector unsigned char __builtin_crypto_vpmsumb (vector unsigned char, + vector unsigned char); + +vector unsigned short __builtin_crypto_vpmsumb (vector unsigned short, + vector unsigned short); + +vector unsigned int __builtin_crypto_vpmsumb (vector unsigned int, + vector unsigned int); + +vector unsigned long long __builtin_crypto_vpmsumb (vector unsigned long long, + vector unsigned long long); + +vector unsigned long long __builtin_crypto_vshasigmad + (vector unsigned long long, int, int); + +vector unsigned int __builtin_crypto_vshasigmaw (vector unsigned int, + int, int); +@end smallexample + +The second argument to the @var{__builtin_crypto_vshasigmad} and +@var{__builtin_crypto_vshasigmaw} builtin functions must be a constant +integer that is 0 or 1. The third argument to these builtin functions +must be a constant integer in the range of 0 to 15. + +@node PowerPC Hardware Transactional Memory Built-in Functions +@subsection PowerPC Hardware Transactional Memory Built-in Functions +GCC provides two interfaces for accessing the Hardware Transactional +Memory (HTM) instructions available on some of the PowerPC family +of prcoessors (eg, POWER8). The two interfaces come in a low level +interface, consisting of built-in functions specific to PowerPC and a +higher level interface consisting of inline functions that are common +between PowerPC and S/390. + +@subsubsection PowerPC HTM Low Level Built-in Functions + +The following low level built-in functions are available with +@option{-mhtm} or @option{-mcpu=CPU} where CPU is `power8' or later. +They all generate the machine instruction that is part of the name. + +The HTM built-ins return true or false depending on their success and +their arguments match exactly the type and order of the associated +hardware instruction's operands. Refer to the ISA manual for a +description of each instruction's operands. + +@smallexample +unsigned int __builtin_tbegin (unsigned int) +unsigned int __builtin_tend (unsigned int) + +unsigned int __builtin_tabort (unsigned int) +unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int) +unsigned int __builtin_tabortdci (unsigned int, unsigned int, int) +unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int) +unsigned int __builtin_tabortwci (unsigned int, unsigned int, int) + +unsigned int __builtin_tcheck (unsigned int) +unsigned int __builtin_treclaim (unsigned int) +unsigned int __builtin_trechkpt (void) +unsigned int __builtin_tsr (unsigned int) +@end smallexample + +In addition to the above HTM built-ins, we have added built-ins for +some common extended mnemonics of the HTM instructions: + +@smallexample +unsigned int __builtin_tendall (void) +unsigned int __builtin_tresume (void) +unsigned int __builtin_tsuspend (void) +@end smallexample + +The following set of built-in functions are available to gain access +to the HTM specific special purpose registers. + +@smallexample +unsigned long __builtin_get_texasr (void) +unsigned long __builtin_get_texasru (void) +unsigned long __builtin_get_tfhar (void) +unsigned long __builtin_get_tfiar (void) + +void __builtin_set_texasr (unsigned long); +void __builtin_set_texasru (unsigned long); +void __builtin_set_tfhar (unsigned long); +void __builtin_set_tfiar (unsigned long); +@end smallexample + +Example usage of these low level built-in functions may look like: + +@smallexample +#include + +int num_retries = 10; + +while (1) + @{ + if (__builtin_tbegin (0)) + @{ + /* Transaction State Initiated. */ + if (is_locked (lock)) + __builtin_tabort (0); + ... transaction code... + __builtin_tend (0); + break; + @} + else + @{ + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ())) + @{ + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + @} + @} + @} +@end smallexample + +One final built-in function has been added that returns the value of +the 2-bit Transaction State field of the Machine Status Register (MSR) +as stored in @code{CR0}. + +@smallexample +unsigned long __builtin_ttest (void) +@end smallexample + +This built-in can be used to determine the current transaction state +using the following code example: + +@smallexample +#include + +unsigned char tx_state = _HTM_STATE (__builtin_ttest ()); + +if (tx_state == _HTM_TRANSACTIONAL) + @{ + /* Code to use in transactional state. */ + @} +else if (tx_state == _HTM_NONTRANSACTIONAL) + @{ + /* Code to use in non-transactional state. */ + @} +else if (tx_state == _HTM_SUSPENDED) + @{ + /* Code to use in transaction suspended state. */ + @} +@end smallexample + +@subsubsection PowerPC HTM High Level Inline Functions + +The following high level HTM interface is made available by including +@code{} and using @option{-mhtm} or @option{-mcpu=CPU} +where CPU is `power8' or later. This interface is common between PowerPC +and S/390, allowing users to write one HTM source implementation that +can be compiled and executed on either system. + +@smallexample +long __TM_simple_begin (void) +long __TM_begin (void* const TM_buff) +long __TM_end (void) +void __TM_abort (void) +void __TM_named_abort (unsigned char const code) +void __TM_resume (void) +void __TM_suspend (void) + +long __TM_is_user_abort (void* const TM_buff) +long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code) +long __TM_is_illegal (void* const TM_buff) +long __TM_is_footprint_exceeded (void* const TM_buff) +long __TM_nesting_depth (void* const TM_buff) +long __TM_is_nested_too_deep(void* const TM_buff) +long __TM_is_conflict(void* const TM_buff) +long __TM_is_failure_persistent(void* const TM_buff) +long __TM_failure_address(void* const TM_buff) +long long __TM_failure_code(void* const TM_buff) +@end smallexample + +Using these common set of HTM inline functions, we can create +a more portable version of the HTM example in the previous +section that will work on either PowerPC or S/390: + +@smallexample +#include + +int num_retries = 10; +TM_buff_type TM_buff; + +while (1) + @{ + if (__TM_begin (TM_buff)) + @{ + /* Transaction State Initiated. */ + if (is_locked (lock)) + __TM_abort (); + ... transaction code... + __TM_end (); + break; + @} + else + @{ + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || __TM_is_failure_persistent (TM_buff)) + @{ + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + @} + @} + @} +@end smallexample + @node RX Built-in Functions @subsection RX Built-in Functions GCC supports some of the RX instructions which cannot be expressed in diff --git a/gcc-4.8/gcc/doc/fsf-funding.7 b/gcc-4.8/gcc/doc/fsf-funding.7 index 5cf80b133..bc192f1ad 100644 --- a/gcc-4.8/gcc/doc/fsf-funding.7 +++ b/gcc-4.8/gcc/doc/fsf-funding.7 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "FSF-FUNDING 7" -.TH FSF-FUNDING 7 "2013-05-31" "gcc-4.8.1" "GNU" +.TH FSF-FUNDING 7 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -133,7 +141,7 @@ fsf\-funding \- Funding Free Software .SH "DESCRIPTION" .IX Header "DESCRIPTION" -.SS "Funding Free Software" +.Sh "Funding Free Software" .IX Subsection "Funding Free Software" If you want to have more free software a few years from now, it makes sense for you to help encourage people to contribute funds for its diff --git a/gcc-4.8/gcc/doc/g++.1 b/gcc-4.8/gcc/doc/g++.1 index 88e400d95..24005b6cc 100644 --- a/gcc-4.8/gcc/doc/g++.1 +++ b/gcc-4.8/gcc/doc/g++.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -180,7 +188,7 @@ these have both positive and negative forms; the negative form of only one of these two forms, whichever one is not the default. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Option Summary" +.Sh "Option Summary" .IX Subsection "Option Summary" Here is a summary of all the options, grouped by type. Explanations are in the following sections. @@ -190,7 +198,7 @@ in the following sections. \&\-pipe \-pass\-exit\-codes \&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR -\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIarg\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR .IP "\fIC Language Options\fR" 4 .IX Item "C Language Options" \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline @@ -867,7 +875,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mno\-recip\-precision \&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions -\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect\fR +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mdirect\-move \-mno\-direct\-move +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm\fR .Sp \&\fI\s-1RX\s0 Options\fR \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu @@ -891,7 +904,8 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd -\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch[=\fR\fIhalfwords\fR\fB] \-mno\-hotpatch\fR .Sp \&\fIScore Options\fR \&\fB\-meb \-mel @@ -936,11 +950,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mhard\-quad\-float \-msoft\-quad\-float \&\-mstack\-bias \-mno\-stack\-bias \&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode \&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis \&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 \&\-mcbcond \-mno\-cbcond \&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc -\&\-mfix\-at697f\fR +\&\-mfix\-at697f \-mfix\-ut699\fR .Sp \&\fI\s-1SPU\s0 Options\fR \&\fB\-mwarn\-reloc \-merror\-reloc @@ -1029,7 +1044,7 @@ See S/390 and zSeries Options. \&\fB\-fstack\-reuse=\fR\fIreuse_level\fR \&\fB\-ftrapv \-fwrapv \-fbounds\-check \&\-fvisibility \-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR -.SS "Options Controlling the Kind of Output" +.Sh "Options Controlling the Kind of Output" .IX Subsection "Options Controlling the Kind of Output" Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of @@ -1459,8 +1474,11 @@ Define an argument called \fIkey\fR with a value of \fIvalue\fR for the plugin called \fIname\fR. .IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 .IX Item "-fdump-ada-spec[-slim]" -For C and \*(C+ source and include files, generate corresponding Ada -specs. +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. .IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 .IX Item "-fdump-go-spec=file" For input files in any language, generate corresponding Go @@ -1481,8 +1499,8 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.Sh "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1505,7 +1523,7 @@ When you compile \*(C+ programs, you may specify many of the same command-line options that you use for compiling programs in any language; or command-line options meaningful for C and related languages; or options that are meaningful only for \*(C+ programs. -.SS "Options Controlling C Dialect" +.Sh "Options Controlling C Dialect" .IX Subsection "Options Controlling C Dialect" The following options control the dialect of C (or languages derived from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler @@ -1892,8 +1910,8 @@ These options control whether a bit-field is signed or unsigned, when the declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By default, such a bit-field is signed, because this is consistent: the basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. -.SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.Sh "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2250,7 +2268,7 @@ Do not assume \fBinline\fR for functions defined inside a class scope. functions have linkage like inline functions; they just aren't inlined by default. .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ generates code that is probably not compatible with the vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about all such cases, there are probably some cases that are not warned about, @@ -2562,7 +2580,7 @@ Warn when overload resolution chooses a promotion from unsigned or enumerated type to a signed type, over a conversion to an unsigned type of the same size. Previous versions of G++ tried to preserve unsignedness, but the standard mandates the current behavior. -.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" .IX Subsection "Options Controlling Objective-C and Objective- Dialects" (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ languages themselves. @@ -2759,7 +2777,7 @@ that methods and selectors must be declared before being used. .IX Item "-print-objc-runtime-info" Generate C header describing the largest structure that is passed by value, if any. -.SS "Options to Control Diagnostic Messages Formatting" +.Sh "Options to Control Diagnostic Messages Formatting" .IX Subsection "Options to Control Diagnostic Messages Formatting" Traditionally, diagnostic messages have been formatted irrespective of the output device's aspect (e.g. its width, ...). You can use the @@ -2800,7 +2818,7 @@ option is known to the diagnostic machinery). Specifying the By default, each diagnostic emitted includes the original source line and a caret '^' indicating the column. This option suppresses this information. -.SS "Options to Request or Suppress Warnings" +.Sh "Options to Request or Suppress Warnings" .IX Subsection "Options to Request or Suppress Warnings" Warnings are diagnostic messages that report constructions that are not inherently erroneous but that are risky or suggest there @@ -3186,7 +3204,7 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, since the value returned by a function is not an lvalue. @@ -3358,7 +3376,7 @@ between \fB\-Wswitch\fR and this option is that this option gives a warning about an omitted enumeration code even if there is a \&\f(CW\*(C`default\*(C'\fR label. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. .IP "\fB\-Wtrigraphs\fR" 4 @@ -3397,7 +3415,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \fBunused\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -4355,7 +4373,7 @@ a suffix. When used together with \fB\-Wsystem\-headers\fR it warns about such constants in system header files. This can be useful when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma from the decimal floating-point extension to C99. -.SS "Options for Debugging Your Program or \s-1GCC\s0" +.Sh "Options for Debugging Your Program or \s-1GCC\s0" .IX Subsection "Options for Debugging Your Program or GCC" \&\s-1GCC\s0 has various special options that are used for debugging either your program or \s-1GCC:\s0 @@ -5859,7 +5877,7 @@ in that compilation unit, for example if, in the debugger, you want to cast a value to a type that is not actually used in your program (but is declared). More often, however, this results in a significant amount of wasted space. -.SS "Options That Control Optimization" +.Sh "Options That Control Optimization" .IX Subsection "Options That Control Optimization" These options control various sorts of optimizations. .PP @@ -8968,7 +8986,7 @@ seeking a basis for a new straight-line strength reduction candidate. .RE .RS 4 .RE -.SS "Options Controlling the Preprocessor" +.Sh "Options Controlling the Preprocessor" .IX Subsection "Options Controlling the Preprocessor" These options control the C preprocessor, which is run on each C source file before actual compilation. @@ -9770,7 +9788,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .PD Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. -.SS "Passing Options to the Assembler" +.Sh "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" You can pass options to the assembler. .IP "\fB\-Wa,\fR\fIoption\fR" 4 @@ -9785,7 +9803,7 @@ recognize. .Sp If you want to pass an option that takes an argument, you must use \&\fB\-Xassembler\fR twice, once for the option and once for the argument. -.SS "Options for Linking" +.Sh "Options for Linking" .IX Subsection "Options for Linking" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is @@ -10024,7 +10042,7 @@ linker. When using the \s-1GNU\s0 linker, you can also get the same effect with Pretend the symbol \fIsymbol\fR is undefined, to force linking of library modules to define it. You can use \fB\-u\fR multiple times with different symbols to force loading of additional library modules. -.SS "Options for Directory Search" +.Sh "Options for Directory Search" .IX Subsection "Options for Directory Search" These options specify directories to search for header files, for libraries and for parts of the compiler: @@ -10159,13 +10177,13 @@ by default, but it is often satisfactory. \&\fB\-I\-\fR does not inhibit the use of the standard system directories for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are independent. -.SS "Specifying Target Machine and Compiler Version" +.Sh "Specifying Target Machine and Compiler Version" .IX Subsection "Specifying Target Machine and Compiler Version" The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or \&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the one that was installed last. -.SS "Hardware Models and Configurations" +.Sh "Hardware Models and Configurations" .IX Subsection "Hardware Models and Configurations" Each target machine types can have its own special options, starting with \fB\-m\fR, to choose among various @@ -10489,11 +10507,31 @@ order. That is, a byte order of the form \fB32107654\fR. Note: this option should only be used if you require compatibility with code for big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBarmv7e\-m\fR +\&\fBarmv8\-a\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, \&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, \&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, @@ -10521,25 +10559,6 @@ assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBfa526\fR, \fBfa626\fR, \&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. .Sp -\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is -equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. -See \fB\-mtune\fR for more information. -.Sp -\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. -.IP "\fB\-mtune=\fR\fIname\fR" 4 -.IX Item "-mtune=name" -This option is very similar to the \fB\-mcpu=\fR option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that \s-1GCC\s0 should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. -For some \s-1ARM\s0 implementations better performance can be obtained by using -this option. -.Sp \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the performance for a blend of processors within architecture \fIarch\fR. The aim is to generate code that run well on the current most popular @@ -10551,21 +10570,23 @@ this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come a of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -.IP "\fB\-march=\fR\fIname\fR" 4 -.IX Item "-march=name" -This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, -\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, -\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, -\&\fBarmv6\fR, \fBarmv6j\fR, -\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, -\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, -\&\fBarmv8\-a\fR, -\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. .Sp -\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -10649,8 +10670,11 @@ responsible for initializing this register with an appropriate value before execution begins. .IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 .IX Item "-mpic-register=reg" -Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default will be any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -10805,7 +10829,7 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .el .IP "\f(CWavr5\fR" 4 .IX Item "avr5" \&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. .ie n .IP """avr51""" 4 .el .IP "\f(CWavr51\fR" 4 .IX Item "avr51" @@ -11043,7 +11067,7 @@ command-line option. .IX Item "-" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-" 4 -.IX Item "-" +.IX Item "-" .PD 0 .ie n .IP "\-" 4 .el .IP "\-" 4 @@ -11790,7 +11814,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -12865,9 +12889,14 @@ Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SS Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction set support. +.IP "\fBcore\-avx2\fR" 4 +.IX Item "core-avx2" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, \s-1BMI\s0, \s-1BMI2\s0 +and F16C instruction set support. .IP "\fBatom\fR" 4 .IX Item "atom" -Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBk6\fR" 4 .IX Item "k6" @@ -16284,7 +16313,9 @@ following options: \&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple \&\-mpopcntb \-mpopcntd \-mpowerpc64 \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float -\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mdirect\-move \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic\fR .Sp The particular options set for any particular \s-1CPU\s0 varies between compiler versions, depending on what setting seems to produce optimal @@ -16331,6 +16362,36 @@ enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set \&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 enhancements. +.Sp +When \fB\-maltivec\fR is used, rather than \fB\-maltivec=le\fR or +\&\fB\-maltivec=be\fR, the element order for Altivec intrinsics such +as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-maltivec=be\fR" 4 +.IX Item "-maltivec=be" +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. +.IP "\fB\-maltivec=le\fR" 4 +.IX Item "-maltivec=le" +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. .IP "\fB\-mvrsave\fR" 4 .IX Item "-mvrsave" .PD 0 @@ -16399,6 +16460,61 @@ This option has been deprecated. Use \fB\-mspe\fR and Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) instructions, and also enable the use of built-in functions that allow more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mdirect\-move\fR" 4 +.IX Item "-mdirect-move" +.PD 0 +.IP "\fB\-mno\-direct\-move\fR" 4 +.IX Item "-mno-direct-move" +.PD +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (\s-1VSX\s0) +registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 .IX Item "-mfloat-gprs=yes/single/double/no" .PD 0 @@ -16828,7 +16944,8 @@ Return structures smaller than 8 bytes in registers (as specified by the .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, -\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR, +\&\fIelfv1\fR, \fIelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change @@ -16845,6 +16962,18 @@ This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. .IP "\fB\-mprototype\fR" 4 .IX Item "-mprototype" .PD 0 @@ -17132,6 +17261,25 @@ stack location in the function prologue if the function calls through a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not saved in the prologue, it is saved just before the call through the pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC\s0. +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC\s0. This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC\s0. +.Sp +In this version of the compiler, the \fB\-mcompat\-align\-parm\fR +is the default, except when using the Linux ELFv2 \s-1ABI\s0. .PP \fI\s-1RX\s0 Options\fR .IX Subsection "RX Options" @@ -17514,6 +17662,23 @@ values have to be exact powers of 2 and \fIstack-size\fR has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by \fIstack-size\fR. The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch[=\fR\fIhalfwords\fR\fB]\fR" 4 +.IX Item "-mhotpatch[=halfwords]" +.PD 0 +.IP "\fB\-mno\-hotpatch\fR" 4 +.IX Item "-mno-hotpatch" +.PD +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (\fIhalfwords\fR, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. .PP \fIScore Options\fR .IX Subsection "Score Options" @@ -18039,8 +18204,9 @@ These \fB\-m\fR options are supported on the \s-1SPARC:\s0 .IX Item "-mapp-regs" .PD Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This -is the default. +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. .Sp To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, specify \fB\-mno\-app\-regs\fR. You should compile libraries and system @@ -18116,6 +18282,15 @@ absolute address. Otherwise, it assumes they have 4\-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The +default is \fB\-mno\-user\-mode\fR. .IP "\fB\-mno\-faster\-structs\fR" 4 .IX Item "-mno-faster-structs" .PD 0 @@ -18135,10 +18310,10 @@ the rules of the \s-1ABI\s0. Set the instruction set, register set, and instruction scheduling parameters for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are \&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, -\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, -\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, -\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, -and \fBniagara4\fR. +\&\fBleon\fR, \fBleon3\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. .Sp Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, which selects the best architecture option for the host processor. @@ -18157,7 +18332,7 @@ implementations. cypress .IP "v8" 4 .IX Item "v8" -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 .IP "sparclite" 4 .IX Item "sparclite" f930, f934, sparclite86x @@ -18220,10 +18395,11 @@ option \fB\-mcpu=\fR\fIcpu_type\fR does. The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, -\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, -\&\fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and \fBniagara4\fR. With -native Solaris and GNU/Linux toolchains, \fBnative\fR can also be used. +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and +\&\fBniagara4\fR. With native Solaris and GNU/Linux toolchains, \fBnative\fR +can also be used. .IP "\fB\-mv8plus\fR" 4 .IX Item "-mv8plus" .PD 0 @@ -18298,6 +18474,10 @@ later. .IX Item "-mfix-at697f" Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. .PP These \fB\-m\fR options are supported in addition to the above on \s-1SPARC\-V9\s0 processors in 64\-bit environments: @@ -18977,7 +19157,7 @@ every cross-file call, not just those that really are out of range. .IX Subsection "zSeries Options" .PP These are listed under -.SS "Options for Code Generation Conventions" +.Sh "Options for Code Generation Conventions" .IX Subsection "Options for Code Generation Conventions" These machine-independent options control the interface conventions used in code generation. diff --git a/gcc-4.8/gcc/doc/gc-analyze.1 b/gcc-4.8/gcc/doc/gc-analyze.1 index b996198bd..c149d2ad1 100644 --- a/gcc-4.8/gcc/doc/gc-analyze.1 +++ b/gcc-4.8/gcc/doc/gc-analyze.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GC-ANALYZE 1" -.TH GC-ANALYZE 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GC-ANALYZE 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/gcc.1 b/gcc-4.8/gcc/doc/gcc.1 index 88e400d95..24005b6cc 100644 --- a/gcc-4.8/gcc/doc/gcc.1 +++ b/gcc-4.8/gcc/doc/gcc.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCC 1" -.TH GCC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -180,7 +188,7 @@ these have both positive and negative forms; the negative form of only one of these two forms, whichever one is not the default. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Option Summary" +.Sh "Option Summary" .IX Subsection "Option Summary" Here is a summary of all the options, grouped by type. Explanations are in the following sections. @@ -190,7 +198,7 @@ in the following sections. \&\-pipe \-pass\-exit\-codes \&\-x\fR \fIlanguage\fR \fB\-v \-### \-\-help\fR[\fB=\fR\fIclass\fR[\fB,...\fR]] \fB\-\-target\-help \&\-\-version \-wrapper @\fR\fIfile\fR \fB\-fplugin=\fR\fIfile\fR \fB\-fplugin\-arg\-\fR\fIname\fR\fB=\fR\fIarg\fR -\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIarg\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR +\&\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] \fB\-fada\-spec\-parent=\fR\fIunit\fR \fB\-fdump\-go\-spec=\fR\fIfile\fR .IP "\fIC Language Options\fR" 4 .IX Item "C Language Options" \&\fB\-ansi \-std=\fR\fIstandard\fR \fB\-fgnu89\-inline @@ -867,7 +875,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mno\-recip\-precision \&\-mveclibabi=\fR\fItype\fR \fB\-mfriz \-mno\-friz \&\-mpointers\-to\-nested\-functions \-mno\-pointers\-to\-nested\-functions -\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect\fR +\&\-msave\-toc\-indirect \-mno\-save\-toc\-indirect +\&\-mpower8\-fusion \-mno\-mpower8\-fusion \-mpower8\-vector \-mno\-power8\-vector +\&\-mcrypto \-mno\-crypto \-mdirect\-move \-mno\-direct\-move +\&\-mquad\-memory \-mno\-quad\-memory +\&\-mquad\-memory\-atomic \-mno\-quad\-memory\-atomic +\&\-mcompat\-align\-parm \-mno\-compat\-align\-parm\fR .Sp \&\fI\s-1RX\s0 Options\fR \&\fB\-m64bit\-doubles \-m32bit\-doubles \-fpu \-nofpu @@ -891,7 +904,8 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-msmall\-exec \-mno\-small\-exec \-mmvcle \-mno\-mvcle \&\-m64 \-m31 \-mdebug \-mno\-debug \-mesa \-mzarch \&\-mtpf\-trace \-mno\-tpf\-trace \-mfused\-madd \-mno\-fused\-madd -\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard\fR +\&\-mwarn\-framesize \-mwarn\-dynamicstack \-mstack\-size \-mstack\-guard +\&\-mhotpatch[=\fR\fIhalfwords\fR\fB] \-mno\-hotpatch\fR .Sp \&\fIScore Options\fR \&\fB\-meb \-mel @@ -936,11 +950,12 @@ See \s-1RS/6000\s0 and PowerPC Options. \&\-mhard\-quad\-float \-msoft\-quad\-float \&\-mstack\-bias \-mno\-stack\-bias \&\-munaligned\-doubles \-mno\-unaligned\-doubles +\&\-muser\-mode \-mno\-user\-mode \&\-mv8plus \-mno\-v8plus \-mvis \-mno\-vis \&\-mvis2 \-mno\-vis2 \-mvis3 \-mno\-vis3 \&\-mcbcond \-mno\-cbcond \&\-mfmaf \-mno\-fmaf \-mpopc \-mno\-popc -\&\-mfix\-at697f\fR +\&\-mfix\-at697f \-mfix\-ut699\fR .Sp \&\fI\s-1SPU\s0 Options\fR \&\fB\-mwarn\-reloc \-merror\-reloc @@ -1029,7 +1044,7 @@ See S/390 and zSeries Options. \&\fB\-fstack\-reuse=\fR\fIreuse_level\fR \&\fB\-ftrapv \-fwrapv \-fbounds\-check \&\-fvisibility \-fstrict\-volatile\-bitfields \-fsync\-libcalls\fR -.SS "Options Controlling the Kind of Output" +.Sh "Options Controlling the Kind of Output" .IX Subsection "Options Controlling the Kind of Output" Compilation can involve up to four stages: preprocessing, compilation proper, assembly and linking, always in that order. \s-1GCC\s0 is capable of @@ -1459,8 +1474,11 @@ Define an argument called \fIkey\fR with a value of \fIvalue\fR for the plugin called \fIname\fR. .IP "\fB\-fdump\-ada\-spec\fR[\fB\-slim\fR]" 4 .IX Item "-fdump-ada-spec[-slim]" -For C and \*(C+ source and include files, generate corresponding Ada -specs. +For C and \*(C+ source and include files, generate corresponding Ada specs. +.IP "\fB\-fada\-spec\-parent=\fR\fIunit\fR" 4 +.IX Item "-fada-spec-parent=unit" +In conjunction with \fB\-fdump\-ada\-spec\fR[\fB\-slim\fR] above, generate +Ada specs as child units of parent \fIunit\fR. .IP "\fB\-fdump\-go\-spec=\fR\fIfile\fR" 4 .IX Item "-fdump-go-spec=file" For input files in any language, generate corresponding Go @@ -1481,8 +1499,8 @@ option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The \fIfile\fR may itself contain additional @\fIfile\fR options; any such options will be processed recursively. -.SS "Compiling \*(C+ Programs" -.IX Subsection "Compiling Programs" +.Sh "Compiling \*(C+ Programs" +.IX Subsection "Compiling Programs" \&\*(C+ source files conventionally use one of the suffixes \fB.C\fR, \&\fB.cc\fR, \fB.cpp\fR, \fB.CPP\fR, \fB.c++\fR, \fB.cp\fR, or \&\fB.cxx\fR; \*(C+ header files often use \fB.hh\fR, \fB.hpp\fR, @@ -1505,7 +1523,7 @@ When you compile \*(C+ programs, you may specify many of the same command-line options that you use for compiling programs in any language; or command-line options meaningful for C and related languages; or options that are meaningful only for \*(C+ programs. -.SS "Options Controlling C Dialect" +.Sh "Options Controlling C Dialect" .IX Subsection "Options Controlling C Dialect" The following options control the dialect of C (or languages derived from C, such as \*(C+, Objective-C and Objective\-\*(C+) that the compiler @@ -1892,8 +1910,8 @@ These options control whether a bit-field is signed or unsigned, when the declaration does not use either \f(CW\*(C`signed\*(C'\fR or \f(CW\*(C`unsigned\*(C'\fR. By default, such a bit-field is signed, because this is consistent: the basic integer types such as \f(CW\*(C`int\*(C'\fR are signed types. -.SS "Options Controlling \*(C+ Dialect" -.IX Subsection "Options Controlling Dialect" +.Sh "Options Controlling \*(C+ Dialect" +.IX Subsection "Options Controlling Dialect" This section describes the command-line options that are only meaningful for \*(C+ programs. You can also use most of the \s-1GNU\s0 compiler options regardless of what language your program is in. For example, you @@ -2250,7 +2268,7 @@ Do not assume \fBinline\fR for functions defined inside a class scope. functions have linkage like inline functions; they just aren't inlined by default. .IP "\fB\-Wabi\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wabi (C, Objective-C, and Objective- only)" +.IX Item "-Wabi (C, Objective-C, and Objective- only)" Warn when G++ generates code that is probably not compatible with the vendor-neutral \*(C+ \s-1ABI\s0. Although an effort has been made to warn about all such cases, there are probably some cases that are not warned about, @@ -2562,7 +2580,7 @@ Warn when overload resolution chooses a promotion from unsigned or enumerated type to a signed type, over a conversion to an unsigned type of the same size. Previous versions of G++ tried to preserve unsignedness, but the standard mandates the current behavior. -.SS "Options Controlling Objective-C and Objective\-\*(C+ Dialects" +.Sh "Options Controlling Objective-C and Objective\-\*(C+ Dialects" .IX Subsection "Options Controlling Objective-C and Objective- Dialects" (\s-1NOTE:\s0 This manual does not describe the Objective-C and Objective\-\*(C+ languages themselves. @@ -2759,7 +2777,7 @@ that methods and selectors must be declared before being used. .IX Item "-print-objc-runtime-info" Generate C header describing the largest structure that is passed by value, if any. -.SS "Options to Control Diagnostic Messages Formatting" +.Sh "Options to Control Diagnostic Messages Formatting" .IX Subsection "Options to Control Diagnostic Messages Formatting" Traditionally, diagnostic messages have been formatted irrespective of the output device's aspect (e.g. its width, ...). You can use the @@ -2800,7 +2818,7 @@ option is known to the diagnostic machinery). Specifying the By default, each diagnostic emitted includes the original source line and a caret '^' indicating the column. This option suppresses this information. -.SS "Options to Request or Suppress Warnings" +.Sh "Options to Request or Suppress Warnings" .IX Subsection "Options to Request or Suppress Warnings" Warnings are diagnostic messages that report constructions that are not inherently erroneous but that are risky or suggest there @@ -3186,7 +3204,7 @@ enabled by default and it is made into an error by Same as \fB\-Wimplicit\-int\fR and \fB\-Wimplicit\-function\-declaration\fR. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wignored\-qualifiers\fR (C and \*(C+ only)" 4 -.IX Item "-Wignored-qualifiers (C and only)" +.IX Item "-Wignored-qualifiers (C and only)" Warn if the return type of a function has a type qualifier such as \f(CW\*(C`const\*(C'\fR. For \s-1ISO\s0 C such a type qualifier has no effect, since the value returned by a function is not an lvalue. @@ -3358,7 +3376,7 @@ between \fB\-Wswitch\fR and this option is that this option gives a warning about an omitted enumeration code even if there is a \&\f(CW\*(C`default\*(C'\fR label. .IP "\fB\-Wsync\-nand\fR (C and \*(C+ only)" 4 -.IX Item "-Wsync-nand (C and only)" +.IX Item "-Wsync-nand (C and only)" Warn when \f(CW\*(C`_\|_sync_fetch_and_nand\*(C'\fR and \f(CW\*(C`_\|_sync_nand_and_fetch\*(C'\fR built-in functions are used. These functions changed semantics in \s-1GCC\s0 4.4. .IP "\fB\-Wtrigraphs\fR" 4 @@ -3397,7 +3415,7 @@ This warning is enabled by \fB\-Wall\fR. .Sp To suppress this warning use the \fBunused\fR attribute. .IP "\fB\-Wunused\-local\-typedefs\fR (C, Objective-C, \*(C+ and Objective\-\*(C+ only)" 4 -.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" +.IX Item "-Wunused-local-typedefs (C, Objective-C, and Objective- only)" Warn when a typedef locally defined in a function is not used. This warning is enabled by \fB\-Wall\fR. .IP "\fB\-Wunused\-parameter\fR" 4 @@ -4355,7 +4373,7 @@ a suffix. When used together with \fB\-Wsystem\-headers\fR it warns about such constants in system header files. This can be useful when preparing code to use with the \f(CW\*(C`FLOAT_CONST_DECIMAL64\*(C'\fR pragma from the decimal floating-point extension to C99. -.SS "Options for Debugging Your Program or \s-1GCC\s0" +.Sh "Options for Debugging Your Program or \s-1GCC\s0" .IX Subsection "Options for Debugging Your Program or GCC" \&\s-1GCC\s0 has various special options that are used for debugging either your program or \s-1GCC:\s0 @@ -5859,7 +5877,7 @@ in that compilation unit, for example if, in the debugger, you want to cast a value to a type that is not actually used in your program (but is declared). More often, however, this results in a significant amount of wasted space. -.SS "Options That Control Optimization" +.Sh "Options That Control Optimization" .IX Subsection "Options That Control Optimization" These options control various sorts of optimizations. .PP @@ -8968,7 +8986,7 @@ seeking a basis for a new straight-line strength reduction candidate. .RE .RS 4 .RE -.SS "Options Controlling the Preprocessor" +.Sh "Options Controlling the Preprocessor" .IX Subsection "Options Controlling the Preprocessor" These options control the C preprocessor, which is run on each C source file before actual compilation. @@ -9770,7 +9788,7 @@ header file is printed with \fB...x\fR and a valid one with \fB...!\fR . .PD Print out \s-1GNU\s0 \s-1CPP\s0's version number. With one dash, proceed to preprocess as normal. With two dashes, exit immediately. -.SS "Passing Options to the Assembler" +.Sh "Passing Options to the Assembler" .IX Subsection "Passing Options to the Assembler" You can pass options to the assembler. .IP "\fB\-Wa,\fR\fIoption\fR" 4 @@ -9785,7 +9803,7 @@ recognize. .Sp If you want to pass an option that takes an argument, you must use \&\fB\-Xassembler\fR twice, once for the option and once for the argument. -.SS "Options for Linking" +.Sh "Options for Linking" .IX Subsection "Options for Linking" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is @@ -10024,7 +10042,7 @@ linker. When using the \s-1GNU\s0 linker, you can also get the same effect with Pretend the symbol \fIsymbol\fR is undefined, to force linking of library modules to define it. You can use \fB\-u\fR multiple times with different symbols to force loading of additional library modules. -.SS "Options for Directory Search" +.Sh "Options for Directory Search" .IX Subsection "Options for Directory Search" These options specify directories to search for header files, for libraries and for parts of the compiler: @@ -10159,13 +10177,13 @@ by default, but it is often satisfactory. \&\fB\-I\-\fR does not inhibit the use of the standard system directories for header files. Thus, \fB\-I\-\fR and \fB\-nostdinc\fR are independent. -.SS "Specifying Target Machine and Compiler Version" +.Sh "Specifying Target Machine and Compiler Version" .IX Subsection "Specifying Target Machine and Compiler Version" The usual way to run \s-1GCC\s0 is to run the executable called \fBgcc\fR, or \&\fImachine\fR\fB\-gcc\fR when cross-compiling, or \&\fImachine\fR\fB\-gcc\-\fR\fIversion\fR to run a version other than the one that was installed last. -.SS "Hardware Models and Configurations" +.Sh "Hardware Models and Configurations" .IX Subsection "Hardware Models and Configurations" Each target machine types can have its own special options, starting with \fB\-m\fR, to choose among various @@ -10489,11 +10507,31 @@ order. That is, a byte order of the form \fB32107654\fR. Note: this option should only be used if you require compatibility with code for big-endian \s-1ARM\s0 processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -.IP "\fB\-mcpu=\fR\fIname\fR" 4 -.IX Item "-mcpu=name" -This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, +.IP "\fB\-march=\fR\fIname\fR" 4 +.IX Item "-march=name" +This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, +\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, +\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, +\&\fBarmv6\fR, \fBarmv6j\fR, +\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, +\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, \fBarmv7e\-m\fR +\&\fBarmv8\-a\fR, +\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.Sp +\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. +.IP "\fB\-mtune=\fR\fIname\fR" 4 +.IX Item "-mtune=name" +This option specifies the name of the target \s-1ARM\s0 processor for +which \s-1GCC\s0 should tune the performance of the code. +For some \s-1ARM\s0 implementations better performance can be obtained by using +this option. +Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBarm3\fR, \fBarm6\fR, \fBarm60\fR, \fBarm600\fR, \fBarm610\fR, \&\fBarm620\fR, \fBarm7\fR, \fBarm7m\fR, \fBarm7d\fR, \fBarm7dm\fR, \&\fBarm7di\fR, \fBarm7dmi\fR, \fBarm70\fR, \fBarm700\fR, @@ -10521,25 +10559,6 @@ assembly code. Permissible names are: \fBarm2\fR, \fBarm250\fR, \&\fBfa526\fR, \fBfa626\fR, \&\fBfa606te\fR, \fBfa626te\fR, \fBfmp626\fR, \fBfa726te\fR. .Sp -\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is -equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. -See \fB\-mtune\fR for more information. -.Sp -\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. -.IP "\fB\-mtune=\fR\fIname\fR" 4 -.IX Item "-mtune=name" -This option is very similar to the \fB\-mcpu=\fR option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that \s-1GCC\s0 should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the \s-1CPU\s0 specified by a \fB\-mcpu=\fR option. -For some \s-1ARM\s0 implementations better performance can be obtained by using -this option. -.Sp \&\fB\-mtune=generic\-\fR\fIarch\fR specifies that \s-1GCC\s0 should tune the performance for a blend of processors within architecture \fIarch\fR. The aim is to generate code that run well on the current most popular @@ -10551,21 +10570,23 @@ this option may change in future \s-1GCC\s0 versions as \s-1CPU\s0 models come a of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -.IP "\fB\-march=\fR\fIname\fR" 4 -.IX Item "-march=name" -This specifies the name of the target \s-1ARM\s0 architecture. \s-1GCC\s0 uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the \fB\-mcpu=\fR option. Permissible names are: \fBarmv2\fR, -\&\fBarmv2a\fR, \fBarmv3\fR, \fBarmv3m\fR, \fBarmv4\fR, \fBarmv4t\fR, -\&\fBarmv5\fR, \fBarmv5t\fR, \fBarmv5e\fR, \fBarmv5te\fR, -\&\fBarmv6\fR, \fBarmv6j\fR, -\&\fBarmv6t2\fR, \fBarmv6z\fR, \fBarmv6zk\fR, \fBarmv6\-m\fR, -\&\fBarmv7\fR, \fBarmv7\-a\fR, \fBarmv7\-r\fR, \fBarmv7\-m\fR, -\&\fBarmv8\-a\fR, -\&\fBiwmmxt\fR, \fBiwmmxt2\fR, \fBep9312\fR. +.IP "\fB\-mcpu=\fR\fIname\fR" 4 +.IX Item "-mcpu=name" +This specifies the name of the target \s-1ARM\s0 processor. \s-1GCC\s0 uses this name +to derive the name of the target \s-1ARM\s0 architecture (as if specified +by \fB\-march\fR) and the \s-1ARM\s0 processor type for which to tune for +performance (as if specified by \fB\-mtune\fR). Where this option +is used in conjunction with \fB\-march\fR or \fB\-mtune\fR, +those options take precedence over the appropriate part of this option. .Sp -\&\fB\-march=native\fR causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +\&\fB\-mtune\fR. +.Sp +\&\fB\-mcpu=generic\-\fR\fIarch\fR is also permissible, and is +equivalent to \fB\-march=\fR\fIarch\fR \fB\-mtune=generic\-\fR\fIarch\fR. +See \fB\-mtune\fR for more information. +.Sp +\&\fB\-mcpu=native\fR causes the compiler to auto-detect the \s-1CPU\s0 of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -10649,8 +10670,11 @@ responsible for initializing this register with an appropriate value before execution begins. .IP "\fB\-mpic\-register=\fR\fIreg\fR" 4 .IX Item "-mpic-register=reg" -Specify the register to be used for \s-1PIC\s0 addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for \s-1PIC\s0 addressing. +For standard \s-1PIC\s0 base case, the default will be any suitable register +determined by compiler. For single \s-1PIC\s0 base case, the default is +\&\fBR9\fR if target is \s-1EABI\s0 based or stack-checking is enabled, +otherwise the default is \fBR10\fR. .IP "\fB\-mpoke\-function\-name\fR" 4 .IX Item "-mpoke-function-name" Write the name of each function into the text section, directly @@ -10805,7 +10829,7 @@ The default for this option is@tie{}\f(CW\*(C`avr2\*(C'\fR. .el .IP "\f(CWavr5\fR" 4 .IX Item "avr5" \&\*(L"Enhanced\*(R" devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. +\&\fImcu\fR\f(CW@tie\fR{}= \f(CW\*(C`ata5790\*(C'\fR, \f(CW\*(C`ata5790n\*(C'\fR, \f(CW\*(C`ata5795\*(C'\fR, \f(CW\*(C`atmega16\*(C'\fR, \f(CW\*(C`atmega16a\*(C'\fR, \f(CW\*(C`atmega16hva\*(C'\fR, \f(CW\*(C`atmega16hva2\*(C'\fR, \f(CW\*(C`atmega16hvb\*(C'\fR, \f(CW\*(C`atmega16hvbrevb\*(C'\fR, \f(CW\*(C`atmega16m1\*(C'\fR, \f(CW\*(C`atmega16u4\*(C'\fR, \f(CW\*(C`atmega161\*(C'\fR, \f(CW\*(C`atmega162\*(C'\fR, \f(CW\*(C`atmega163\*(C'\fR, \f(CW\*(C`atmega164a\*(C'\fR, \f(CW\*(C`atmega164p\*(C'\fR, \f(CW\*(C`atmega164pa\*(C'\fR, \f(CW\*(C`atmega165\*(C'\fR, \f(CW\*(C`atmega165a\*(C'\fR, \f(CW\*(C`atmega165p\*(C'\fR, \f(CW\*(C`atmega165pa\*(C'\fR, \f(CW\*(C`atmega168\*(C'\fR, \f(CW\*(C`atmega168a\*(C'\fR, \f(CW\*(C`atmega168p\*(C'\fR, \f(CW\*(C`atmega168pa\*(C'\fR, \f(CW\*(C`atmega169\*(C'\fR, \f(CW\*(C`atmega169a\*(C'\fR, \f(CW\*(C`atmega169p\*(C'\fR, \f(CW\*(C`atmega169pa\*(C'\fR, \f(CW\*(C`atmega26hvg\*(C'\fR, \f(CW\*(C`atmega32\*(C'\fR, \f(CW\*(C`atmega32a\*(C'\fR, \f(CW\*(C`atmega32c1\*(C'\fR, \f(CW\*(C`atmega32hvb\*(C'\fR, \f(CW\*(C`atmega32hvbrevb\*(C'\fR, \f(CW\*(C`atmega32m1\*(C'\fR, \f(CW\*(C`atmega32u4\*(C'\fR, \f(CW\*(C`atmega32u6\*(C'\fR, \f(CW\*(C`atmega323\*(C'\fR, \f(CW\*(C`atmega324a\*(C'\fR, \f(CW\*(C`atmega324p\*(C'\fR, \f(CW\*(C`atmega324pa\*(C'\fR, \f(CW\*(C`atmega325\*(C'\fR, \f(CW\*(C`atmega325a\*(C'\fR, \f(CW\*(C`atmega325p\*(C'\fR, \f(CW\*(C`atmega3250\*(C'\fR, \f(CW\*(C`atmega3250a\*(C'\fR, \f(CW\*(C`atmega3250p\*(C'\fR, \f(CW\*(C`atmega3250pa\*(C'\fR, \f(CW\*(C`atmega328\*(C'\fR, \f(CW\*(C`atmega328p\*(C'\fR, \f(CW\*(C`atmega329\*(C'\fR, \f(CW\*(C`atmega329a\*(C'\fR, \f(CW\*(C`atmega329p\*(C'\fR, \f(CW\*(C`atmega329pa\*(C'\fR, \f(CW\*(C`atmega3290\*(C'\fR, \f(CW\*(C`atmega3290a\*(C'\fR, \f(CW\*(C`atmega3290p\*(C'\fR, \f(CW\*(C`atmega3290pa\*(C'\fR, \f(CW\*(C`atmega406\*(C'\fR, \f(CW\*(C`atmega48hvf\*(C'\fR, \f(CW\*(C`atmega64\*(C'\fR, \f(CW\*(C`atmega64a\*(C'\fR, \f(CW\*(C`atmega64c1\*(C'\fR, \f(CW\*(C`atmega64hve\*(C'\fR, \f(CW\*(C`atmega64m1\*(C'\fR, \f(CW\*(C`atmega64rfa2\*(C'\fR, \f(CW\*(C`atmega64rfr2\*(C'\fR, \f(CW\*(C`atmega640\*(C'\fR, \f(CW\*(C`atmega644\*(C'\fR, \f(CW\*(C`atmega644a\*(C'\fR, \f(CW\*(C`atmega644p\*(C'\fR, \f(CW\*(C`atmega644pa\*(C'\fR, \f(CW\*(C`atmega645\*(C'\fR, \f(CW\*(C`atmega645a\*(C'\fR, \f(CW\*(C`atmega645p\*(C'\fR, \f(CW\*(C`atmega6450\*(C'\fR, \f(CW\*(C`atmega6450a\*(C'\fR, \f(CW\*(C`atmega6450p\*(C'\fR, \f(CW\*(C`atmega649\*(C'\fR, \f(CW\*(C`atmega649a\*(C'\fR, \f(CW\*(C`atmega649p\*(C'\fR, \f(CW\*(C`atmega6490\*(C'\fR, \f(CW\*(C`atmega6490a\*(C'\fR, \f(CW\*(C`atmega6490p\*(C'\fR, \f(CW\*(C`at90can32\*(C'\fR, \f(CW\*(C`at90can64\*(C'\fR, \f(CW\*(C`at90pwm161\*(C'\fR, \f(CW\*(C`at90pwm216\*(C'\fR, \f(CW\*(C`at90pwm316\*(C'\fR, \f(CW\*(C`at90scr100\*(C'\fR, \f(CW\*(C`at90usb646\*(C'\fR, \f(CW\*(C`at90usb647\*(C'\fR, \f(CW\*(C`at94k\*(C'\fR, \f(CW\*(C`m3000\*(C'\fR. .ie n .IP """avr51""" 4 .el .IP "\f(CWavr51\fR" 4 .IX Item "avr51" @@ -11043,7 +11067,7 @@ command-line option. .IX Item "-" tables you can specify the \fB\-fno\-jump\-tables\fR command-line option. .IP "\-" 4 -.IX Item "-" +.IX Item "-" .PD 0 .ie n .IP "\-" 4 .el .IP "\-" 4 @@ -11790,7 +11814,7 @@ an executable when linking, using the Darwin \fIlibtool\fR command. This causes \s-1GCC\s0's output file to have the \fI\s-1ALL\s0\fR subtype, instead of one controlled by the \fB\-mcpu\fR or \fB\-march\fR option. .IP "\fB\-allowable_client\fR \fIclient_name\fR" 4 -.IX Item "-allowable_client client_name" +.IX Item "-allowable_client client_name" .PD 0 .IP "\fB\-client_name\fR" 4 .IX Item "-client_name" @@ -12865,9 +12889,14 @@ Intel Core i7 \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SS Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, \&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0 and F16C instruction set support. +.IP "\fBcore\-avx2\fR" 4 +.IX Item "core-avx2" +Intel Core \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0, \s-1SSSE3\s0, +\&\s-1SSE4\s0.1, \s-1SSE4\s0.2, \s-1AVX\s0, \s-1AVX2\s0, \s-1AES\s0, \s-1PCLMUL\s0, \s-1FSGSBASE\s0, \s-1RDRND\s0, \s-1FMA\s0, \s-1BMI\s0, \s-1BMI2\s0 +and F16C instruction set support. .IP "\fBatom\fR" 4 .IX Item "atom" -Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 +Intel Atom \s-1CPU\s0 with 64\-bit extensions, \s-1MOVBE\s0, \s-1MMX\s0, \s-1SSE\s0, \s-1SSE2\s0, \s-1SSE3\s0 and \s-1SSSE3\s0 instruction set support. .IP "\fBk6\fR" 4 .IX Item "k6" @@ -16284,7 +16313,9 @@ following options: \&\fB\-maltivec \-mfprnd \-mhard\-float \-mmfcrf \-mmultiple \&\-mpopcntb \-mpopcntd \-mpowerpc64 \&\-mpowerpc\-gpopt \-mpowerpc\-gfxopt \-msingle\-float \-mdouble\-float -\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx\fR +\&\-msimple\-fpu \-mstring \-mmulhw \-mdlmzb \-mmfpgpr \-mvsx +\&\-mcrypto \-mdirect\-move \-mpower8\-fusion \-mpower8\-vector +\&\-mquad\-memory \-mquad\-memory\-atomic\fR .Sp The particular options set for any particular \s-1CPU\s0 varies between compiler versions, depending on what setting seems to produce optimal @@ -16331,6 +16362,36 @@ enable the use of built-in functions that allow more direct access to the AltiVec instruction set. You may also need to set \&\fB\-mabi=altivec\fR to adjust the current \s-1ABI\s0 with AltiVec \s-1ABI\s0 enhancements. +.Sp +When \fB\-maltivec\fR is used, rather than \fB\-maltivec=le\fR or +\&\fB\-maltivec=be\fR, the element order for Altivec intrinsics such +as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and \f(CW\*(C`vec_insert\*(C'\fR will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. +.IP "\fB\-maltivec=be\fR" 4 +.IX Item "-maltivec=be" +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. +.IP "\fB\-maltivec=le\fR" 4 +.IX Item "-maltivec=le" +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big\- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. +.Sp +The element order is used to interpret element numbers in Altivec +intrinsics such as \f(CW\*(C`vec_splat\*(C'\fR, \f(CW\*(C`vec_extract\*(C'\fR, and +\&\f(CW\*(C`vec_insert\*(C'\fR. By default, these will match array element order +corresponding to the endianness for the target. .IP "\fB\-mvrsave\fR" 4 .IX Item "-mvrsave" .PD 0 @@ -16399,6 +16460,61 @@ This option has been deprecated. Use \fB\-mspe\fR and Generate code that uses (does not use) vector/scalar (\s-1VSX\s0) instructions, and also enable the use of built-in functions that allow more direct access to the \s-1VSX\s0 instruction set. +.IP "\fB\-mcrypto\fR" 4 +.IX Item "-mcrypto" +.PD 0 +.IP "\fB\-mno\-crypto\fR" 4 +.IX Item "-mno-crypto" +.PD +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mdirect\-move\fR" 4 +.IX Item "-mdirect-move" +.PD 0 +.IP "\fB\-mno\-direct\-move\fR" 4 +.IX Item "-mno-direct-move" +.PD +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (\s-1VSX\s0) +registers that were added in version 2.07 of the PowerPC \s-1ISA\s0. +.IP "\fB\-mpower8\-fusion\fR" 4 +.IX Item "-mpower8-fusion" +.PD 0 +.IP "\fB\-mno\-power8\-fusion\fR" 4 +.IX Item "-mno-power8-fusion" +.PD +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. +.IP "\fB\-mpower8\-vector\fR" 4 +.IX Item "-mpower8-vector" +.PD 0 +.IP "\fB\-mno\-power8\-vector\fR" 4 +.IX Item "-mno-power8-vector" +.PD +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC \s-1ISA\s0. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. +.IP "\fB\-mquad\-memory\fR" 4 +.IX Item "-mquad-memory" +.PD 0 +.IP "\fB\-mno\-quad\-memory\fR" 4 +.IX Item "-mno-quad-memory" +.PD +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The \fB\-mquad\-memory\fR option requires use of +64\-bit mode. +.IP "\fB\-mquad\-memory\-atomic\fR" 4 +.IX Item "-mquad-memory-atomic" +.PD 0 +.IP "\fB\-mno\-quad\-memory\-atomic\fR" 4 +.IX Item "-mno-quad-memory-atomic" +.PD +Generate code that uses (does not use) the atomic quad word memory +instructions. The \fB\-mquad\-memory\-atomic\fR option requires use of +64\-bit mode. .IP "\fB\-mfloat\-gprs=\fR\fIyes/single/double/no\fR" 4 .IX Item "-mfloat-gprs=yes/single/double/no" .PD 0 @@ -16828,7 +16944,8 @@ Return structures smaller than 8 bytes in registers (as specified by the .IX Item "-mabi=abi-type" Extend the current \s-1ABI\s0 with a particular extension, or remove such extension. Valid values are \fIaltivec\fR, \fIno-altivec\fR, \fIspe\fR, -\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR. +\&\fIno-spe\fR, \fIibmlongdouble\fR, \fIieeelongdouble\fR, +\&\fIelfv1\fR, \fIelfv2\fR. .IP "\fB\-mabi=spe\fR" 4 .IX Item "-mabi=spe" Extend the current \s-1ABI\s0 with \s-1SPE\s0 \s-1ABI\s0 extensions. This does not change @@ -16845,6 +16962,18 @@ This is a PowerPC 32\-bit \s-1SYSV\s0 \s-1ABI\s0 option. .IX Item "-mabi=ieeelongdouble" Change the current \s-1ABI\s0 to use \s-1IEEE\s0 extended-precision long double. This is a PowerPC 32\-bit Linux \s-1ABI\s0 option. +.IP "\fB\-mabi=elfv1\fR" 4 +.IX Item "-mabi=elfv1" +Change the current \s-1ABI\s0 to use the ELFv1 \s-1ABI\s0. +This is the default \s-1ABI\s0 for big-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. +.IP "\fB\-mabi=elfv2\fR" 4 +.IX Item "-mabi=elfv2" +Change the current \s-1ABI\s0 to use the ELFv2 \s-1ABI\s0. +This is the default \s-1ABI\s0 for little-endian PowerPC 64\-bit Linux. +Overriding the default \s-1ABI\s0 requires special system support and is +likely to fail in spectacular ways. .IP "\fB\-mprototype\fR" 4 .IX Item "-mprototype" .PD 0 @@ -17132,6 +17261,25 @@ stack location in the function prologue if the function calls through a pointer on \s-1AIX\s0 and 64\-bit Linux systems. If the \s-1TOC\s0 value is not saved in the prologue, it is saved just before the call through the pointer. The \fB\-mno\-save\-toc\-indirect\fR option is the default. +.IP "\fB\-mcompat\-align\-parm\fR" 4 +.IX Item "-mcompat-align-parm" +.PD 0 +.IP "\fB\-mno\-compat\-align\-parm\fR" 4 +.IX Item "-mno-compat-align-parm" +.PD +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of \s-1GCC\s0. +.Sp +Older versions of \s-1GCC\s0 (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128\-bit boundary when that structure contained +a member requiring 128\-bit alignment. This is corrected in more +recent versions of \s-1GCC\s0. This option may be used to generate code +that is compatible with functions compiled with older versions of +\&\s-1GCC\s0. +.Sp +In this version of the compiler, the \fB\-mcompat\-align\-parm\fR +is the default, except when using the Linux ELFv2 \s-1ABI\s0. .PP \fI\s-1RX\s0 Options\fR .IX Subsection "RX Options" @@ -17514,6 +17662,23 @@ values have to be exact powers of 2 and \fIstack-size\fR has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by \fIstack-size\fR. The \fIstack-guard\fR option can only be used in conjunction with \fIstack-size\fR. +.IP "\fB\-mhotpatch[=\fR\fIhalfwords\fR\fB]\fR" 4 +.IX Item "-mhotpatch[=halfwords]" +.PD 0 +.IP "\fB\-mno\-hotpatch\fR" 4 +.IX Item "-mno-hotpatch" +.PD +If the hotpatch option is enabled, a \*(L"hot-patching\*(R" function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (\fIhalfwords\fR, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. +.Sp +This option can be overridden for individual functions with the +\&\f(CW\*(C`hotpatch\*(C'\fR attribute. .PP \fIScore Options\fR .IX Subsection "Score Options" @@ -18039,8 +18204,9 @@ These \fB\-m\fR options are supported on the \s-1SPARC:\s0 .IX Item "-mapp-regs" .PD Specify \fB\-mapp\-regs\fR to generate output using the global registers -2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. This -is the default. +2 through 4, which the \s-1SPARC\s0 \s-1SVR4\s0 \s-1ABI\s0 reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. .Sp To be fully \s-1SVR4\s0 ABI-compliant at the cost of some performance loss, specify \fB\-mno\-app\-regs\fR. You should compile libraries and system @@ -18116,6 +18282,15 @@ absolute address. Otherwise, it assumes they have 4\-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +.IP "\fB\-muser\-mode\fR" 4 +.IX Item "-muser-mode" +.PD 0 +.IP "\fB\-mno\-user\-mode\fR" 4 +.IX Item "-mno-user-mode" +.PD +Do not generate code that can only run in supervisor mode. This is relevant +only for the \f(CW\*(C`casa\*(C'\fR instruction emitted for the \s-1LEON3\s0 processor. The +default is \fB\-mno\-user\-mode\fR. .IP "\fB\-mno\-faster\-structs\fR" 4 .IX Item "-mno-faster-structs" .PD 0 @@ -18135,10 +18310,10 @@ the rules of the \s-1ABI\s0. Set the instruction set, register set, and instruction scheduling parameters for machine type \fIcpu_type\fR. Supported values for \fIcpu_type\fR are \&\fBv7\fR, \fBcypress\fR, \fBv8\fR, \fBsupersparc\fR, \fBhypersparc\fR, -\&\fBleon\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, \fBsparclite86x\fR, -\&\fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, \fBultrasparc\fR, -\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR, -and \fBniagara4\fR. +\&\fBleon\fR, \fBleon3\fR, \fBsparclite\fR, \fBf930\fR, \fBf934\fR, +\&\fBsparclite86x\fR, \fBsparclet\fR, \fBtsc701\fR, \fBv9\fR, +\&\fBultrasparc\fR, \fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, +\&\fBniagara3\fR and \fBniagara4\fR. .Sp Native Solaris and GNU/Linux toolchains also support the value \fBnative\fR, which selects the best architecture option for the host processor. @@ -18157,7 +18332,7 @@ implementations. cypress .IP "v8" 4 .IX Item "v8" -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 .IP "sparclite" 4 .IX Item "sparclite" f930, f934, sparclite86x @@ -18220,10 +18395,11 @@ option \fB\-mcpu=\fR\fIcpu_type\fR does. The same values for \fB\-mcpu=\fR\fIcpu_type\fR can be used for \&\fB\-mtune=\fR\fIcpu_type\fR, but the only useful values are those that select a particular \s-1CPU\s0 implementation. Those are \fBcypress\fR, -\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBf930\fR, \fBf934\fR, -\&\fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, \fBultrasparc3\fR, -\&\fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and \fBniagara4\fR. With -native Solaris and GNU/Linux toolchains, \fBnative\fR can also be used. +\&\fBsupersparc\fR, \fBhypersparc\fR, \fBleon\fR, \fBleon3\fR, \fBf930\fR, +\&\fBf934\fR, \fBsparclite86x\fR, \fBtsc701\fR, \fBultrasparc\fR, +\&\fBultrasparc3\fR, \fBniagara\fR, \fBniagara2\fR, \fBniagara3\fR and +\&\fBniagara4\fR. With native Solaris and GNU/Linux toolchains, \fBnative\fR +can also be used. .IP "\fB\-mv8plus\fR" 4 .IX Item "-mv8plus" .PD 0 @@ -18298,6 +18474,10 @@ later. .IX Item "-mfix-at697f" Enable the documented workaround for the single erratum of the Atmel \s-1AT697F\s0 processor (which corresponds to erratum #13 of the \s-1AT697E\s0 processor). +.IP "\fB\-mfix\-ut699\fR" 4 +.IX Item "-mfix-ut699" +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the \s-1UT699\s0 processor. .PP These \fB\-m\fR options are supported in addition to the above on \s-1SPARC\-V9\s0 processors in 64\-bit environments: @@ -18977,7 +19157,7 @@ every cross-file call, not just those that really are out of range. .IX Subsection "zSeries Options" .PP These are listed under -.SS "Options for Code Generation Conventions" +.Sh "Options for Code Generation Conventions" .IX Subsection "Options for Code Generation Conventions" These machine-independent options control the interface conventions used in code generation. diff --git a/gcc-4.8/gcc/doc/gcc.info b/gcc-4.8/gcc/doc/gcc.info index e5a735552..cb0d668de 100644 --- a/gcc-4.8/gcc/doc/gcc.info +++ b/gcc-4.8/gcc/doc/gcc.info @@ -1,5 +1,5 @@ -This is doc/gcc.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/gcc.texi. +This is doc/gcc.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/gcc.texi. Copyright (C) 1988-2013 Free Software Foundation, Inc. @@ -58,7 +58,7 @@ Introduction This manual documents how to use the GNU compilers, as well as their features and incompatibilities, and how to report bugs. It corresponds -to the compilers (GCC) version 4.8.1. The internals of the GNU +to the compilers (GCC) version 4.8.3. The internals of the GNU compilers, including how to port them to new targets and some information about how to write front ends for new languages, are documented in a separate manual. *Note Introduction: (gccint)Top. @@ -264,7 +264,7 @@ experimental support for the second ISO C++ standard (2011). The original ISO C++ standard was published as the ISO standard (ISO/IEC 14882:1998) and amended by a Technical Corrigenda published in -2003 (ISO/IEC 14882:2003). These standards are referred to as C++98 and +2003 (ISO/IEC 14882:2003). These standards are referred to as C++98 and C++03, respectively. GCC implements the majority of C++98 (`export' is a notable exception) and most of the changes in C++03. To select this standard in GCC, use one of the options `-ansi', `-std=c++98', or @@ -323,7 +323,7 @@ at a number of web sites: * `http://objc.toodarkpark.net' is the same document in another format; - * + * `http://developer.apple.com/mac/library/documentation/Cocoa/Conceptual/ObjectiveC/' has an updated version but make sure you search for "Object Oriented Programming and the Objective-C Programming Language 1.0", @@ -349,7 +349,7 @@ by GCC 4.0, and to produce an error if one of the new features is used. GCC has currently no support for non-fragile instance variables. The authoritative manual on Objective-C 2.0 is available from Apple: - * + * `http://developer.apple.com/mac/library/documentation/Cocoa/Conceptual/ObjectiveC/' For more information concerning the history of Objective-C that is @@ -463,7 +463,7 @@ _Overall Options_ -pipe -pass-exit-codes -x LANGUAGE -v -### --help[=CLASS[,...]] --target-help --version -wrapper @FILE -fplugin=FILE -fplugin-arg-NAME=ARG - -fdump-ada-spec[-slim] -fada-spec-parent=ARG -fdump-go-spec=FILE + -fdump-ada-spec[-slim] -fada-spec-parent=UNIT -fdump-go-spec=FILE _C Language Options_ *Note Options Controlling C Dialect: C Dialect Options. @@ -1155,6 +1155,11 @@ _Machine Dependent Options_ -mveclibabi=TYPE -mfriz -mno-friz -mpointers-to-nested-functions -mno-pointers-to-nested-functions -msave-toc-indirect -mno-save-toc-indirect + -mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector + -mcrypto -mno-crypto -mdirect-move -mno-direct-move + -mquad-memory -mno-quad-memory + -mquad-memory-atomic -mno-quad-memory-atomic + -mcompat-align-parm -mno-compat-align-parm _RX Options_ -m64bit-doubles -m32bit-doubles -fpu -nofpu @@ -1179,6 +1184,7 @@ _Machine Dependent Options_ -m64 -m31 -mdebug -mno-debug -mesa -mzarch -mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd -mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard + -mhotpatch[=HALFWORDS] -mno-hotpatch _Score Options_ -meb -mel @@ -1223,11 +1229,12 @@ _Machine Dependent Options_ -mhard-quad-float -msoft-quad-float -mstack-bias -mno-stack-bias -munaligned-doubles -mno-unaligned-doubles + -muser-mode -mno-user-mode -mv8plus -mno-v8plus -mvis -mno-vis -mvis2 -mno-vis2 -mvis3 -mno-vis3 -mcbcond -mno-cbcond -mfmaf -mno-fmaf -mpopc -mno-popc - -mfix-at697f + -mfix-at697f -mfix-ut699 _SPU Options_ -mwarn-reloc -merror-reloc @@ -1596,7 +1603,7 @@ do nothing at all. `params' Display the values recognized by the `--param' option. - LANGUAGE + LANGUAGE Display the options supported for LANGUAGE, where LANGUAGE is the name of one of the languages supported in this version of GCC. @@ -1704,10 +1711,14 @@ do nothing at all. `-fdump-ada-spec[-slim]' For C and C++ source and include files, generate corresponding Ada - specs. *Note Generating Ada Bindings for C and C++ headers: + specs. *Note Generating Ada Bindings for C and C++ headers: (gnat_ugn)Generating Ada Bindings for C and C++ headers, which provides detailed documentation on this feature. +`-fada-spec-parent=UNIT' + In conjunction with `-fdump-ada-spec[-slim]' above, generate Ada + specs as child units of parent UNIT. + `-fdump-go-spec=FILE' For input files in any language, generate corresponding Go declarations in FILE. This generates Go `const', `type', `var', @@ -1806,7 +1817,7 @@ accepts: affected. `-std=' - Determine the language standard. *Note Language Standards + Determine the language standard. *Note Language Standards Supported by GCC: Standards, for details of these standard versions. This option is currently only supported when compiling C or C++. @@ -1857,7 +1868,7 @@ accepts: `gnu90' `gnu89' - GNU dialect of ISO C90 (including some C99 features). This is + GNU dialect of ISO C90 (including some C99 features). This is the default for C code. `gnu99' @@ -2578,7 +2589,7 @@ have meanings only for C++ programs: changes at this point include: * For SysV/x86-64, unions with `long double' members are passed - in memory as specified in psABI. For example: + in memory as specified in psABI. For example: union U { long double ld; @@ -2597,7 +2608,7 @@ have meanings only for C++ programs: `-Wdelete-non-virtual-dtor (C++ and Objective-C++ only)' Warn when `delete' is used to destroy an instance of a class that - has virtual functions and non-virtual destructor. It is unsafe to + has virtual functions and non-virtual destructor. It is unsafe to delete an instance of a derived class through a pointer to a base class if the base class does not have a virtual destructor. This warning is enabled by `-Wall'. @@ -2681,9 +2692,9 @@ have meanings only for C++ programs: * Item 11: Define a copy constructor and an assignment operator for classes with dynamically-allocated memory. - * Item 12: Prefer initialization to assignment in constructors. + * Item 12: Prefer initialization to assignment in constructors. - * Item 14: Make destructors virtual in base classes. + * Item 14: Make destructors virtual in base classes. * Item 15: Have `operator=' return a reference to `*this'. @@ -2694,7 +2705,7 @@ have meanings only for C++ programs: Also warn about violations of the following style guidelines from Scott Meyers' `More Effective C++' book: - * Item 6: Distinguish between prefix and postfix forms of + * Item 6: Distinguish between prefix and postfix forms of increment and decrement operators. * Item 7: Never overload `&&', `||', or `,'. @@ -2825,7 +2836,7 @@ and Objective-C++ programs: support for properties and other Objective-C 2.0 additions. Version 1 is the traditional (32-bit) ABI with support for properties and other Objective-C 2.0 additions. Version 2 is the - modern (64-bit) ABI. If nothing is specified, the default is + modern (64-bit) ABI. If nothing is specified, the default is Version 0 on 32-bit target machines, and Version 2 on 64-bit target machines. @@ -3624,9 +3635,9 @@ present. `-Wunused-value' Warn whenever a statement computes a result that is explicitly not - used. To suppress this warning cast the unused expression to + used. To suppress this warning cast the unused expression to `void'. This includes an expression-statement or the left-hand - side of a comma expression that contains no side effects. For + side of a comma expression that contains no side effects. For example, an expression such as `x[i,j]' causes a warning, while `x[(void)i,j]' does not. @@ -3686,7 +3697,7 @@ present. } If the value of `y' is always 1, 2 or 3, then `x' is always - initialized, but GCC doesn't know this. To suppress the warning, + initialized, but GCC doesn't know this. To suppress the warning, you need to provide a default case with assert(0) or similar code. This option also warns when a non-volatile automatic variable @@ -3808,7 +3819,7 @@ present. level gives a very large number of false positives. `-Wsuggest-attribute=[pure|const|noreturn|format]' - Warn for cases where adding an attribute may be beneficial. The + Warn for cases where adding an attribute may be beneficial. The attributes currently supported are listed below. `-Wsuggest-attribute=pure' @@ -3818,7 +3829,7 @@ present. `pure', `const' or `noreturn'. The compiler only warns for functions visible in other compilation units or (in the case of `pure' and `const') if it cannot prove that the function - returns normally. A function returns normally if it doesn't + returns normally. A function returns normally if it doesn't contain an infinite loop or return abnormally by throwing, calling `abort()' or trapping. This analysis requires option `-fipa-pure-const', which is enabled by default at `-O' and @@ -3872,10 +3883,10 @@ present. Warn about trampolines generated for pointers to nested functions. A trampoline is a small piece of data or code that is created at - run time on the stack when the address of a nested function is - taken, and is used to call the nested function indirectly. For - some targets, it is made up of data only and thus requires no - special treatment. But, for most targets, it is made up of code + run time on the stack when the address of a nested function is + taken, and is used to call the nested function indirectly. For + some targets, it is made up of data only and thus requires no + special treatment. But, for most targets, it is made up of code and thus requires the stack to be made executable in order for the program to work properly. @@ -3997,7 +4008,7 @@ present. `-Wshadow' Warn whenever a local variable or type declaration shadows another variable, parameter, type, or class member (in C++), or whenever a - built-in function is shadowed. Note that in C++, the compiler + built-in function is shadowed. Note that in C++, the compiler warns if a local variable shadows an explicit typedef, but not if it shadows a struct/class/enum. @@ -4134,7 +4145,7 @@ present. For C++, also warn for confusing overload resolution for user-defined conversions; and conversions that never use a type conversion operator: conversions to `void', the same type, a base - class or a reference to them. Warnings about conversions between + class or a reference to them. Warnings about conversions between signed and unsigned integers are disabled by default in C++ unless `-Wsign-conversion' is explicitly enabled. @@ -4180,7 +4191,7 @@ present. `-Wsign-conversion' Warn for implicit conversions that may change the sign of an integer value, like assigning a signed integer expression to an - unsigned integer variable. An explicit cast silences the warning. + unsigned integer variable. An explicit cast silences the warning. In C, this option is enabled also by `-Wconversion'. `-Wsizeof-pointer-memaccess' @@ -4238,7 +4249,7 @@ present. `-Wold-style-declaration (C and Objective-C only)' Warn for obsolescent usages, according to the C Standard, in a - declaration. For example, warn if storage-class specifiers like + declaration. For example, warn if storage-class specifiers like `static' are not the first things in a declaration. This warning is also enabled by `-Wextra'. @@ -4444,7 +4455,7 @@ present. `-Wno-int-to-pointer-cast' Suppress warnings from casts to pointer type of an integer of a - different size. In C++, casting to a pointer type of smaller size + different size. In C++, casting to a pointer type of smaller size is an error. `Wint-to-pointer-cast' is enabled by default. `-Wno-pointer-to-int-cast (C and Objective-C only)' @@ -5023,11 +5034,11 @@ program or GCC: `-fdisable-KIND-PASS=RANGE-LIST' This is a set of options that are used to explicitly disable/enable optimization passes. These options are intended for use for - debugging GCC. Compiler users should use regular options for + debugging GCC. Compiler users should use regular options for enabling/disabling passes instead. `-fdisable-ipa-PASS' - Disable IPA pass PASS. PASS is the pass name. If the same + Disable IPA pass PASS. PASS is the pass name. If the same pass is statically invoked in the compiler multiple times, the pass name should be appended with a sequential number starting from 1. @@ -5094,7 +5105,7 @@ program or GCC: by LETTERS. This is used for debugging the RTL-based passes of the compiler. The file names for most of the dumps are made by appending a pass number and a word to the DUMPNAME, and the files - are created in the directory of the output file. In case of + are created in the directory of the output file. In case of `=FILENAME' option, the dump is output on the given file instead of the pass numbered dump files. Note that the pass number is computed statically as passes get registered into the pass manager. @@ -5396,7 +5407,7 @@ program or GCC: Control the dumping at various stages of processing the intermediate language tree to a file. The file name is generated by appending a switch-specific suffix to the source file name, and - the file is created in the same directory as the output file. In + the file is created in the same directory as the output file. In case of `=FILENAME' option, the dump is output on the given file instead of the auto named dump files. If the `-OPTIONS' form is used, OPTIONS is a list of `-' separated options which control the @@ -5618,7 +5629,7 @@ program or GCC: source file name. `vrp' - Dump each function after Value Range Propagation (VRP). The + Dump each function after Value Range Propagation (VRP). The file name is made by appending `.vrp' to the source file name. `all' @@ -5628,7 +5639,7 @@ program or GCC: `-fopt-info' `-fopt-info-OPTIONS' `-fopt-info-OPTIONS=FILENAME' - Controls optimization dumps from various optimization passes. If + Controls optimization dumps from various optimization passes. If the `-OPTIONS' form is used, OPTIONS is a list of `-' separated options to select the dump details and optimizations. If OPTIONS is not specified, it defaults to `all' for details and `optall' @@ -5640,10 +5651,10 @@ program or GCC: The options can be divided into two groups, 1) options describing the verbosity of the dump, and 2) options describing which - optimizations should be included. The options from both the groups - can be freely mixed as they are non-overlapping. However, in case + optimizations should be included. The options from both the groups + can be freely mixed as they are non-overlapping. However, in case of any conflicts, the latter options override the earlier options - on the command line. Though multiple -fopt-info options are + on the command line. Though multiple -fopt-info options are accepted, only one of them can have `=filename'. If other filenames are provided then all but the first one are ignored. @@ -5651,12 +5662,12 @@ program or GCC: `optimized' Print information when an optimization is successfully - applied. It is up to a pass to decide which information is - relevant. For example, the vectorizer passes print the source + applied. It is up to a pass to decide which information is + relevant. For example, the vectorizer passes print the source location of loops which got successfully vectorized. `missed' - Print information about missed optimizations. Individual + Print information about missed optimizations. Individual passes control which information to include in the output. For example, @@ -5670,7 +5681,7 @@ program or GCC: transformations, more detailed messages about decisions etc. `all' - Print detailed optimization information. This includes + Print detailed optimization information. This includes OPTIMIZED, MISSED, and NOTE. The second set of options describes a group of optimizations and @@ -5717,7 +5728,7 @@ program or GCC: gcc -fopt-info-vec-missed=vec.miss -fopt-info-loop-optimized=loop.opt Here the two output filenames `vec.miss' and `loop.opt' are in - conflict since only one output file is allowed. In this case, only + conflict since only one output file is allowed. In this case, only the first option takes effect and the subsequent options are ignored. Thus only the `vec.miss' is produced which cotaints dumps from the vectorizer about missed opportunities. @@ -5725,12 +5736,12 @@ program or GCC: `-ftree-vectorizer-verbose=N' This option is deprecated and is implemented in terms of `-fopt-info'. Please use `-fopt-info-KIND' form instead, where - KIND is one of the valid opt-info options. It prints additional + KIND is one of the valid opt-info options. It prints additional optimization information. For N=0 no diagnostic information is reported. If N=1 the vectorizer reports each loop that got vectorized, and the total number of loops that got vectorized. If N=2 the vectorizer reports locations which could not be vectorized - and the reasons for those. For any higher verbosity levels all the + and the reasons for those. For any higher verbosity levels all the analysis and transformation information from the vectorizer is reported. @@ -6854,9 +6865,9 @@ optimizations to be performed is desired. `-fipa-profile' Perform interprocedural profile propagation. The functions called - only from cold functions are marked as cold. Also functions + only from cold functions are marked as cold. Also functions executed once (such as `cold', `noreturn', static constructors or - destructors) are identified. Cold functions and loop less parts of + destructors) are identified. Cold functions and loop less parts of functions executed once are then optimized for size. Enabled by default at `-O' and higher. @@ -6879,7 +6890,7 @@ optimizations to be performed is desired. `-O3'. `-ftree-sink' - Perform forward store motion on trees. This flag is enabled by + Perform forward store motion on trees. This flag is enabled by default at `-O' and higher. `-ftree-bit-ccp' @@ -6920,7 +6931,7 @@ optimizations to be performed is desired. Perform a variety of simple scalar cleanups (constant/copy propagation, redundancy elimination, range propagation and expression simplification) based on a dominator tree traversal. - This also performs jump threading (to reduce jumps to jumps). This + This also performs jump threading (to reduce jumps to jumps). This flag is enabled by default at `-O' and higher. `-ftree-dse' @@ -7182,11 +7193,11 @@ optimizations to be performed is desired. is enabled by default at `-O' and higher. `-ftree-vectorize' - Perform loop vectorization on trees. This flag is enabled by + Perform loop vectorization on trees. This flag is enabled by default at `-O3'. `-ftree-slp-vectorize' - Perform basic block vectorization on trees. This flag is enabled + Perform basic block vectorization on trees. This flag is enabled by default at `-O3' and when `-ftree-vectorize' is enabled. `-ftree-vect-loop-version' @@ -7709,7 +7720,7 @@ optimizations to be performed is desired. available in gold or in GNU ld 2.21 or newer. This option enables the extraction of object files with GIMPLE - bytecode out of library archives. This improves the quality of + bytecode out of library archives. This improves the quality of optimization by exposing more code to the link-time optimizer. This information specifies what symbols can be accessed externally (by non-LTO object or during dynamic linking). Resulting code @@ -7768,9 +7779,9 @@ optimizations to be performed is desired. `-fprofile-correction' Profiles collected using an instrumented binary for multi-threaded - programs may be inconsistent due to missed counter updates. When + programs may be inconsistent due to missed counter updates. When this option is specified, GCC uses heuristics to correct or smooth - out such inconsistencies. By default, GCC emits an error message + out such inconsistencies. By default, GCC emits an error message when an inconsistent profile is detected. `-fprofile-dir=PATH' @@ -7864,7 +7875,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option besides `-Ofast' since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for - math functions. It may, however, yield faster code for programs + math functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. `-fno-math-errno' @@ -7876,7 +7887,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math - functions. It may, however, yield faster code for programs that do + functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. The default is `-fmath-errno'. @@ -7895,7 +7906,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math - functions. It may, however, yield faster code for programs that do + functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. Enables `-fno-signed-zeros', `-fno-trapping-math', `-fassociative-math' and `-freciprocal-math'. @@ -7934,7 +7945,7 @@ correctness. All must be specifically enabled. This option is not turned on by any `-O' option since it can result in incorrect output for programs that depend on an exact implementation of IEEE or ISO rules/specifications for math - functions. It may, however, yield faster code for programs that do + functions. It may, however, yield faster code for programs that do not require the guarantees of these specifications. The default is `-fno-finite-math-only'. @@ -8204,7 +8215,7 @@ includes experimental options that may produce broken code. `predictable-branch-outcome' When branch is predicted to be taken with probability lower than this threshold (in percent), then it is considered well - predictable. The default is 10. + predictable. The default is 10. `max-crossjump-edges' The maximum number of incoming edges to consider for @@ -8561,7 +8572,7 @@ includes experimental options that may produce broken code. `hot-bb-count-ws-permille' A basic block profile count is considered hot if it - contributes to the given permillage (i.e. 0...1000) of the + contributes to the given permillage (i.e. 0...1000) of the entire profiled execution. `hot-bb-frequency-fraction' @@ -9017,7 +9028,7 @@ includes experimental options that may produce broken code. `tree-reassoc-width' Set the maximum number of instructions executed in parallel in - reassociated tree. This parameter overrides target dependent + reassociated tree. This parameter overrides target dependent heuristics used by default if has non zero value. `sched-pressure-algorithm' @@ -9575,9 +9586,9 @@ cause the preprocessor output to be unsuitable for actual compilation. When used without `-E', this option has no effect. `-ftrack-macro-expansion[=LEVEL]' - Track locations of tokens across macro expansions. This allows the + Track locations of tokens across macro expansions. This allows the compiler to emit diagnostic about the current macro expansion stack - when a compilation error occurs in a macro expansion. Using this + when a compilation error occurs in a macro expansion. Using this option makes the preprocessor and the compiler consume more memory. The LEVEL parameter can be used to choose the level of precision of token location tracking thus decreasing the memory @@ -9888,8 +9899,8 @@ doing a link step. `-rdynamic' Pass the flag `-export-dynamic' to the ELF linker, on targets that - support it. This instructs the linker to add all symbols, not only - used ones, to the dynamic symbol table. This option is needed for + support it. This instructs the linker to add all symbols, not only + used ones, to the dynamic symbol table. This option is needed for some uses of `dlopen' or to allow obtaining backtraces from within a program. @@ -10017,7 +10028,7 @@ doing a link step. library modules to define it. You can use `-u' multiple times with different symbols to force loading of additional library modules. - ---------- Footnotes ---------- + ---------- Footnotes ---------- (1) On some systems, `gcc -shared' needs to build supplementary stub code for constructors to work. On multi-libbed systems, `gcc -shared' @@ -10412,7 +10423,7 @@ or combine them with constant text in a single argument. `%T' Current argument is the name of a linker script. Search for that - file in the current list of directories to scan for libraries. If + file in the current list of directories to scan for libraries. If the file is located insert a `--script' option into the command line followed by the full path name found. If the file is not found then generate an error message. Note: the current working @@ -10974,7 +10985,7 @@ These `-m' options are defined for Adapteva Epiphany: `int' This is the mode used to perform integer calculations in the - FPU, e.g. integer multiply, or integer + FPU, e.g. integer multiply, or integer multiply-and-accumulate. The default is `-mfp-mode=caller' @@ -11085,45 +11096,41 @@ architectures: versions of the compiler prior to 2.8. This option is now deprecated. -`-mcpu=NAME' - This specifies the name of the target ARM processor. GCC uses +`-march=NAME' + This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of instructions it can emit when - generating assembly code. Permissible names are: `arm2', `arm250', - `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', - `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', - `arm700i', `arm710', `arm710c', `arm7100', `arm720', `arm7500', - `arm7500fe', `arm7tdmi', `arm7tdmi-s', `arm710t', `arm720t', - `arm740t', `strongarm', `strongarm110', `strongarm1100', - `strongarm1110', `arm8', `arm810', `arm9', `arm9e', `arm920', - `arm920t', `arm922t', `arm946e-s', `arm966e-s', `arm968e-s', - `arm926ej-s', `arm940t', `arm9tdmi', `arm10tdmi', `arm1020t', - `arm1026ej-s', `arm10e', `arm1020e', `arm1022e', `arm1136j-s', - `arm1136jf-s', `mpcore', `mpcorenovfp', `arm1156t2-s', - `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', `cortex-a5', - `cortex-a7', `cortex-a8', `cortex-a9', `cortex-a15', `cortex-r4', - `cortex-r4f', `cortex-r5', `cortex-m4', `cortex-m3', `cortex-m1', - `cortex-m0', `cortex-m0plus', `marvell-pj4', `xscale', `iwmmxt', - `iwmmxt2', `ep9312', `fa526', `fa626', `fa606te', `fa626te', - `fmp626', `fa726te'. - - `-mcpu=generic-ARCH' is also permissible, and is equivalent to - `-march=ARCH -mtune=generic-ARCH'. See `-mtune' for more - information. + generating assembly code. This option can be used in conjunction + with or instead of the `-mcpu=' option. Permissible names are: + `armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5', + `armv5t', `armv5e', `armv5te', `armv6', `armv6j', `armv6t2', + `armv6z', `armv6zk', `armv6-m', `armv7', `armv7-a', `armv7-r', + `armv7-m', `armv7e-m' `armv8-a', `iwmmxt', `iwmmxt2', `ep9312'. - `-mcpu=native' causes the compiler to auto-detect the CPU of the - build computer. At present, this feature is only supported on - Linux, and not all architectures are recognized. If the + `-march=native' causes the compiler to auto-detect the architecture + of the build computer. At present, this feature is only supported + on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. `-mtune=NAME' - This option is very similar to the `-mcpu=' option, except that - instead of specifying the actual target processor type, and hence - restricting which instructions can be used, it specifies that GCC - should tune the performance of the code as if the target were of - the type specified in this option, but still choosing the - instructions it generates based on the CPU specified by a `-mcpu=' - option. For some ARM implementations better performance can be - obtained by using this option. + This option specifies the name of the target ARM processor for + which GCC should tune the performance of the code. For some ARM + implementations better performance can be obtained by using this + option. Permissible names are: `arm2', `arm250', `arm3', `arm6', + `arm60', `arm600', `arm610', `arm620', `arm7', `arm7m', `arm7d', + `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', `arm700i', + `arm710', `arm710c', `arm7100', `arm720', `arm7500', `arm7500fe', + `arm7tdmi', `arm7tdmi-s', `arm710t', `arm720t', `arm740t', + `strongarm', `strongarm110', `strongarm1100', `strongarm1110', + `arm8', `arm810', `arm9', `arm9e', `arm920', `arm920t', `arm922t', + `arm946e-s', `arm966e-s', `arm968e-s', `arm926ej-s', `arm940t', + `arm9tdmi', `arm10tdmi', `arm1020t', `arm1026ej-s', `arm10e', + `arm1020e', `arm1022e', `arm1136j-s', `arm1136jf-s', `mpcore', + `mpcorenovfp', `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', + `arm1176jzf-s', `cortex-a5', `cortex-a7', `cortex-a8', `cortex-a9', + `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-r5', `cortex-m4', + `cortex-m3', `cortex-m1', `cortex-m0', `cortex-m0plus', + `marvell-pj4', `xscale', `iwmmxt', `iwmmxt2', `ep9312', `fa526', + `fa626', `fa606te', `fa626te', `fmp626', `fa726te'. `-mtune=generic-ARCH' specifies that GCC should tune the performance for a blend of processors within architecture ARCH. @@ -11138,19 +11145,24 @@ architectures: Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -`-march=NAME' - This specifies the name of the target ARM architecture. GCC uses - this name to determine what kind of instructions it can emit when - generating assembly code. This option can be used in conjunction - with or instead of the `-mcpu=' option. Permissible names are: - `armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5', - `armv5t', `armv5e', `armv5te', `armv6', `armv6j', `armv6t2', - `armv6z', `armv6zk', `armv6-m', `armv7', `armv7-a', `armv7-r', - `armv7-m', `armv8-a', `iwmmxt', `iwmmxt2', `ep9312'. +`-mcpu=NAME' + This specifies the name of the target ARM processor. GCC uses + this name to derive the name of the target ARM architecture (as if + specified by `-march') and the ARM processor type for which to + tune for performance (as if specified by `-mtune'). Where this + option is used in conjunction with `-march' or `-mtune', those + options take precedence over the appropriate part of this option. - `-march=native' causes the compiler to auto-detect the architecture - of the build computer. At present, this feature is only supported - on Linux, and not all architectures are recognized. If the + Permissible names for this option are the same as those for + `-mtune'. + + `-mcpu=generic-ARCH' is also permissible, and is equivalent to + `-march=ARCH -mtune=generic-ARCH'. See `-mtune' for more + information. + + `-mcpu=native' causes the compiler to auto-detect the CPU of the + build computer. At present, this feature is only supported on + Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. `-mfpu=NAME' @@ -11229,8 +11241,11 @@ architectures: appropriate value before execution begins. `-mpic-register=REG' - Specify the register to be used for PIC addressing. The default - is R10 unless stack-checking is enabled, when R9 is used. + Specify the register to be used for PIC addressing. For standard + PIC base case, the default will be any suitable register + determined by compiler. For single PIC base case, the default is + `R9' if target is EABI based or stack-checking is enabled, + otherwise the default is `R10'. `-mpoke-function-name' Write the name of each function into the text section, directly @@ -11366,7 +11381,7 @@ These options are defined for AVR implementations: `attiny87', `attiny88', `at86rf401'. `avr3' - "Classic" devices with 16 KiB up to 64 KiB of program memory. + "Classic" devices with 16 KiB up to 64 KiB of program memory. MCU = `at43usb355', `at76c711'. `avr31' @@ -11390,33 +11405,29 @@ These options are defined for AVR implementations: `avr5' "Enhanced" devices with 16 KiB up to 64 KiB of program memory. MCU = `ata5790', `ata5790n', `ata5795', `atmega16', - `atmega16a', `atmega16hva', `atmega16hva', `atmega16hva2', - `atmega16hva2', `atmega16hvb', `atmega16hvb', - `atmega16hvbrevb', `atmega16m1', `atmega16m1', `atmega16u4', - `atmega16u4', `atmega161', `atmega162', `atmega163', - `atmega164a', `atmega164p', `atmega164pa', `atmega165', - `atmega165a', `atmega165p', `atmega165pa', `atmega168', - `atmega168a', `atmega168p', `atmega168pa', `atmega169', - `atmega169a', `atmega169p', `atmega169pa', `atmega26hvg', - `atmega32', `atmega32a', `atmega32a', `atmega32c1', - `atmega32c1', `atmega32hvb', `atmega32hvb', - `atmega32hvbrevb', `atmega32m1', `atmega32m1', `atmega32u4', - `atmega32u4', `atmega32u6', `atmega32u6', `atmega323', - `atmega324a', `atmega324p', `atmega324pa', `atmega325', - `atmega325a', `atmega325p', `atmega3250', `atmega3250a', - `atmega3250p', `atmega3250pa', `atmega328', `atmega328p', - `atmega329', `atmega329a', `atmega329p', `atmega329pa', - `atmega3290', `atmega3290a', `atmega3290p', `atmega3290pa', - `atmega406', `atmega48hvf', `atmega64', `atmega64a', - `atmega64c1', `atmega64c1', `atmega64hve', `atmega64m1', - `atmega64m1', `atmega64rfa2', `atmega64rfr2', `atmega640', - `atmega644', `atmega644a', `atmega644p', `atmega644pa', - `atmega645', `atmega645a', `atmega645p', `atmega6450', - `atmega6450a', `atmega6450p', `atmega649', `atmega649a', - `atmega649p', `atmega6490', `atmega6490a', `atmega6490p', - `at90can32', `at90can64', `at90pwm161', `at90pwm216', - `at90pwm316', `at90scr100', `at90usb646', `at90usb647', - `at94k', `m3000'. + `atmega16a', `atmega16hva', `atmega16hva2', `atmega16hvb', + `atmega16hvbrevb', `atmega16m1', `atmega16u4', `atmega161', + `atmega162', `atmega163', `atmega164a', `atmega164p', + `atmega164pa', `atmega165', `atmega165a', `atmega165p', + `atmega165pa', `atmega168', `atmega168a', `atmega168p', + `atmega168pa', `atmega169', `atmega169a', `atmega169p', + `atmega169pa', `atmega26hvg', `atmega32', `atmega32a', + `atmega32c1', `atmega32hvb', `atmega32hvbrevb', `atmega32m1', + `atmega32u4', `atmega32u6', `atmega323', `atmega324a', + `atmega324p', `atmega324pa', `atmega325', `atmega325a', + `atmega325p', `atmega3250', `atmega3250a', `atmega3250p', + `atmega3250pa', `atmega328', `atmega328p', `atmega329', + `atmega329a', `atmega329p', `atmega329pa', `atmega3290', + `atmega3290a', `atmega3290p', `atmega3290pa', `atmega406', + `atmega48hvf', `atmega64', `atmega64a', `atmega64c1', + `atmega64hve', `atmega64m1', `atmega64rfa2', `atmega64rfr2', + `atmega640', `atmega644', `atmega644a', `atmega644p', + `atmega644pa', `atmega645', `atmega645a', `atmega645p', + `atmega6450', `atmega6450a', `atmega6450p', `atmega649', + `atmega649a', `atmega649p', `atmega6490', `atmega6490a', + `atmega6490p', `at90can32', `at90can64', `at90pwm161', + `at90pwm216', `at90pwm316', `at90scr100', `at90usb646', + `at90usb647', `at94k', `m3000'. `avr51' "Enhanced" devices with 128 KiB of program memory. @@ -11488,7 +11499,7 @@ These options are defined for AVR implementations: `-mbranch-cost=COST' Set the branch costs for conditional branch instructions to COST. - Reasonable values for COST are small, non-negative integers. The + Reasonable values for COST are small, non-negative integers. The default branch cost is 0. `-mcall-prologues' @@ -11512,7 +11523,7 @@ These options are defined for AVR implementations: linker is called. Jump relaxing is performed by the linker because jump offsets are - not known before code is located. Therefore, the assembler code + not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code. @@ -11581,12 +11592,12 @@ the compiler and are subject to some limitations: prologue/epilogue. * For indirect calls to functions and computed goto, the linker - generates _stubs_. Stubs are jump pads sometimes also called - _trampolines_. Thus, the indirect call/jump jumps to such a stub. + generates _stubs_. Stubs are jump pads sometimes also called + _trampolines_. Thus, the indirect call/jump jumps to such a stub. The stub contains a direct jump to the desired address. * Linker relaxation must be turned on so that the linker will - generate the stubs correctly an all situaltion. See the compiler + generate the stubs correctly an all situaltion. See the compiler option `-mrelax' and the linler option `--relax'. There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message. @@ -11598,7 +11609,7 @@ the compiler and are subject to some limitations: points to. * The startup code from libgcc never sets `EIND'. Notice that - startup code is a blend of code from libgcc and AVR-LibC. For the + startup code is a blend of code from libgcc and AVR-LibC. For the impact of AVR-LibC on `EIND', see the AVR-LibC user manual (http://nongnu.org/avr-libc/user-manual/). @@ -11639,7 +11650,7 @@ the compiler and are subject to some limitations: - If prologue-save function is used, see `-mcall-prologues' command-line option. - - Switch/case dispatch tables. If you do not want such dispatch + - Switch/case dispatch tables. If you do not want such dispatch tables you can specify the `-fno-jump-tables' command-line option. @@ -11771,7 +11782,7 @@ Spaces:: and *note AVR Built-in Functions::. also means that the program counter (PC) is 3 bytes wide. `__AVR_2_BYTE_PC__' - The program counter (PC) is 2 bytes wide. This is the case for + The program counter (PC) is 2 bytes wide. This is the case for devices with up to 128 KiB of program memory. `__AVR_HAVE_8BIT_SP__' @@ -11869,7 +11880,7 @@ File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, `-mspecld-anomaly' When enabled, the compiler ensures that the generated code does not - contain speculative loads after jump instructions. If this option + contain speculative loads after jump instructions. If this option is used, `__WORKAROUND_SPECULATIVE_LOADS' is defined. `-mno-specld-anomaly' @@ -11950,7 +11961,7 @@ File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, handle function calls via function pointers. `-mfast-fp' - Link with the fast floating-point library. This library relaxes + Link with the fast floating-point library. This library relaxes some of the IEEE floating-point standard's rules for checking inputs against Not-a-Number (NAN), in the interest of performance. @@ -11975,14 +11986,14 @@ File: gcc.info, Node: Blackfin Options, Next: C6X Options, Prev: AVR Options, `-mcorea' Build a standalone application for Core A of BF561 when using the - one-application-per-core programming model. Proper start files and + one-application-per-core programming model. Proper start files and link scripts are used to support Core A, and the macro `__BFIN_COREA' is defined. This option can only be used in conjunction with `-mmulticore'. `-mcoreb' Build a standalone application for Core B of BF561 when using the - one-application-per-core programming model. Proper start files and + one-application-per-core programming model. Proper start files and link scripts are used to support Core B, and the macro `__BFIN_COREB' is defined. When this option is used, `coreb_main' should be used instead of `main'. This option can only be used in @@ -12154,7 +12165,7 @@ File: gcc.info, Node: CR16 Options, Next: Darwin Options, Prev: CRIS Options, These options are defined specifically for the CR16 ports. `-mmac' - Enable the use of multiply-accumulate instructions. Disabled by + Enable the use of multiply-accumulate instructions. Disabled by default. `-mcr16cplus' @@ -12393,7 +12404,7 @@ These `-m' options are defined for the DEC Alpha implementations: operations. Unless they are replaced by routines that emulate the floating-point operations, or compiled in such a way as to call such emulations routines, these routines issue floating-point - operations. If you are compiling for an Alpha without + operations. If you are compiling for an Alpha without floating-point operations, you must ensure that the library is built so as not to call them. @@ -13289,9 +13300,15 @@ computers: SSSE3, SSE4.1, SSE4.2, AVX, AES, PCLMUL, FSGSBASE, RDRND and F16C instruction set support. + `core-avx2' + Intel Core CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, + SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AES, PCLMUL, + FSGSBASE, RDRND, FMA, BMI, BMI2 and F16C instruction set + support. + `atom' - Intel Atom CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 - and SSSE3 instruction set support. + Intel Atom CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, + SSE3 and SSSE3 instruction set support. `k6' AMD K6 CPU with MMX instruction set support. @@ -13369,7 +13386,7 @@ computers: `winchip2' IDT WinChip 2 CPU, dealt in same way as i486 with additional - MMX and 3DNow! instruction set support. + MMX and 3DNow! instruction set support. `c3' VIA C3 CPU with MMX and 3DNow! instruction set support. (No @@ -13558,7 +13575,7 @@ computers: `-mlong-double-80' These switches control the size of `long double' type. A size of 64 bits makes the `long double' type equivalent to the `double' - type. This is the default for Bionic C library. + type. This is the default for Bionic C library. *Warning:* if you override the default value for your target ABI, this changes the size of structures and arrays containing `long @@ -13763,7 +13780,7 @@ computers: These switches enable or disable the use of instructions in the MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, F16C, FMA, SSE4A, FMA4, XOP, LWP, ABM, BMI, BMI2, - LZCNT, RTM or 3DNow! extended instruction sets. These extensions + LZCNT, RTM or 3DNow! extended instruction sets. These extensions are also available as built-in functions: see *note X86 Built-in Functions::, for details of the functions enabled and disabled by these switches. @@ -14108,7 +14125,7 @@ These additional options are available for Microsoft Windows targets: specifies that the `dllimport' attribute should be ignored. `-mthread' - This option is available for MinGW targets. It specifies that + This option is available for MinGW targets. It specifies that MinGW-specific thread support is to be used. `-municode' @@ -14128,7 +14145,7 @@ These additional options are available for Microsoft Windows targets: the linker to set the PE header subsystem type appropriately. `-fno-set-stack-executable' - This option is available for MinGW targets. It specifies that the + This option is available for MinGW targets. It specifies that the executable flag for the stack used by nested functions isn't set. This is necessary for binaries running in kernel mode of Microsoft Windows, as there the User32 API, which is used to set executable @@ -15080,7 +15097,7 @@ File: gcc.info, Node: MicroBlaze Options, Next: MIPS Options, Prev: MeP Optio instead. `-mcpu=CPU-TYPE' - Use features of, and schedule code for, the given CPU. Supported + Use features of, and schedule code for, the given CPU. Supported values are in the format `vX.YY.Z', where X is a major version, YY is the minor version, and Z is compatibility code. Example values are `v3.00.a', `v4.00.b', `v5.00.a', `v5.00.b', `v5.00.b', @@ -15132,20 +15149,20 @@ File: gcc.info, Node: MicroBlaze Options, Next: MIPS Options, Prev: MeP Optio `xmdstub' for use with Xilinx Microprocessor Debugger (XMD) based - software intrusive debug agent called xmdstub. This uses + software intrusive debug agent called xmdstub. This uses startup file `crt1.o' and sets the start address of the program to 0x800. `bootstrap' for applications that are loaded using a bootloader. This model uses startup file `crt2.o' which does not contain a - processor reset vector handler. This is suitable for + processor reset vector handler. This is suitable for transferring control on a processor reset to the bootloader rather than the application. `novectors' for applications that do not require any of the MicroBlaze - vectors. This option may be useful for applications running + vectors. This option may be useful for applications running within a monitoring application. This model uses `crt3.o' as a startup file. @@ -16275,6 +16292,8 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: -mpopcntb -mpopcntd -mpowerpc64 -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float -msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx + -mcrypto -mdirect-move -mpower8-fusion -mpower8-vector + -mquad-memory -mquad-memory-atomic The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce @@ -16318,6 +16337,36 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mabi=altivec' to adjust the current ABI with AltiVec ABI enhancements. + When `-maltivec' is used, rather than `-maltivec=le' or + `-maltivec=be', the element order for Altivec intrinsics such as + `vec_splat', `vec_extract', and `vec_insert' will match array + element order corresponding to the endianness of the target. That + is, element zero identifies the leftmost element in a vector + register when targeting a big-endian platform, and identifies the + rightmost element in a vector register when targeting a + little-endian platform. + +`-maltivec=be' + Generate Altivec instructions using big-endian element order, + regardless of whether the target is big- or little-endian. This is + the default when targeting a big-endian platform. + + The element order is used to interpret element numbers in Altivec + intrinsics such as `vec_splat', `vec_extract', and `vec_insert'. + By default, these will match array element order corresponding to + the endianness for the target. + +`-maltivec=le' + Generate Altivec instructions using little-endian element order, + regardless of whether the target is big- or little-endian. This is + the default when targeting a little-endian platform. This option + is currently ignored when targeting a big-endian platform. + + The element order is used to interpret element numbers in Altivec + intrinsics such as `vec_splat', `vec_extract', and `vec_insert'. + By default, these will match array element order corresponding to + the endianness for the target. + `-mvrsave' `-mno-vrsave' Generate VRSAVE instructions when generating AltiVec code. @@ -16368,6 +16417,43 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. +`-mcrypto' +`-mno-crypto' + Enable the use (disable) of the built-in functions that allow + direct access to the cryptographic instructions that were added in + version 2.07 of the PowerPC ISA. + +`-mdirect-move' +`-mno-direct-move' + Generate code that uses (does not use) the instructions to move + data between the general purpose registers and the vector/scalar + (VSX) registers that were added in version 2.07 of the PowerPC ISA. + +`-mpower8-fusion' +`-mno-power8-fusion' + Generate code that keeps (does not keeps) some integer operations + adjacent so that the instructions can be fused together on power8 + and later processors. + +`-mpower8-vector' +`-mno-power8-vector' + Generate code that uses (does not use) the vector and scalar + instructions that were added in version 2.07 of the PowerPC ISA. + Also enable the use of built-in functions that allow more direct + access to the vector instructions. + +`-mquad-memory' +`-mno-quad-memory' + Generate code that uses (does not use) the non-atomic quad word + memory instructions. The `-mquad-memory' option requires use of + 64-bit mode. + +`-mquad-memory-atomic' +`-mno-quad-memory-atomic' + Generate code that uses (does not use) the atomic quad word memory + instructions. The `-mquad-memory-atomic' option requires use of + 64-bit mode. + `-mfloat-gprs=YES/SINGLE/DOUBLE/NO' `-mfloat-gprs' This switch enables or disables the generation of floating-point @@ -16535,7 +16621,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mavoid-indexed-addresses' `-mno-avoid-indexed-addresses' Generate code that tries to avoid (not avoid) the use of indexed - load or store instructions. These instructions can incur a + load or store instructions. These instructions can incur a performance penalty on Power6 processors in certain situations, such as when stepping through large arrays that cross a 16M boundary. This option is enabled by default when targeting Power6 @@ -16654,7 +16740,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `store_to_load' Any dependence from store to load is costly. - NUMBER + NUMBER Any dependence for which the latency is greater than or equal to NUMBER is costly. @@ -16676,7 +16762,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: insn to a new group, according to the estimated processor grouping. - NUMBER + NUMBER Insert NOPs to force costly dependent insns into separate groups. Insert NUMBER NOPs to force an insn to a new group. @@ -16724,7 +16810,7 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: `-mabi=ABI-TYPE' Extend the current ABI with a particular extension, or remove such extension. Valid values are ALTIVEC, NO-ALTIVEC, SPE, NO-SPE, - IBMLONGDOUBLE, IEEELONGDOUBLE. + IBMLONGDOUBLE, IEEELONGDOUBLE, ELFV1, ELFV2. `-mabi=spe' Extend the current ABI with SPE ABI extensions. This does not @@ -16742,6 +16828,18 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option. +`-mabi=elfv1' + Change the current ABI to use the ELFv1 ABI. This is the default + ABI for big-endian PowerPC 64-bit Linux. Overriding the default + ABI requires special system support and is likely to fail in + spectacular ways. + +`-mabi=elfv2' + Change the current ABI to use the ELFv2 ABI. This is the default + ABI for little-endian PowerPC 64-bit Linux. Overriding the + default ABI requires special system support and is likely to fail + in spectacular ways. + `-mprototype' `-mno-prototype' On System V.4 and embedded PowerPC systems assume that all calls to @@ -16992,6 +17090,22 @@ These `-m' options are defined for the IBM RS/6000 and PowerPC: the call through the pointer. The `-mno-save-toc-indirect' option is the default. +`-mcompat-align-parm' +`-mno-compat-align-parm' + Generate (do not generate) code to pass structure parameters with a + maximum alignment of 64 bits, for compatibility with older versions + of GCC. + + Older versions of GCC (prior to 4.9.0) incorrectly did not align a + structure parameter on a 128-bit boundary when that structure + contained a member requiring 128-bit alignment. This is corrected + in more recent versions of GCC. This option may be used to + generate code that is compatible with functions compiled with + older versions of GCC. + + In this version of the compiler, the `-mcompat-align-parm' is the + default, except when using the Linux ELFv2 ABI. +  File: gcc.info, Node: RX Options, Next: S/390 and zSeries Options, Prev: RS/6000 and PowerPC Options, Up: Submodel Options @@ -17024,7 +17138,7 @@ These command-line options are defined for RX targets: `-mcpu=NAME' Selects the type of RX CPU to be targeted. Currently three types are supported, the generic RX600 and RX200 series hardware and the - specific RX610 CPU. The default is RX600. + specific RX610 CPU. The default is RX600. The only difference between RX600 and RX610 is that the RX610 does not support the `MVTIPL' instruction. @@ -17180,7 +17294,7 @@ architecture. `-mlong-double-128' These switches control the size of `long double' type. A size of 64 bits makes the `long double' type equivalent to the `double' - type. This is the default. + type. This is the default. `-mbackchain' `-mno-backchain' @@ -17321,6 +17435,20 @@ architecture. value given by STACK-SIZE. The STACK-GUARD option can only be used in conjunction with STACK-SIZE. +`-mhotpatch[=HALFWORDS]' +`-mno-hotpatch' + If the hotpatch option is enabled, a "hot-patching" function + prologue is generated for all functions in the compilation unit. + The funtion label is prepended with the given number of two-byte + Nop instructions (HALFWORDS, maximum 1000000) or 12 Nop + instructions if no argument is present. Functions with a + hot-patching prologue are never inlined automatically, and a + hot-patching prologue is never generated for functions functions + that are explicitly inline. + + This option can be overridden for individual functions with the + `hotpatch' attribute. +  File: gcc.info, Node: Score Options, Next: SH Options, Prev: S/390 and zSeries Options, Up: Submodel Options @@ -17342,7 +17470,7 @@ These options are defined for Score implementations: Enable generation of unaligned load and store instructions. `-mmac' - Enable the use of multiply-accumulate instructions. Disabled by + Enable the use of multiply-accumulate instructions. Disabled by default. `-mscore5' @@ -17669,7 +17797,7 @@ These `-m' options are defined for the SH implementations: Calls a library function that performs the operation in double precision floating point. Division by zero causes a floating-point exception. This is the default for SHcompact - with FPU. Specifying this for targets that do not have a + with FPU. Specifying this for targets that do not have a double precision FPU will default to `call-div1'. `call-table' @@ -17853,7 +17981,9 @@ These `-m' options are supported on the SPARC: `-mapp-regs' Specify `-mapp-regs' to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. - This is the default. + Like the global register 1, each global register 2 through 4 is + then treated as an allocable register that is clobbered by + function calls. This is the default. To be fully SVR4 ABI-compliant at the cost of some performance loss, specify `-mno-app-regs'. You should compile libraries and @@ -17923,6 +18053,12 @@ These `-m' options are supported on the SPARC: default because it results in a performance loss, especially for floating-point code. +`-muser-mode' +`-mno-user-mode' + Do not generate code that can only run in supervisor mode. This + is relevant only for the `casa' instruction emitted for the LEON3 + processor. The default is `-mno-user-mode'. + `-mno-faster-structs' `-mfaster-structs' With `-mfaster-structs', the compiler assumes that structures @@ -17938,9 +18074,9 @@ These `-m' options are supported on the SPARC: Set the instruction set, register set, and instruction scheduling parameters for machine type CPU_TYPE. Supported values for CPU_TYPE are `v7', `cypress', `v8', `supersparc', `hypersparc', - `leon', `sparclite', `f930', `f934', `sparclite86x', `sparclet', - `tsc701', `v9', `ultrasparc', `ultrasparc3', `niagara', - `niagara2', `niagara3', and `niagara4'. + `leon', `leon3', `sparclite', `f930', `f934', `sparclite86x', + `sparclet', `tsc701', `v9', `ultrasparc', `ultrasparc3', + `niagara', `niagara2', `niagara3' and `niagara4'. Native Solaris and GNU/Linux toolchains also support the value `native', which selects the best architecture option for the host @@ -17954,19 +18090,19 @@ These `-m' options are supported on the SPARC: Here is a list of each supported architecture and their supported implementations. - v7 + v7 cypress - v8 - supersparc, hypersparc, leon + v8 + supersparc, hypersparc, leon, leon3 - sparclite + sparclite f930, f934, sparclite86x - sparclet + sparclet tsc701 - v9 + v9 ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4 By default (unless configured otherwise), GCC generates code for @@ -18021,7 +18157,7 @@ These `-m' options are supported on the SPARC: The same values for `-mcpu=CPU_TYPE' can be used for `-mtune=CPU_TYPE', but the only useful values are those that select a particular CPU implementation. Those are `cypress', - `supersparc', `hypersparc', `leon', `f930', `f934', + `supersparc', `hypersparc', `leon', `leon3', `f930', `f934', `sparclite86x', `tsc701', `ultrasparc', `ultrasparc3', `niagara', `niagara2', `niagara3' and `niagara4'. With native Solaris and GNU/Linux toolchains, `native' can also be used. @@ -18081,6 +18217,10 @@ These `-m' options are supported on the SPARC: Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor). +`-mfix-ut699' + Enable the documented workarounds for the floating-point errata + and the data cache nullify errata of the UT699 processor. + These `-m' options are supported in addition to the above on SPARC-V9 processors in 64-bit environments: @@ -18408,7 +18548,7 @@ These `-m' options are defined for V850 implementations: is used. `-mv850es' - Specify that the target processor is the V850ES. This is an alias + Specify that the target processor is the V850ES. This is an alias for the `-mv850e1' option. `-mv850e' @@ -18460,7 +18600,7 @@ These `-m' options are defined for V850 implementations: `-mrh850-abi' `-mghs' - Enables support for the RH850 version of the V850 ABI. This is the + Enables support for the RH850 version of the V850 ABI. This is the default. With this version of the ABI the following rules apply: * Integer sized structures and unions are returned via a memory @@ -18481,7 +18621,7 @@ These `-m' options are defined for V850 implementations: `__V850_RH850_ABI__' is defined. `-mgcc-abi' - Enables support for the old GCC version of the V850 ABI. With this + Enables support for the old GCC version of the V850 ABI. With this version of the ABI the following rules apply: * Integer sized structures and unions are returned in register @@ -18561,7 +18701,7 @@ These `-m' options are defined for the VMS implementations: Default to 64-bit memory allocation routines. `-mpointer-size=SIZE' - Set the default size of pointers. Possible options for SIZE are + Set the default size of pointers. Possible options for SIZE are `32' or `short' for 32 bit pointers, `64' or `long' for 64 bit pointers, and `no' for supporting only 32 bit pointers. The later option disables `pragma pointer_size'. @@ -18799,13 +18939,13 @@ form by either removing `no-' or adding it. } The lifetime of a compiler generated temporary is well defined by - the C++ standard. When a lifetime of a temporary ends, and if the + the C++ standard. When a lifetime of a temporary ends, and if the temporary lives in memory, the optimizing compiler has the freedom to reuse its stack space with other temporaries or scoped local - variables whose live range does not overlap with it. However some + variables whose live range does not overlap with it. However some of the legacy code relies on the behavior of older compilers in which temporaries' stack space is not reused, the aggressive stack - reuse can lead to runtime errors. This option is used to control + reuse can lead to runtime errors. This option is used to control the temporary stack reuse optimization. `-ftrapv' @@ -19419,7 +19559,7 @@ Controlling the Compilation Driver `gcc': (gccint)Driver. tries looking in the usual places for the subprogram. The default value of `GCC_EXEC_PREFIX' is `PREFIX/lib/gcc/' where - PREFIX is the prefix to the installed compiler. In many cases + PREFIX is the prefix to the installed compiler. In many cases PREFIX is the value of `prefix' when you ran the `configure' script. @@ -19998,9 +20138,9 @@ File: gcc.info, Node: Arrays and pointers implementation, Next: Hints implemen determined by the ABI. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) Future versions of GCC may zero-extend, or use a target-defined + (1) Future versions of GCC may zero-extend, or use a target-defined `ptr_extend' pattern. Do not rely on sign extension.  @@ -20269,8 +20409,8 @@ File: gcc.info, Node: C++ Implementation, Next: C Extensions, Prev: C Impleme A conforming implementation of ISO C++ is required to document its choice of behavior in each of the areas that are designated "implementation defined". The following lists all such areas, along -with the section numbers from the ISO/IEC 14822:1998 and ISO/IEC -14822:2003 standards. Some areas are only implementation-defined in +with the section numbers from the ISO/IEC 14882:1998 and ISO/IEC +14882:2003 standards. Some areas are only implementation-defined in one version of the standard. Some choices depend on the externally determined ABI for the platform @@ -20650,9 +20790,9 @@ on them being always the same, inlining and cloning. If `&&foo' is used in a static variable initializer, inlining and cloning is forbidden. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) The analogous feature in Fortran is called an assigned goto, but + (1) The analogous feature in Fortran is called an assigned goto, but that name seems inappropriate in C, where one can do more than simply store label addresses in label variables. @@ -20825,7 +20965,7 @@ acting as mere forwarders for their arguments. the containing function. You should specify, for RESULT, a value returned by `__builtin_apply'. - -- Built-in Function: __builtin_va_arg_pack () + -- Built-in Function: __builtin_va_arg_pack () This built-in function represents all anonymous arguments of an inline function. It can be used only in inline functions that are always inlined, never compiled as a separate function, such as @@ -22463,7 +22603,7 @@ attributes. `thiscall' On the Intel 386, the `thiscall' attribute causes the compiler to pass the first argument (if of integral type) in the register ECX. - Subsequent and other typed arguments are passed on the stack. The + Subsequent and other typed arguments are passed on the stack. The called function pops the arguments off the stack. If the number of arguments is variable all arguments are pushed on the stack. The `thiscall' attribute is intended for C++ non-static member @@ -22613,11 +22753,11 @@ attributes. of these calls. On M16C/M32C targets, the `function_vector' attribute declares a - special page subroutine call function. Use of this attribute + special page subroutine call function. Use of this attribute reduces the code size by 2 bytes for each call generated to the - subroutine. The argument to the attribute is the vector number + subroutine. The argument to the attribute is the vector number entry from the special page vector table which contains the 16 - low-order bits of the subroutine's entry address. Each vector + low-order bits of the subroutine's entry address. Each vector table has special page number (18 to 255) that is used in `jsrs' instructions. Jump addresses of the routines are generated by adding 0x0F0000 (in case of M16C targets) or 0xFF0000 (in case of @@ -22812,7 +22952,7 @@ attributes. `l1_text' This attribute specifies a function to be placed into L1 - Instruction SRAM. The function is put into a specific section + Instruction SRAM. The function is put into a specific section named `.l1.text'. With `-mfdpic', function calls with a such function as the callee or caller uses inlined PLT. @@ -22963,6 +23103,14 @@ attributes. "hot-patching" function prologue used in Win32 API functions in Microsoft Windows XP Service Pack 2 and newer. +`hotpatch [(PROLOGUE-HALFWORDS)]' + On S/390 System z targets, you can use this function attribute to + make GCC generate a "hot-patching" function prologue. The + `hotpatch' has no effect on funtions that are explicitly inline. + If the `-mhotpatch' or `-mno-hotpatch' command-line option is used + at the same time, the `hotpatch' attribute takes precedence. If + an argument is given, the maximum allowed value is 1000000. + `naked' Use this attribute on the ARM, AVR, MCORE, RX and SPU ports to indicate that the specified function does not need @@ -23133,8 +23281,8 @@ attributes. The `OS_task' attribute can be used when there is _no guarantee_ that interrupts are disabled at that time when the function is - entered like for, e.g. task functions in a multi-threading - operating system. In that case, changing the stack pointer + entered like for, e.g. task functions in a multi-threading + operating system. In that case, changing the stack pointer register is guarded by save/clear/restore of the global interrupt enable flag. @@ -23149,7 +23297,7 @@ attributes. `pcs' The `pcs' attribute can be used to control the calling convention - used for a function on ARM. The attribute takes an argument that + used for a function on ARM. The attribute takes an argument that specifies the calling convention to use. When compiling using the AAPCS ABI (or a variant of it) then valid @@ -23259,7 +23407,7 @@ attributes. clobbered, as per the standard calling conventions. Solaris 8 is affected by this. Systems with the GNU C Library version 2.1 or higher and FreeBSD are believed to be safe since the loaders there - save EAX, EDX and ECX. (Lazy binding can be disabled with the + save EAX, EDX and ECX. (Lazy binding can be disabled with the linker or the loader if desired, to avoid the problem.) `sseregparm' @@ -23773,7 +23921,7 @@ attributes. The possible values of VISIBILITY_TYPE correspond to the visibility settings in the ELF gABI. - "default" + "default" Default visibility is the normal case for the object file format. This value is available for the visibility attribute to override other options that may change the assumed @@ -23789,13 +23937,13 @@ attributes. Default visibility corresponds to "external linkage" in the language. - "hidden" + "hidden" Hidden visibility indicates that the entity declared has a new form of linkage, which we call "hidden linkage". Two declarations of an object with hidden linkage refer to the same object if they are in the same shared object. - "internal" + "internal" Internal visibility is like hidden visibility, but with additional processor specific semantics. Unless otherwise specified by the psABI, GCC defines internal visibility to @@ -23807,7 +23955,7 @@ attributes. for instance omit the load of a PIC register since it is known that the calling function loaded the correct value. - "protected" + "protected" Protected visibility is like default visibility except that it indicates that references within the defining module bind to the definition in that module. That is, the declared entity @@ -26609,7 +26757,7 @@ _picoChip family--`picochip.h'_ 16-bit signed integer. -_PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ +_PowerPC and IBM RS6000--`config/rs6000/constraints.md'_ `b' Address base register @@ -26623,17 +26771,64 @@ _PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ `v' Altivec vector register + `wa' + Any VSX register if the -mvsx option was used or NO_REGS. + `wd' - VSX vector register to hold vector double data + VSX vector register to hold vector double data or NO_REGS. `wf' - VSX vector register to hold vector float data + VSX vector register to hold vector float data or NO_REGS. + + `wg' + If `-mmfpgpr' was used, a floating point register or NO_REGS. + + `wl' + Floating point register if the LFIWAX instruction is enabled + or NO_REGS. + + `wm' + VSX register if direct move instructions are enabled, or + NO_REGS. + + `wn' + No register (NO_REGS). + + `wr' + General purpose register if 64-bit instructions are enabled + or NO_REGS. `ws' - VSX vector register to hold scalar float data + VSX vector register to hold scalar double values or NO_REGS. - `wa' - Any VSX register + `wt' + VSX vector register to hold 128 bit integer or NO_REGS. + + `wu' + Altivec register to use for float/32-bit int loads/stores or + NO_REGS. + + `wv' + Altivec register to use for double loads/stores or NO_REGS. + + `ww' + FP or VSX register to perform float operations under `-mvsx' + or NO_REGS. + + `wx' + Floating point register if the STFIWX instruction is enabled + or NO_REGS. + + `wy' + VSX vector register to hold scalar float values or NO_REGS. + + `wz' + Floating point register if the LFIWZX instruction is enabled + or NO_REGS. + + `wQ' + A memory address that will work with the `lq' and `stq' + instructions. `h' `MQ', `CTR', or `LINK' register @@ -27058,7 +27253,7 @@ _Blackfin family--`config/bfin/constraints.md'_ M register `c' - Registers used for circular buffering, i.e. I, B, or L + Registers used for circular buffering, i.e. I, B, or L registers. `C' @@ -28608,7 +28803,7 @@ assignment, for example `r0' below: register int *p2 asm ("r1") = ...; In those cases, a solution is to use a temporary variable for each -arbitrary expression. *Note Example of asm with clobbered asm reg::. +arbitrary expression. *Note Example of asm with clobbered asm reg::.  File: gcc.info, Node: Alternate Keywords, Next: Incomplete Enums, Prev: Explicit Reg Vars, Up: C Extensions @@ -28832,7 +29027,7 @@ corresponding mode of `foo' is V4SI. The `vector_size' attribute is only applicable to integral and float scalars, although arrays, pointers, and function return values are -allowed in conjunction with this construct. Only sizes that are a power +allowed in conjunction with this construct. Only sizes that are a power of two are currently allowed. All the basic integer types can be used as base types, both as signed @@ -28869,13 +29064,13 @@ elements in the operand. It is possible to use shifting operators `<<', `>>' on integer-type vectors. The operation is defined as following: `{a0, a1, ..., an} >> -{b0, b1, ..., bn} == {a0 >> b0, a1 >> b1, ..., an >> bn}'. Vector +{b0, b1, ..., bn} == {a0 >> b0, a1 >> b1, ..., an >> bn}'. Vector operands must have the same number of elements. For convenience, it is allowed to use a binary vector operation where -one operand is a scalar. In that case the compiler transforms the +one operand is a scalar. In that case the compiler transforms the scalar operand into a vector where each element is the scalar from the -operation. The transformation happens only if the scalar could be +operation. The transformation happens only if the scalar could be safely converted to the vector-element type. Consider the following code. @@ -28903,7 +29098,7 @@ operands with a signed integral element type. Vectors are compared element-wise producing 0 when comparison is false and -1 (constant of the appropriate type where all bits are set) -otherwise. Consider the following example. +otherwise. Consider the following example. typedef int v4si __attribute__ ((vector_size (16))); @@ -29241,7 +29436,7 @@ values ensures proper usage. model can be used here. False is returned otherwise, and the execution is considered to - conform to FAILURE_MEMMODEL. This memory model cannot be + conform to FAILURE_MEMMODEL. This memory model cannot be `__ATOMIC_RELEASE' nor `__ATOMIC_ACQ_REL'. It also cannot be a stronger model than that specified by SUCCESS_MEMMODEL. @@ -29268,7 +29463,7 @@ values ensures proper usage. -- Built-in Function: TYPE __atomic_nand_fetch (TYPE *ptr, TYPE val, int memmodel) These built-in functions perform the operation suggested by the - name, and return the result of the operation. That is, + name, and return the result of the operation. That is, { *ptr OP= val; return *ptr; } @@ -29301,14 +29496,19 @@ values ensures proper usage. This built-in function performs an atomic test-and-set operation on the byte at `*PTR'. The byte is set to some implementation defined nonzero "set" value and the return value is `true' if and - only if the previous contents were "set". + only if the previous contents were "set". It should be only used + for operands of type `bool' or `char'. For other types only part + of the value may be set. All memory models are valid. -- Built-in Function: void __atomic_clear (bool *ptr, int memmodel) This built-in function performs an atomic clear operation on - `*PTR'. After the operation, `*PTR' contains 0. + `*PTR'. After the operation, `*PTR' contains 0. It should be + only used for operands of type `bool' or `char' and in conjunction + with `__atomic_test_and_set'. For other types it may only clear + partially. If the type is not `bool' prefer using `__atomic_store'. The valid memory model variants are `__ATOMIC_RELAXED', `__ATOMIC_SEQ_CST', and `__ATOMIC_RELEASE'. @@ -29371,17 +29571,19 @@ specified in addition to an existing memory model to atomic intrinsics. End lock elision on a lock variable. Memory model must be `__ATOMIC_RELEASE' or stronger. - When a lock acquire fails it's required for good performance to abort + When a lock acquire fails it is required for good performance to abort the transaction quickly. This can be done with a `_mm_pause' #include // For _mm_pause + int lockvar; + /* Acquire lock with lock elision */ while (__atomic_exchange_n(&lockvar, 1, __ATOMIC_ACQUIRE|__ATOMIC_HLE_ACQUIRE)) _mm_pause(); /* Abort failed transaction */ ... /* Free lock with lock elision */ - __atomic_clear(&lockvar, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE); + __atomic_store_n(&lockvar, 0, __ATOMIC_RELEASE|__ATOMIC_HLE_RELEASE);  File: gcc.info, Node: Object Size Checking, Next: Other Builtins, Prev: x86 specific memory model extensions for transactional memory, Up: C Extensions @@ -30136,7 +30338,9 @@ instructions, but allow the compiler to schedule those calls. * picoChip Built-in Functions:: * PowerPC Built-in Functions:: * PowerPC AltiVec/VSX Built-in Functions:: +* PowerPC Hardware Transactional Memory Built-in Functions:: * RX Built-in Functions:: +* S/390 System z Built-in Functions:: * SH Built-in Functions:: * SPARC VIS Built-in Functions:: * SPU Built-in Functions:: @@ -36231,7 +36435,7 @@ starts at `0'. If the address does not point to flash memory, return unsigned char __builtin_avr_insert_bits (unsigned long map, unsigned char bits, unsigned char val) -Insert bits from BITS into VAL and return the resulting value. The +Insert bits from BITS into VAL and return the resulting value. The nibbles of MAP determine how the insertion is performed: Let X be the N-th nibble of MAP 1. If X is `0xf', then the N-th bit of VAL is returned unaltered. @@ -36243,7 +36447,7 @@ N-th nibble of MAP undefined. One typical use case for this built-in is adjusting input and output -values to non-contiguous port layouts. Some examples: +values to non-contiguous port layouts. Some examples: // same as val, bits is unused __builtin_avr_insert_bits (0xffffffff, bits, val) @@ -36427,22 +36631,22 @@ Function prototype Example usage Assembly output `void __MQMACHS (acc, sw2, sw2)' `__MQMACHS (C, A, B)' `MQMACHS A,B,C' `void __MQMACHU (acc, uw2, uw2)' `__MQMACHU (C, A, B)' `MQMACHU A,B,C' `void __MQMACXHS (acc, sw2, `__MQMACXHS (C, A, B)' `MQMACXHS A,B,C' -sw2)' +sw2)' `void __MQMULHS (acc, sw2, sw2)' `__MQMULHS (C, A, B)' `MQMULHS A,B,C' `void __MQMULHU (acc, uw2, uw2)' `__MQMULHU (C, A, B)' `MQMULHU A,B,C' `void __MQMULXHS (acc, sw2, `__MQMULXHS (C, A, B)' `MQMULXHS A,B,C' -sw2)' +sw2)' `void __MQMULXHU (acc, uw2, `__MQMULXHU (C, A, B)' `MQMULXHU A,B,C' -uw2)' +uw2)' `sw2 __MQSATHS (sw2, sw2)' `C = __MQSATHS (A, B)' `MQSATHS A,B,C' `uw2 __MQSLLHI (uw2, int)' `C = __MQSLLHI (A, B)' `MQSLLHI A,B,C' `sw2 __MQSRAHI (sw2, int)' `C = __MQSRAHI (A, B)' `MQSRAHI A,B,C' `sw2 __MQSUBHSS (sw2, sw2)' `C = __MQSUBHSS (A, B)' `MQSUBHSS A,B,C' `uw2 __MQSUBHUS (uw2, uw2)' `C = __MQSUBHUS (A, B)' `MQSUBHUS A,B,C' `void __MQXMACHS (acc, sw2, `__MQXMACHS (C, A, B)' `MQXMACHS A,B,C' -sw2)' +sw2)' `void __MQXMACXHS (acc, sw2, `__MQXMACXHS (C, A, B)' `MQXMACXHS A,B,C' -sw2)' +sw2)' `uw1 __MRDACC (acc)' `B = __MRDACC (A)' `MRDACC A,B' `uw1 __MRDACCG (acc)' `B = __MRDACCG (A)' `MRDACCG A,B' `uw1 __MROTLI (uw1, const)' `C = __MROTLI (A, B)' `MROTLI A,#B,C' @@ -37847,8 +38051,8 @@ that is part of the name. v2si __builtin_ia32_pswapdsi (v2si) The following built-in functions are available when `-mrtm' is used -They are used for restricted transactional memory. These are the -internal low level functions. Normally the functions in *note X86 +They are used for restricted transactional memory. These are the +internal low level functions. Normally the functions in *note X86 transactional memory intrinsics:: should be used instead. int __builtin_ia32_xbegin () @@ -37862,7 +38066,7 @@ File: gcc.info, Node: X86 transactional memory intrinsics, Next: MIPS DSP Buil 6.56.8 X86 transaction memory intrinsics ---------------------------------------- -Hardware transactional memory intrinsics for i386. These allow to use +Hardware transactional memory intrinsics for i386. These allow to use memory transactions with RTM (Restricted Transactional Memory). For using HLE (Hardware Lock Elision) see *note x86 specific memory model extensions for transactional memory:: instead. This support is enabled @@ -37915,8 +38119,8 @@ and suitable fallback code always needs to be supplied. Transaction abort in a inner nested transaction -- RTM Function: void _xend () - Commit the current transaction. When no transaction is active this - will fault. All memory side effects of the transactions will + Commit the current transaction. When no transaction is active this + will fault. All memory side effects of the transactions will become visible to other threads in an atomic matter. -- RTM Function: int _xtest () @@ -37924,7 +38128,7 @@ and suitable fallback code always needs to be supplied. otherwise 0. -- RTM Function: void _xabort (status) - Abort the current transaction. When no transaction is active this + Abort the current transaction. When no transaction is active this is a no-op. status must be a 8bit constant, that is included in the status code returned by `_xbegin' @@ -38687,9 +38891,12 @@ processors: float __builtin_rsqrtf (float); double __builtin_recipdiv (double, double); double __builtin_rsqrt (double); - long __builtin_bpermd (long, long); uint64_t __builtin_ppc_get_timebase (); unsigned long __builtin_ppc_mftb (); + double __builtin_unpack_longdouble (long double, int); + double __builtin_longdouble_dw0 (long double); + double __builtin_longdouble_dw1 (long double); + long double __builtin_pack_longdouble (double, double); The `vec_rsqrt', `__builtin_rsqrt', and `__builtin_rsqrtf' functions generate multiple instructions to implement the reciprocal sqrt @@ -38707,8 +38914,52 @@ The `__builtin_ppc_mftb' function always generates one instruction and returns the Time Base Register value as an unsigned long, throwing away the most significant word on 32-bit environments. - -File: gcc.info, Node: PowerPC AltiVec/VSX Built-in Functions, Next: RX Built-in Functions, Prev: PowerPC Built-in Functions, Up: Target Builtins + The following built-in functions are available for the PowerPC family +of processors, starting with ISA 2.06 or later (`-mcpu=power7' or +`-mpopcntd'): + long __builtin_bpermd (long, long); + int __builtin_divwe (int, int); + int __builtin_divweo (int, int); + unsigned int __builtin_divweu (unsigned int, unsigned int); + unsigned int __builtin_divweuo (unsigned int, unsigned int); + long __builtin_divde (long, long); + long __builtin_divdeo (long, long); + unsigned long __builtin_divdeu (unsigned long, unsigned long); + unsigned long __builtin_divdeuo (unsigned long, unsigned long); + unsigned int cdtbcd (unsigned int); + unsigned int cbcdtd (unsigned int); + unsigned int addg6s (unsigned int, unsigned int); + + The `__builtin_divde', `__builtin_divdeo', `__builitin_divdeu', +`__builtin_divdeou' functions require a 64-bit environment support ISA +2.06 or later. + + The following built-in functions are available for the PowerPC family +of processors when hardware decimal floating point (`-mhard-dfp') is +available: + _Decimal64 __builtin_dxex (_Decimal64); + _Decimal128 __builtin_dxexq (_Decimal128); + _Decimal64 __builtin_ddedpd (int, _Decimal64); + _Decimal128 __builtin_ddedpdq (int, _Decimal128); + _Decimal64 __builtin_denbcd (int, _Decimal64); + _Decimal128 __builtin_denbcdq (int, _Decimal128); + _Decimal64 __builtin_diex (_Decimal64, _Decimal64); + _Decimal128 _builtin_diexq (_Decimal128, _Decimal128); + _Decimal64 __builtin_dscli (_Decimal64, int); + _Decimal128 __builitn_dscliq (_Decimal128, int); + _Decimal64 __builtin_dscri (_Decimal64, int); + _Decimal128 __builitn_dscriq (_Decimal128, int); + unsigned long long __builtin_unpack_dec128 (_Decimal128, int); + _Decimal128 __builtin_pack_dec128 (unsigned long long, unsigned long long); + + The following built-in functions are available for the PowerPC family +of processors when the Vector Scalar (vsx) instruction set is available: + unsigned long long __builtin_unpack_vector_int128 (vector __int128_t, int); + vector __int128_t __builtin_pack_vector_int128 (unsigned long long, + unsigned long long); + + +File: gcc.info, Node: PowerPC AltiVec/VSX Built-in Functions, Next: PowerPC Hardware Transactional Memory Built-in Functions, Prev: PowerPC Built-in Functions, Up: Target Builtins 6.56.15 PowerPC AltiVec Built-in Functions ------------------------------------------ @@ -40743,16 +40994,614 @@ additional functions are available: void vec_vsx_st (vector bool char, int, unsigned char *); void vec_vsx_st (vector bool char, int, signed char *); + vector double vec_xxpermdi (vector double, vector double, int); + vector float vec_xxpermdi (vector float, vector float, int); + vector long long vec_xxpermdi (vector long long, vector long long, int); + vector unsigned long long vec_xxpermdi (vector unsigned long long, + vector unsigned long long, int); + vector int vec_xxpermdi (vector int, vector int, int); + vector unsigned int vec_xxpermdi (vector unsigned int, + vector unsigned int, int); + vector short vec_xxpermdi (vector short, vector short, int); + vector unsigned short vec_xxpermdi (vector unsigned short, + vector unsigned short, int); + vector signed char vec_xxpermdi (vector signed char, vector signed char, int); + vector unsigned char vec_xxpermdi (vector unsigned char, + vector unsigned char, int); + + vector double vec_xxsldi (vector double, vector double, int); + vector float vec_xxsldi (vector float, vector float, int); + vector long long vec_xxsldi (vector long long, vector long long, int); + vector unsigned long long vec_xxsldi (vector unsigned long long, + vector unsigned long long, int); + vector int vec_xxsldi (vector int, vector int, int); + vector unsigned int vec_xxsldi (vector unsigned int, vector unsigned int, int); + vector short vec_xxsldi (vector short, vector short, int); + vector unsigned short vec_xxsldi (vector unsigned short, + vector unsigned short, int); + vector signed char vec_xxsldi (vector signed char, vector signed char, int); + vector unsigned char vec_xxsldi (vector unsigned char, + vector unsigned char, int); + Note that the `vec_ld' and `vec_st' built-in functions always generate the AltiVec `LVX' and `STVX' instructions even if the VSX instruction set is available. The `vec_vsx_ld' and `vec_vsx_st' built-in functions always generate the VSX `LXVD2X', `LXVW4X', `STXVD2X', and `STXVW4X' instructions. + If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for both 32-bit and 64-bit targets. For 64-bit targets, you +can use VECTOR LONG instead of VECTOR LONG LONG, VECTOR BOOL LONG +instead of VECTOR BOOL LONG LONG, and VECTOR UNSIGNED LONG instead of +VECTOR UNSIGNED LONG LONG. + + vector long long vec_abs (vector long long); + + vector long long vec_add (vector long long, vector long long); + vector unsigned long long vec_add (vector unsigned long long, + vector unsigned long long); + + int vec_all_eq (vector long long, vector long long); + int vec_all_ge (vector long long, vector long long); + int vec_all_gt (vector long long, vector long long); + int vec_all_le (vector long long, vector long long); + int vec_all_lt (vector long long, vector long long); + int vec_all_ne (vector long long, vector long long); + int vec_any_eq (vector long long, vector long long); + int vec_any_ge (vector long long, vector long long); + int vec_any_gt (vector long long, vector long long); + int vec_any_le (vector long long, vector long long); + int vec_any_lt (vector long long, vector long long); + int vec_any_ne (vector long long, vector long long); + + vector long long vec_eqv (vector long long, vector long long); + vector long long vec_eqv (vector bool long long, vector long long); + vector long long vec_eqv (vector long long, vector bool long long); + vector unsigned long long vec_eqv (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_eqv (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_eqv (vector unsigned long long, + vector bool long long); + vector int vec_eqv (vector int, vector int); + vector int vec_eqv (vector bool int, vector int); + vector int vec_eqv (vector int, vector bool int); + vector unsigned int vec_eqv (vector unsigned int, vector unsigned int); + vector unsigned int vec_eqv (vector bool unsigned int, + vector unsigned int); + vector unsigned int vec_eqv (vector unsigned int, + vector bool unsigned int); + vector short vec_eqv (vector short, vector short); + vector short vec_eqv (vector bool short, vector short); + vector short vec_eqv (vector short, vector bool short); + vector unsigned short vec_eqv (vector unsigned short, vector unsigned short); + vector unsigned short vec_eqv (vector bool unsigned short, + vector unsigned short); + vector unsigned short vec_eqv (vector unsigned short, + vector bool unsigned short); + vector signed char vec_eqv (vector signed char, vector signed char); + vector signed char vec_eqv (vector bool signed char, vector signed char); + vector signed char vec_eqv (vector signed char, vector bool signed char); + vector unsigned char vec_eqv (vector unsigned char, vector unsigned char); + vector unsigned char vec_eqv (vector bool unsigned char, vector unsigned char); + vector unsigned char vec_eqv (vector unsigned char, vector bool unsigned char); + + vector long long vec_max (vector long long, vector long long); + vector unsigned long long vec_max (vector unsigned long long, + vector unsigned long long); + + vector long long vec_min (vector long long, vector long long); + vector unsigned long long vec_min (vector unsigned long long, + vector unsigned long long); + + vector long long vec_nand (vector long long, vector long long); + vector long long vec_nand (vector bool long long, vector long long); + vector long long vec_nand (vector long long, vector bool long long); + vector unsigned long long vec_nand (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_nand (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_nand (vector unsigned long long, + vector bool long long); + vector int vec_nand (vector int, vector int); + vector int vec_nand (vector bool int, vector int); + vector int vec_nand (vector int, vector bool int); + vector unsigned int vec_nand (vector unsigned int, vector unsigned int); + vector unsigned int vec_nand (vector bool unsigned int, + vector unsigned int); + vector unsigned int vec_nand (vector unsigned int, + vector bool unsigned int); + vector short vec_nand (vector short, vector short); + vector short vec_nand (vector bool short, vector short); + vector short vec_nand (vector short, vector bool short); + vector unsigned short vec_nand (vector unsigned short, vector unsigned short); + vector unsigned short vec_nand (vector bool unsigned short, + vector unsigned short); + vector unsigned short vec_nand (vector unsigned short, + vector bool unsigned short); + vector signed char vec_nand (vector signed char, vector signed char); + vector signed char vec_nand (vector bool signed char, vector signed char); + vector signed char vec_nand (vector signed char, vector bool signed char); + vector unsigned char vec_nand (vector unsigned char, vector unsigned char); + vector unsigned char vec_nand (vector bool unsigned char, vector unsigned char); + vector unsigned char vec_nand (vector unsigned char, vector bool unsigned char); + + vector long long vec_orc (vector long long, vector long long); + vector long long vec_orc (vector bool long long, vector long long); + vector long long vec_orc (vector long long, vector bool long long); + vector unsigned long long vec_orc (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_orc (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_orc (vector unsigned long long, + vector bool long long); + vector int vec_orc (vector int, vector int); + vector int vec_orc (vector bool int, vector int); + vector int vec_orc (vector int, vector bool int); + vector unsigned int vec_orc (vector unsigned int, vector unsigned int); + vector unsigned int vec_orc (vector bool unsigned int, + vector unsigned int); + vector unsigned int vec_orc (vector unsigned int, + vector bool unsigned int); + vector short vec_orc (vector short, vector short); + vector short vec_orc (vector bool short, vector short); + vector short vec_orc (vector short, vector bool short); + vector unsigned short vec_orc (vector unsigned short, vector unsigned short); + vector unsigned short vec_orc (vector bool unsigned short, + vector unsigned short); + vector unsigned short vec_orc (vector unsigned short, + vector bool unsigned short); + vector signed char vec_orc (vector signed char, vector signed char); + vector signed char vec_orc (vector bool signed char, vector signed char); + vector signed char vec_orc (vector signed char, vector bool signed char); + vector unsigned char vec_orc (vector unsigned char, vector unsigned char); + vector unsigned char vec_orc (vector bool unsigned char, vector unsigned char); + vector unsigned char vec_orc (vector unsigned char, vector bool unsigned char); + + vector int vec_pack (vector long long, vector long long); + vector unsigned int vec_pack (vector unsigned long long, + vector unsigned long long); + vector bool int vec_pack (vector bool long long, vector bool long long); + + vector int vec_packs (vector long long, vector long long); + vector unsigned int vec_packs (vector unsigned long long, + vector unsigned long long); + + vector unsigned int vec_packsu (vector long long, vector long long); + + vector long long vec_rl (vector long long, + vector unsigned long long); + vector long long vec_rl (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sl (vector long long, vector unsigned long long); + vector long long vec_sl (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sr (vector long long, vector unsigned long long); + vector unsigned long long char vec_sr (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sra (vector long long, vector unsigned long long); + vector unsigned long long vec_sra (vector unsigned long long, + vector unsigned long long); + + vector long long vec_sub (vector long long, vector long long); + vector unsigned long long vec_sub (vector unsigned long long, + vector unsigned long long); + + vector long long vec_unpackh (vector int); + vector unsigned long long vec_unpackh (vector unsigned int); + + vector long long vec_unpackl (vector int); + vector unsigned long long vec_unpackl (vector unsigned int); + + vector long long vec_vaddudm (vector long long, vector long long); + vector long long vec_vaddudm (vector bool long long, vector long long); + vector long long vec_vaddudm (vector long long, vector bool long long); + vector unsigned long long vec_vaddudm (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_vaddudm (vector bool unsigned long long, + vector unsigned long long); + vector unsigned long long vec_vaddudm (vector unsigned long long, + vector bool unsigned long long); + + vector long long vec_vbpermq (vector signed char, vector signed char); + vector long long vec_vbpermq (vector unsigned char, vector unsigned char); + + vector long long vec_vclz (vector long long); + vector unsigned long long vec_vclz (vector unsigned long long); + vector int vec_vclz (vector int); + vector unsigned int vec_vclz (vector int); + vector short vec_vclz (vector short); + vector unsigned short vec_vclz (vector unsigned short); + vector signed char vec_vclz (vector signed char); + vector unsigned char vec_vclz (vector unsigned char); + + vector signed char vec_vclzb (vector signed char); + vector unsigned char vec_vclzb (vector unsigned char); + + vector long long vec_vclzd (vector long long); + vector unsigned long long vec_vclzd (vector unsigned long long); + + vector short vec_vclzh (vector short); + vector unsigned short vec_vclzh (vector unsigned short); + + vector int vec_vclzw (vector int); + vector unsigned int vec_vclzw (vector int); + + vector signed char vec_vgbbd (vector signed char); + vector unsigned char vec_vgbbd (vector unsigned char); + + vector long long vec_vmaxsd (vector long long, vector long long); + + vector unsigned long long vec_vmaxud (vector unsigned long long, + unsigned vector long long); + + vector long long vec_vminsd (vector long long, vector long long); + + vector unsigned long long vec_vminud (vector long long, + vector long long); + + vector int vec_vpksdss (vector long long, vector long long); + vector unsigned int vec_vpksdss (vector long long, vector long long); + + vector unsigned int vec_vpkudus (vector unsigned long long, + vector unsigned long long); + + vector int vec_vpkudum (vector long long, vector long long); + vector unsigned int vec_vpkudum (vector unsigned long long, + vector unsigned long long); + vector bool int vec_vpkudum (vector bool long long, vector bool long long); + + vector long long vec_vpopcnt (vector long long); + vector unsigned long long vec_vpopcnt (vector unsigned long long); + vector int vec_vpopcnt (vector int); + vector unsigned int vec_vpopcnt (vector int); + vector short vec_vpopcnt (vector short); + vector unsigned short vec_vpopcnt (vector unsigned short); + vector signed char vec_vpopcnt (vector signed char); + vector unsigned char vec_vpopcnt (vector unsigned char); + + vector signed char vec_vpopcntb (vector signed char); + vector unsigned char vec_vpopcntb (vector unsigned char); + + vector long long vec_vpopcntd (vector long long); + vector unsigned long long vec_vpopcntd (vector unsigned long long); + + vector short vec_vpopcnth (vector short); + vector unsigned short vec_vpopcnth (vector unsigned short); + + vector int vec_vpopcntw (vector int); + vector unsigned int vec_vpopcntw (vector int); + + vector long long vec_vrld (vector long long, vector unsigned long long); + vector unsigned long long vec_vrld (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsld (vector long long, vector unsigned long long); + vector long long vec_vsld (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsrad (vector long long, vector unsigned long long); + vector unsigned long long vec_vsrad (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsrd (vector long long, vector unsigned long long); + vector unsigned long long char vec_vsrd (vector unsigned long long, + vector unsigned long long); + + vector long long vec_vsubudm (vector long long, vector long long); + vector long long vec_vsubudm (vector bool long long, vector long long); + vector long long vec_vsubudm (vector long long, vector bool long long); + vector unsigned long long vec_vsubudm (vector unsigned long long, + vector unsigned long long); + vector unsigned long long vec_vsubudm (vector bool long long, + vector unsigned long long); + vector unsigned long long vec_vsubudm (vector unsigned long long, + vector bool long long); + + vector long long vec_vupkhsw (vector int); + vector unsigned long long vec_vupkhsw (vector unsigned int); + + vector long long vec_vupklsw (vector int); + vector unsigned long long vec_vupklsw (vector int); + + If the ISA 2.07 additions to the vector/scalar (power8-vector) +instruction set is available, the following additional functions are +available for 64-bit targets. New vector types (VECTOR __INT128_T and +VECTOR __UINT128_T) are available to hold the __INT128_T and +__UINT128_T types to use these builtins. + + The normal vector extract, and set operations work on VECTOR +__INT128_T and VECTOR __UINT128_T types, but the index value must be 0. + + vector __int128_t vec_vaddcuq (vector __int128_t, vector __int128_t); + vector __uint128_t vec_vaddcuq (vector __uint128_t, vector __uint128_t); + + vector __int128_t vec_vadduqm (vector __int128_t, vector __int128_t); + vector __uint128_t vec_vadduqm (vector __uint128_t, vector __uint128_t); + + vector __int128_t vec_vaddecuq (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vaddecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vaddeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vaddeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vsubecuq (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vsubecuq (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vsubeuqm (vector __int128_t, vector __int128_t, + vector __int128_t); + vector __uint128_t vec_vsubeuqm (vector __uint128_t, vector __uint128_t, + vector __uint128_t); + + vector __int128_t vec_vsubcuq (vector __int128_t, vector __int128_t); + vector __uint128_t vec_vsubcuq (vector __uint128_t, vector __uint128_t); + + __int128_t vec_vsubuqm (__int128_t, __int128_t); + __uint128_t vec_vsubuqm (__uint128_t, __uint128_t); + + vector __int128_t __builtin_bcdadd (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_lt (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_eq (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_gt (vector __int128_t, vector__int128_t); + int __builtin_bcdadd_ov (vector __int128_t, vector__int128_t); + vector __int128_t bcdsub (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_lt (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_eq (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_gt (vector __int128_t, vector__int128_t); + int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t); + + If the cryptographic instructions are enabled (`-mcrypto' or +`-mcpu=power8'), the following builtins are enabled. + + vector unsigned long long __builtin_crypto_vsbox (vector unsigned long long); + + vector unsigned long long __builtin_crypto_vcipher (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vcipherlast + (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vncipher (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vncipherlast + (vector unsigned long long, + vector unsigned long long); + + vector unsigned char __builtin_crypto_vpermxor (vector unsigned char, + vector unsigned char, + vector unsigned char); + + vector unsigned short __builtin_crypto_vpermxor (vector unsigned short, + vector unsigned short, + vector unsigned short); + + vector unsigned int __builtin_crypto_vpermxor (vector unsigned int, + vector unsigned int, + vector unsigned int); + + vector unsigned long long __builtin_crypto_vpermxor (vector unsigned long long, + vector unsigned long long, + vector unsigned long long); + + vector unsigned char __builtin_crypto_vpmsumb (vector unsigned char, + vector unsigned char); + + vector unsigned short __builtin_crypto_vpmsumb (vector unsigned short, + vector unsigned short); + + vector unsigned int __builtin_crypto_vpmsumb (vector unsigned int, + vector unsigned int); + + vector unsigned long long __builtin_crypto_vpmsumb (vector unsigned long long, + vector unsigned long long); + + vector unsigned long long __builtin_crypto_vshasigmad + (vector unsigned long long, int, int); + + vector unsigned int __builtin_crypto_vshasigmaw (vector unsigned int, + int, int); + + The second argument to the __BUILTIN_CRYPTO_VSHASIGMAD and +__BUILTIN_CRYPTO_VSHASIGMAW builtin functions must be a constant +integer that is 0 or 1. The third argument to these builtin functions +must be a constant integer in the range of 0 to 15. + + +File: gcc.info, Node: PowerPC Hardware Transactional Memory Built-in Functions, Next: RX Built-in Functions, Prev: PowerPC AltiVec/VSX Built-in Functions, Up: Target Builtins + +6.56.16 PowerPC Hardware Transactional Memory Built-in Functions +---------------------------------------------------------------- + +GCC provides two interfaces for accessing the Hardware Transactional +Memory (HTM) instructions available on some of the PowerPC family of +prcoessors (eg, POWER8). The two interfaces come in a low level +interface, consisting of built-in functions specific to PowerPC and a +higher level interface consisting of inline functions that are common +between PowerPC and S/390. + +6.56.16.1 PowerPC HTM Low Level Built-in Functions +.................................................. + +The following low level built-in functions are available with `-mhtm' +or `-mcpu=CPU' where CPU is `power8' or later. They all generate the +machine instruction that is part of the name. + + The HTM built-ins return true or false depending on their success and +their arguments match exactly the type and order of the associated +hardware instruction's operands. Refer to the ISA manual for a +description of each instruction's operands. + + unsigned int __builtin_tbegin (unsigned int) + unsigned int __builtin_tend (unsigned int) + + unsigned int __builtin_tabort (unsigned int) + unsigned int __builtin_tabortdc (unsigned int, unsigned int, unsigned int) + unsigned int __builtin_tabortdci (unsigned int, unsigned int, int) + unsigned int __builtin_tabortwc (unsigned int, unsigned int, unsigned int) + unsigned int __builtin_tabortwci (unsigned int, unsigned int, int) + + unsigned int __builtin_tcheck (unsigned int) + unsigned int __builtin_treclaim (unsigned int) + unsigned int __builtin_trechkpt (void) + unsigned int __builtin_tsr (unsigned int) + + In addition to the above HTM built-ins, we have added built-ins for +some common extended mnemonics of the HTM instructions: + + unsigned int __builtin_tendall (void) + unsigned int __builtin_tresume (void) + unsigned int __builtin_tsuspend (void) + + The following set of built-in functions are available to gain access +to the HTM specific special purpose registers. + + unsigned long __builtin_get_texasr (void) + unsigned long __builtin_get_texasru (void) + unsigned long __builtin_get_tfhar (void) + unsigned long __builtin_get_tfiar (void) + + void __builtin_set_texasr (unsigned long); + void __builtin_set_texasru (unsigned long); + void __builtin_set_tfhar (unsigned long); + void __builtin_set_tfiar (unsigned long); + + Example usage of these low level built-in functions may look like: + + #include + + int num_retries = 10; + + while (1) + { + if (__builtin_tbegin (0)) + { + /* Transaction State Initiated. */ + if (is_locked (lock)) + __builtin_tabort (0); + ... transaction code... + __builtin_tend (0); + break; + } + else + { + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || _TEXASRU_FAILURE_PERSISTENT (__builtin_get_texasru ())) + { + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + } + } + } + + One final built-in function has been added that returns the value of +the 2-bit Transaction State field of the Machine Status Register (MSR) +as stored in `CR0'. + + unsigned long __builtin_ttest (void) + + This built-in can be used to determine the current transaction state +using the following code example: + + #include + + unsigned char tx_state = _HTM_STATE (__builtin_ttest ()); + + if (tx_state == _HTM_TRANSACTIONAL) + { + /* Code to use in transactional state. */ + } + else if (tx_state == _HTM_NONTRANSACTIONAL) + { + /* Code to use in non-transactional state. */ + } + else if (tx_state == _HTM_SUSPENDED) + { + /* Code to use in transaction suspended state. */ + } + +6.56.16.2 PowerPC HTM High Level Inline Functions +................................................. + +The following high level HTM interface is made available by including +`' and using `-mhtm' or `-mcpu=CPU' where CPU is +`power8' or later. This interface is common between PowerPC and S/390, +allowing users to write one HTM source implementation that can be +compiled and executed on either system. + + long __TM_simple_begin (void) + long __TM_begin (void* const TM_buff) + long __TM_end (void) + void __TM_abort (void) + void __TM_named_abort (unsigned char const code) + void __TM_resume (void) + void __TM_suspend (void) + + long __TM_is_user_abort (void* const TM_buff) + long __TM_is_named_user_abort (void* const TM_buff, unsigned char *code) + long __TM_is_illegal (void* const TM_buff) + long __TM_is_footprint_exceeded (void* const TM_buff) + long __TM_nesting_depth (void* const TM_buff) + long __TM_is_nested_too_deep(void* const TM_buff) + long __TM_is_conflict(void* const TM_buff) + long __TM_is_failure_persistent(void* const TM_buff) + long __TM_failure_address(void* const TM_buff) + long long __TM_failure_code(void* const TM_buff) + + Using these common set of HTM inline functions, we can create a more +portable version of the HTM example in the previous section that will +work on either PowerPC or S/390: + + #include + + int num_retries = 10; + TM_buff_type TM_buff; + + while (1) + { + if (__TM_begin (TM_buff)) + { + /* Transaction State Initiated. */ + if (is_locked (lock)) + __TM_abort (); + ... transaction code... + __TM_end (); + break; + } + else + { + /* Transaction State Failed. Use locks if the transaction + failure is "persistent" or we've tried too many times. */ + if (num_retries-- <= 0 + || __TM_is_failure_persistent (TM_buff)) + { + acquire_lock (lock); + ... non transactional fallback path... + release_lock (lock); + break; + } + } + } +  -File: gcc.info, Node: RX Built-in Functions, Next: SH Built-in Functions, Prev: PowerPC AltiVec/VSX Built-in Functions, Up: Target Builtins +File: gcc.info, Node: RX Built-in Functions, Next: S/390 System z Built-in Functions, Prev: PowerPC Hardware Transactional Memory Built-in Functions, Up: Target Builtins -6.56.16 RX Built-in Functions +6.56.17 RX Built-in Functions ----------------------------- GCC supports some of the RX instructions which cannot be expressed in @@ -40848,9 +41697,117 @@ following functions are supported: Generates the `wait' machine instruction.  -File: gcc.info, Node: SH Built-in Functions, Next: SPARC VIS Built-in Functions, Prev: RX Built-in Functions, Up: Target Builtins +File: gcc.info, Node: S/390 System z Built-in Functions, Next: SH Built-in Functions, Prev: RX Built-in Functions, Up: Target Builtins + +6.56.18 S/390 System z Built-in Functions +----------------------------------------- + + -- Built-in Function: int __builtin_tbegin (void*) + Generates the `tbegin' machine instruction starting a + non-constraint hardware transaction. If the parameter is non-NULL + the memory area is used to store the transaction diagnostic buffer + and will be passed as first operand to `tbegin'. This buffer can + be defined using the `struct __htm_tdb' C struct defined in + `htmintrin.h' and must reside on a double-word boundary. The + second tbegin operand is set to `0xff0c'. This enables + save/restore of all GPRs and disables aborts for FPR and AR + manipulations inside the transaction body. The condition code set + by the tbegin instruction is returned as integer value. The tbegin + instruction by definition overwrites the content of all FPRs. The + compiler will generate code which saves and restores the FPRs. For + soft-float code it is recommended to used the `*_nofloat' variant. + In order to prevent a TDB from being written it is required to + pass an constant zero value as parameter. Passing the zero value + through a variable is not sufficient. Although modifications of + access registers inside the transaction will not trigger an + transaction abort it is not supported to actually modify them. + Access registers do not get saved when entering a transaction. + They will have undefined state when reaching the abort code. + + Macros for the possible return codes of tbegin are defined in the +`htmintrin.h' header file: + +`_HTM_TBEGIN_STARTED' + `tbegin' has been executed as part of normal processing. The + transaction body is supposed to be executed. + +`_HTM_TBEGIN_INDETERMINATE' + The transaction was aborted due to an indeterminate condition which + might be persistent. + +`_HTM_TBEGIN_TRANSIENT' + The transaction aborted due to a transient failure. The + transaction should be re-executed in that case. + +`_HTM_TBEGIN_PERSISTENT' + The transaction aborted due to a persistent failure. Re-execution + under same circumstances will not be productive. + + -- Macro: _HTM_FIRST_USER_ABORT_CODE + The `_HTM_FIRST_USER_ABORT_CODE' defined in `htmintrin.h' + specifies the first abort code which can be used for + `__builtin_tabort'. Values below this threshold are reserved for + machine use. + + -- Data type: struct __htm_tdb + The `struct __htm_tdb' defined in `htmintrin.h' describes the + structure of the transaction diagnostic block as specified in the + Principles of Operation manual chapter 5-91. + + -- Built-in Function: int __builtin_tbegin_nofloat (void*) + Same as `__builtin_tbegin' but without FPR saves and restores. + Using this variant in code making use of FPRs will leave the FPRs + in undefined state when entering the transaction abort handler + code. -6.56.17 SH Built-in Functions + -- Built-in Function: int __builtin_tbegin_retry (void*, int) + In addition to `__builtin_tbegin' a loop for transient failures is + generated. If tbegin returns a condition code of 2 the transaction + will be retried as often as specified in the second argument. The + perform processor assist instruction is used to tell the CPU about + the number of fails so far. + + -- Built-in Function: int __builtin_tbegin_retry_nofloat (void*, int) + Same as `__builtin_tbegin_retry' but without FPR saves and + restores. Using this variant in code making use of FPRs will leave + the FPRs in undefined state when entering the transaction abort + handler code. + + -- Built-in Function: void __builtin_tbeginc (void) + Generates the `tbeginc' machine instruction starting a constraint + hardware transaction. The second operand is set to `0xff08'. + + -- Built-in Function: int __builtin_tend (void) + Generates the `tend' machine instruction finishing a transaction + and making the changes visible to other threads. The condition + code generated by tend is returned as integer value. + + -- Built-in Function: void __builtin_tabort (int) + Generates the `tabort' machine instruction with the specified + abort code. Abort codes from 0 through 255 are reserved and will + result in an error message. + + -- Built-in Function: void __builtin_tx_assist (int) + Generates the `ppa rX,rY,1' machine instruction. Where the + integer parameter is loaded into rX and a value of zero is loaded + into rY. The integer parameter specifies the number of times the + transaction repeatedly aborted. + + -- Built-in Function: int __builtin_tx_nesting_depth (void) + Generates the `etnd' machine instruction. The current nesting + depth is returned as integer value. For a nesting depth of 0 the + code is not executed as part of an transaction. + + -- Built-in Function: void __builtin_non_tx_store (uint64_t *, + uint64_t) + Generates the `ntstg' machine instruction. The second argument is + written to the first arguments location. The store operation will + not be rolled-back in case of an transaction abort. + + +File: gcc.info, Node: SH Built-in Functions, Next: SPARC VIS Built-in Functions, Prev: S/390 System z Built-in Functions, Up: Target Builtins + +6.56.19 SH Built-in Functions ----------------------------- The following built-in functions are supported on the SH1, SH2, SH3 and @@ -40885,7 +41842,7 @@ SH4 families of processors:  File: gcc.info, Node: SPARC VIS Built-in Functions, Next: SPU Built-in Functions, Prev: SH Built-in Functions, Up: Target Builtins -6.56.18 SPARC VIS Built-in Functions +6.56.20 SPARC VIS Built-in Functions ------------------------------------ GCC supports SIMD operations on the SPARC using both the generic vector @@ -41026,7 +41983,7 @@ functions also become available:  File: gcc.info, Node: SPU Built-in Functions, Next: TI C6X Built-in Functions, Prev: SPARC VIS Built-in Functions, Up: Target Builtins -6.56.19 SPU Built-in Functions +6.56.21 SPU Built-in Functions ------------------------------ GCC provides extensions for the SPU processor as described in the @@ -41065,14 +42022,14 @@ differs in several ways. _Note:_ Only the interface described in the aforementioned -specification is supported. Internally, GCC uses built-in functions to +specification is supported. Internally, GCC uses built-in functions to implement the required functionality, but these are not supported and are subject to change without notice.  File: gcc.info, Node: TI C6X Built-in Functions, Next: TILE-Gx Built-in Functions, Prev: SPU Built-in Functions, Up: Target Builtins -6.56.20 TI C6X Built-in Functions +6.56.22 TI C6X Built-in Functions --------------------------------- GCC provides intrinsics to access certain instructions of the TI C6X @@ -41111,7 +42068,7 @@ C6X instructions.  File: gcc.info, Node: TILE-Gx Built-in Functions, Next: TILEPro Built-in Functions, Prev: TI C6X Built-in Functions, Up: Target Builtins -6.56.21 TILE-Gx Built-in Functions +6.56.23 TILE-Gx Built-in Functions ---------------------------------- GCC provides intrinsics to access every instruction of the TILE-Gx @@ -41143,7 +42100,7 @@ after it.  File: gcc.info, Node: TILEPro Built-in Functions, Prev: TILE-Gx Built-in Functions, Up: Target Builtins -6.56.22 TILEPro Built-in Functions +6.56.24 TILEPro Built-in Functions ---------------------------------- GCC provides intrinsics to access every instruction of the TILEPro @@ -41435,7 +42392,7 @@ File: gcc.info, Node: Symbol-Renaming Pragmas, Next: Structure-Packing Pragmas For compatibility with the Solaris system headers, GCC supports two `#pragma' directives that change the name used in assembly for a given -declaration. To get this effect on all platforms supported by GCC, use +declaration. To get this effect on all platforms supported by GCC, use the asm labels extension (*note Asm Labels::). `redefine_extname OLDNAME NEWNAME' @@ -41471,7 +42428,7 @@ File: gcc.info, Node: Structure-Packing Pragmas, Next: Weak Pragmas, Prev: Sy For compatibility with Microsoft Windows compilers, GCC supports a set of `#pragma' directives that change the maximum alignment of members of structures (other than zero-width bit-fields), unions, and classes -subsequently defined. The N value below always is required to be a +subsequently defined. The N value below always is required to be a small power of two and specifies the new alignment in bytes. 1. `#pragma pack(N)' simply sets the new alignment. @@ -41628,7 +42585,7 @@ pop_macro("MACRO_NAME")'. `#pragma pop_macro("MACRO_NAME")' This pragma sets the value of the macro named as MACRO_NAME to the - value on top of the stack for this macro. If the stack for + value on top of the stack for this macro. If the stack for MACRO_NAME is empty, the value of the macro remains unchanged. For example: @@ -42286,9 +43243,9 @@ If all calls to the function can be inlined, you can avoid emitting the function by compiling with `-fno-implement-inlines'. If any calls are not inlined, you will get linker errors. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) A file's "basename" is the name stripped of all leading path + (1) A file's "basename" is the name stripped of all leading path information and of trailing suffixes, such as `.h' or `.C' or `.cc'.  @@ -42561,10 +43518,10 @@ the execution platform. Here is an example. return 0; } - In the above example, four versions of function foo are created. The + In the above example, four versions of function foo are created. The first version of foo with the target attribute "default" is the default version. This version gets executed when no other target specific -version qualifies for execution on a particular platform. A new version +version qualifies for execution on a particular platform. A new version of foo is created by using the same function signature but with a different target string. Function foo is called or a pointer to it is taken just like a regular function. GCC takes care of doing the @@ -42850,7 +43807,7 @@ expressions, e.g. ` enum E { e = int(2.2 * 3.7) } ' This extension is deprecated and will be removed from a future version. G++ allows static data members of const floating-point type to be -declared with an initializer in a class definition. The standard only +declared with an initializer in a class definition. The standard only allows initializers for static members of const integral types and const enumeration types so this extension has been deprecated and will be removed from a future version. @@ -42867,8 +43824,8 @@ used to be acceptable in previous drafts of the standard, such as the ARM [Annotated C++ Reference Manual], are no longer accepted. In order to allow compilation of C++ written to such drafts, G++ contains some backwards compatibilities. _All such backwards compatibility features -are liable to disappear in future versions of G++._ They should be -considered deprecated. *Note Deprecated Features::. +are liable to disappear in future versions of G++._ They should be +considered deprecated. *Note Deprecated Features::. `For scope' If a variable is declared at for scope, it used to remain in scope @@ -43163,7 +44120,7 @@ selectors and methods and about objects and classes. `unsigned long' `L' `long long' `q' `unsigned long `Q' -long' +long' `float' `f' `double' `d' `long double' `D' @@ -43221,12 +44178,12 @@ compiler on an i386 machine: Objective-C type Compiler encoding int a[10]; `[10i]' struct { `{?=i[3f]b128i3b131i2c}' - int i; - float f[3]; - int a:3; - int b:2; - char c; - } + int i; + float f[3]; + int a:3; + int b:2; + char c; + } int a __attribute__ ((vector_size (16)));`![16,16i]' (alignment would depend on the machine) @@ -43329,7 +44286,7 @@ File: gcc.info, Node: Method signatures, Prev: @encode, Up: Type encoding ----------------------- This section documents the encoding of method types, which is rarely -needed to use Objective-C. You should skip it at a first reading; the +needed to use Objective-C. You should skip it at a first reading; the runtime provides functions that will work on methods and can walk through the list of parameters and interpret them for you. These functions are part of the public "API" and are the preferred way to @@ -43592,7 +44549,7 @@ the `finally' clause in Java. needed in the NeXT Objective-C runtime. * As mentioned above, the new exceptions do not support handling - types other than Objective-C objects. Furthermore, when used from + types other than Objective-C objects. Furthermore, when used from Objective-C++, the Objective-C exception model does not interoperate with C++ exceptions at this time. This means you cannot `@throw' an exception from Objective-C and `catch' it in @@ -44629,7 +45586,7 @@ can relocate the data files based on two environment variables: to strip off the hardwired absolute paths. Default value is 0. _Note:_ If GCOV_PREFIX_STRIP is set without GCOV_PREFIX is - undefined, then a relative path is made out of the hardwired + undefined, then a relative path is made out of the hardwired absolute paths. For example, if the object file `/user/build/foo.o' was built with @@ -45340,9 +46297,9 @@ where variables in base classes are used (as in the example above). these examples wrong and accept above code without an error. Those compilers do not implement two-stage name lookup correctly. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) The C++ standard just uses the term "dependent" for names that + (1) The C++ standard just uses the term "dependent" for names that depend on the type or value of template parameters. This shorter term will also be used in the rest of this section. @@ -45624,7 +46581,7 @@ do not make because we think GCC is better without them. programs run any faster. However, the rationale here is that optimization of a nonempty loop - cannot produce an empty one. This held for carefully written C + cannot produce an empty one. This held for carefully written C compiled with less powerful optimizers but is not always the case for carefully written C++ or with more powerful optimizers. Thus GCC will remove operations from loops whenever it can determine @@ -46379,7 +47336,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -46407,7 +47364,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -46480,7 +47437,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -46494,7 +47451,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -46505,7 +47462,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -46532,19 +47489,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -46557,7 +47514,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -47030,7 +47987,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -47051,7 +48008,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -47098,7 +48055,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, -replace the "with...Texts." line with this: +replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -48058,7 +49015,7 @@ GCC version 4.1: and improvements. * Thomas Fitzsimmons for lots of upgrades to the gtk+ AWT and Cairo - 2D support. Lots of imageio framework additions, lots of AWT and + 2D support. Lots of imageio framework additions, lots of AWT and Free Swing bug fixes. * Jeroen Frijters for `ClassLoader' and nio cleanups, serialization @@ -48093,7 +49050,7 @@ GCC version 4.1: * Ito Kazumitsu for `NetworkInterface' implementation and updates. * Roman Kennke for `BoxLayout', `GrayFilter' and `SplitPane', plus - bug fixes all over. Lots of Free Swing work including styled text. + bug fixes all over. Lots of Free Swing work including styled text. * Simon Kitching for `String' cleanups and optimization suggestions. @@ -48350,7 +49307,7 @@ look up both forms. * -mcpu: RX Options. (line 30) * -mpointer-size=SIZE: VMS Options. (line 20) * 8bit-idiv: i386 and x86-64 Options. - (line 818) + (line 824) * A: Preprocessor Options. (line 597) * all_load: Darwin Options. (line 110) @@ -48364,9 +49321,9 @@ look up both forms. * arch_errors_fatal: Darwin Options. (line 114) * aux-info: C Dialect Options. (line 168) * avx256-split-unaligned-load: i386 and x86-64 Options. - (line 826) + (line 832) * avx256-split-unaligned-store: i386 and x86-64 Options. - (line 826) + (line 832) * B: Directory Options. (line 46) * Bdynamic: VxWorks Options. (line 22) * bind_at_load: Darwin Options. (line 118) @@ -48418,6 +49375,7 @@ look up both forms. * F: Darwin Options. (line 31) * fabi-version: C++ Dialect Options. (line 20) +* fada-spec-parent: Overall Options. (line 369) * faggressive-loop-optimizations: Optimize Options. (line 509) * falign-functions: Optimize Options. (line 1462) * falign-jumps: Optimize Options. (line 1511) @@ -48482,8 +49440,10 @@ look up both forms. * fdollars-in-identifiers: Preprocessor Options. (line 495) * fdse: Optimize Options. (line 543) +* fdump-ada-spec: Overall Options. (line 363) * fdump-class-hierarchy: Debugging Options. (line 805) * fdump-final-insns: Debugging Options. (line 194) +* fdump-go-spec: Overall Options. (line 373) * fdump-ipa: Debugging Options. (line 813) * fdump-noaddr: Debugging Options. (line 778) * fdump-passes: Debugging Options. (line 831) @@ -48646,7 +49606,7 @@ look up both forms. * finput-charset: Preprocessor Options. (line 567) * finstrument-functions <1>: Function Attributes. - (line 946) + (line 954) * finstrument-functions: Code Gen Options. (line 375) * finstrument-functions-exclude-file-list: Code Gen Options. (line 411) * finstrument-functions-exclude-function-list: Code Gen Options. @@ -48902,7 +49862,7 @@ look up both forms. * fsingle-precision-constant: Optimize Options. (line 2052) * fsplit-ivs-in-unroller: Optimize Options. (line 1281) * fsplit-stack <1>: Function Attributes. - (line 951) + (line 959) * fsplit-stack: Code Gen Options. (line 496) * fsplit-wide-types: Optimize Options. (line 437) * fstack-check: Code Gen Options. (line 443) @@ -49004,7 +49964,7 @@ look up both forms. (line 141) * G <1>: System V Options. (line 10) * G <2>: RS/6000 and PowerPC Options. - (line 662) + (line 743) * G <3>: MIPS Options. (line 330) * G: M32R/D Options. (line 57) * g: Debugging Options. (line 10) @@ -49070,13 +50030,13 @@ look up both forms. * l: Link Options. (line 26) * lobjc: Link Options. (line 53) * m: RS/6000 and PowerPC Options. - (line 515) + (line 584) * M: Preprocessor Options. (line 185) * m1: SH Options. (line 9) * m10: PDP-11 Options. (line 29) * m128bit-long-double: i386 and x86-64 Options. - (line 336) + (line 342) * m16-bit: CRIS Options. (line 64) * m1reg-: Adapteva Epiphany Options. (line 132) @@ -49091,11 +50051,11 @@ look up both forms. (line 87) * m32 <1>: TILEPro Options. (line 13) * m32 <2>: TILE-Gx Options. (line 23) -* m32 <3>: SPARC Options. (line 245) +* m32 <3>: SPARC Options. (line 257) * m32 <4>: RS/6000 and PowerPC Options. - (line 207) + (line 276) * m32: i386 and x86-64 Options. - (line 835) + (line 841) * m32-bit: CRIS Options. (line 64) * m32bit-doubles: RX Options. (line 10) * m32r: M32R/D Options. (line 15) @@ -49103,7 +50063,7 @@ look up both forms. * m32rx: M32R/D Options. (line 12) * m340: MCore Options. (line 43) * m3dnow: i386 and x86-64 Options. - (line 565) + (line 571) * m3e: SH Options. (line 37) * m4: SH Options. (line 51) * m4-nofpu: SH Options. (line 40) @@ -49123,13 +50083,13 @@ look up both forms. * m5307: M680x0 Options. (line 164) * m5407: M680x0 Options. (line 168) * m64 <1>: TILE-Gx Options. (line 23) -* m64 <2>: SPARC Options. (line 245) +* m64 <2>: SPARC Options. (line 257) * m64 <3>: S/390 and zSeries Options. (line 87) * m64 <4>: RS/6000 and PowerPC Options. - (line 207) + (line 276) * m64: i386 and x86-64 Options. - (line 835) + (line 841) * m64bit-doubles: RX Options. (line 10) * m68000: M680x0 Options. (line 95) * m68010: M680x0 Options. (line 103) @@ -49143,65 +50103,73 @@ look up both forms. * m8-bit: CRIS Options. (line 64) * m8byte-align: V850 Options. (line 170) * m96bit-long-double: i386 and x86-64 Options. - (line 336) + (line 342) * mabi <1>: RS/6000 and PowerPC Options. - (line 542) + (line 611) * mabi <2>: i386 and x86-64 Options. - (line 715) + (line 721) * mabi: ARM Options. (line 10) * mabi=32: MIPS Options. (line 131) * mabi=64: MIPS Options. (line 131) * mabi=eabi: MIPS Options. (line 131) +* mabi=elfv1: RS/6000 and PowerPC Options. + (line 632) +* mabi=elfv2: RS/6000 and PowerPC Options. + (line 638) * mabi=gnu: MMIX Options. (line 20) * mabi=ibmlongdouble: RS/6000 and PowerPC Options. - (line 555) + (line 624) * mabi=ieeelongdouble: RS/6000 and PowerPC Options. - (line 559) + (line 628) * mabi=mmixware: MMIX Options. (line 20) * mabi=n32: MIPS Options. (line 131) * mabi=no-spe: RS/6000 and PowerPC Options. - (line 552) + (line 621) * mabi=o64: MIPS Options. (line 131) * mabi=spe: RS/6000 and PowerPC Options. - (line 547) + (line 616) * mabicalls: MIPS Options. (line 155) -* mabort-on-noreturn: ARM Options. (line 183) +* mabort-on-noreturn: ARM Options. (line 184) * mabsdiff: MeP Options. (line 7) * mabshi: PDP-11 Options. (line 55) * mac0: PDP-11 Options. (line 16) * macc-4: FRV Options. (line 113) * macc-8: FRV Options. (line 116) -* maccumulate-args: AVR Options. (line 139) +* maccumulate-args: AVR Options. (line 135) * maccumulate-outgoing-args <1>: SH Options. (line 330) * maccumulate-outgoing-args: i386 and x86-64 Options. - (line 738) + (line 744) * maddress-mode=long: i386 and x86-64 Options. - (line 878) + (line 884) * maddress-mode=short: i386 and x86-64 Options. - (line 883) + (line 889) * maddress-space-conversion: SPU Options. (line 63) * mads: RS/6000 and PowerPC Options. - (line 585) + (line 666) * maix-struct-return: RS/6000 and PowerPC Options. - (line 535) + (line 604) * maix32: RS/6000 and PowerPC Options. - (line 245) + (line 314) * maix64: RS/6000 and PowerPC Options. - (line 245) + (line 314) * malign-300: H8/300 Options. (line 41) * malign-double: i386 and x86-64 Options. - (line 320) + (line 326) * malign-int: M680x0 Options. (line 267) * malign-labels: FRV Options. (line 104) * malign-loops: M32R/D Options. (line 73) * malign-natural: RS/6000 and PowerPC Options. - (line 284) + (line 353) * malign-power: RS/6000 and PowerPC Options. - (line 284) + (line 353) * mall-opts: MeP Options. (line 11) * malloc-cc: FRV Options. (line 25) * maltivec: RS/6000 and PowerPC Options. - (line 132) + (line 134) +* maltivec=be: RS/6000 and PowerPC Options. + (line 150) +* maltivec=le: RS/6000 and PowerPC Options. + (line 160) * mam33: MN10300 Options. (line 17) * mam33-2: MN10300 Options. (line 24) * mam34: MN10300 Options. (line 27) @@ -49219,18 +50187,18 @@ look up both forms. * march <5>: HPPA Options. (line 9) * march <6>: CRIS Options. (line 10) * march <7>: C6X Options. (line 7) -* march <8>: ARM Options. (line 128) +* march <8>: ARM Options. (line 75) * march: AArch64 Options. (line 55) -* marm: ARM Options. (line 244) +* marm: ARM Options. (line 248) * mas100-syntax: RX Options. (line 76) * masm=DIALECT: i386 and x86-64 Options. - (line 275) + (line 281) * matomic-model=MODEL: SH Options. (line 144) * matomic-updates: SPU Options. (line 78) * mauto-pic: IA-64 Options. (line 50) * maverage: MeP Options. (line 16) * mavoid-indexed-addresses: RS/6000 and PowerPC Options. - (line 354) + (line 423) * max-vect-align: Adapteva Epiphany Options. (line 120) * mb: SH Options. (line 74) @@ -49242,9 +50210,9 @@ look up both forms. * mbcopy: PDP-11 Options. (line 36) * mbcopy-builtin: PDP-11 Options. (line 32) * mbig: RS/6000 and PowerPC Options. - (line 434) + (line 503) * mbig-endian <1>: RS/6000 and PowerPC Options. - (line 434) + (line 503) * mbig-endian <2>: MicroBlaze Options. (line 57) * mbig-endian <3>: MCore Options. (line 39) * mbig-endian <4>: IA-64 Options. (line 9) @@ -49257,16 +50225,16 @@ look up both forms. * mbigtable: SH Options. (line 89) * mbionic: GNU/Linux Options. (line 17) * mbit-align: RS/6000 and PowerPC Options. - (line 386) + (line 455) * mbit-ops: CR16 Options. (line 25) * mbitfield: M680x0 Options. (line 235) * mbitops <1>: SH Options. (line 93) * mbitops: MeP Options. (line 26) * mblock-move-inline-limit: RS/6000 and PowerPC Options. - (line 656) + (line 737) * mbranch-cheap: PDP-11 Options. (line 65) * mbranch-cost <1>: MIPS Options. (line 635) -* mbranch-cost <2>: AVR Options. (line 154) +* mbranch-cost <2>: AVR Options. (line 150) * mbranch-cost: Adapteva Epiphany Options. (line 18) * mbranch-cost=NUM: SH Options. (line 396) @@ -49276,7 +50244,7 @@ look up both forms. * mbranch-likely: MIPS Options. (line 642) * mbranch-predict: MMIX Options. (line 49) * mbss-plt: RS/6000 and PowerPC Options. - (line 155) + (line 187) * mbuild-constants: DEC Alpha Options. (line 141) * mbwx: DEC Alpha Options. (line 163) * mc68000: M680x0 Options. (line 95) @@ -49284,50 +50252,50 @@ look up both forms. * mc=: MeP Options. (line 31) * mcache-size: SPU Options. (line 70) * mcall-eabi: RS/6000 and PowerPC Options. - (line 509) + (line 578) * mcall-freebsd: RS/6000 and PowerPC Options. - (line 523) + (line 592) * mcall-linux: RS/6000 and PowerPC Options. - (line 519) + (line 588) * mcall-netbsd: RS/6000 and PowerPC Options. - (line 527) -* mcall-prologues: AVR Options. (line 159) + (line 596) +* mcall-prologues: AVR Options. (line 155) * mcall-sysv: RS/6000 and PowerPC Options. - (line 501) + (line 570) * mcall-sysv-eabi: RS/6000 and PowerPC Options. - (line 509) + (line 578) * mcall-sysv-noeabi: RS/6000 and PowerPC Options. - (line 512) -* mcallee-super-interworking: ARM Options. (line 262) -* mcaller-super-interworking: ARM Options. (line 269) + (line 581) +* mcallee-super-interworking: ARM Options. (line 266) +* mcaller-super-interworking: ARM Options. (line 273) * mcallgraph-data: MCore Options. (line 31) -* mcbcond: SPARC Options. (line 216) +* mcbcond: SPARC Options. (line 224) * mcbranchdi: SH Options. (line 411) * mcc-init: CRIS Options. (line 41) * mcfv4e: M680x0 Options. (line 172) * mcheck-zero-division: MIPS Options. (line 441) * mcix: DEC Alpha Options. (line 163) * mcld: i386 and x86-64 Options. - (line 588) + (line 594) * mclip: MeP Options. (line 35) -* mcmodel: SPARC Options. (line 250) +* mcmodel: SPARC Options. (line 262) * mcmodel=kernel: i386 and x86-64 Options. - (line 862) + (line 868) * mcmodel=large <1>: TILE-Gx Options. (line 14) * mcmodel=large <2>: RS/6000 and PowerPC Options. - (line 126) + (line 128) * mcmodel=large <3>: i386 and x86-64 Options. - (line 874) + (line 880) * mcmodel=large: AArch64 Options. (line 33) * mcmodel=medium <1>: RS/6000 and PowerPC Options. - (line 122) + (line 124) * mcmodel=medium: i386 and x86-64 Options. - (line 867) + (line 873) * mcmodel=small <1>: TILE-Gx Options. (line 9) * mcmodel=small <2>: RS/6000 and PowerPC Options. - (line 118) + (line 120) * mcmodel=small <3>: i386 and x86-64 Options. - (line 856) + (line 862) * mcmodel=small: AArch64 Options. (line 27) * mcmodel=tiny: AArch64 Options. (line 20) * mcmove: Adapteva Epiphany Options. @@ -49336,6 +50304,8 @@ look up both forms. (line 27) * mcmpeqdi: SH Options. (line 414) * mcode-readable: MIPS Options. (line 401) +* mcompat-align-parm: RS/6000 and PowerPC Options. + (line 895) * mcond-exec: FRV Options. (line 152) * mcond-move: FRV Options. (line 128) * mconfig=: MeP Options. (line 39) @@ -49351,17 +50321,17 @@ look up both forms. * mcoreb: Blackfin Options. (line 164) * mcpu <1>: TILEPro Options. (line 9) * mcpu <2>: TILE-Gx Options. (line 18) -* mcpu <3>: SPARC Options. (line 94) +* mcpu <3>: SPARC Options. (line 102) * mcpu <4>: RS/6000 and PowerPC Options. (line 69) * mcpu <5>: picoChip Options. (line 9) * mcpu <6>: M680x0 Options. (line 28) * mcpu <7>: i386 and x86-64 Options. - (line 223) + (line 229) * mcpu <8>: FRV Options. (line 212) * mcpu <9>: DEC Alpha Options. (line 215) * mcpu <10>: CRIS Options. (line 10) -* mcpu <11>: ARM Options. (line 75) +* mcpu <11>: ARM Options. (line 124) * mcpu: AArch64 Options. (line 69) * mcpu32: M680x0 Options. (line 138) * mcpu= <1>: MicroBlaze Options. (line 20) @@ -49370,10 +50340,12 @@ look up both forms. * mcr16c: CR16 Options. (line 14) * mcr16cplus: CR16 Options. (line 14) * mcrc32: i386 and x86-64 Options. - (line 635) + (line 641) +* mcrypto: RS/6000 and PowerPC Options. + (line 222) * mcsync-anomaly: Blackfin Options. (line 60) * mcx16: i386 and x86-64 Options. - (line 612) + (line 618) * MD: Preprocessor Options. (line 274) * mdalign: SH Options. (line 80) @@ -49385,6 +50357,8 @@ look up both forms. * mdebug: M32R/D Options. (line 69) * mdebug-main=PREFIX: VMS Options. (line 13) * mdec-asm: PDP-11 Options. (line 72) +* mdirect-move: RS/6000 and PowerPC Options. + (line 228) * mdisable-callt: V850 Options. (line 92) * mdisable-fpregs: HPPA Options. (line 33) * mdisable-indexing: HPPA Options. (line 39) @@ -49399,11 +50373,11 @@ look up both forms. * mdll: i386 and x86-64 Windows Options. (line 16) * mdlmzb: RS/6000 and PowerPC Options. - (line 379) + (line 448) * mdmx: MIPS Options. (line 290) * mdouble: FRV Options. (line 38) * mdouble-float <1>: RS/6000 and PowerPC Options. - (line 302) + (line 371) * mdouble-float: MIPS Options. (line 248) * mdsp: MIPS Options. (line 267) * mdspr2: MIPS Options. (line 273) @@ -49411,11 +50385,11 @@ look up both forms. * mdwarf2-asm: IA-64 Options. (line 94) * mdword: FRV Options. (line 32) * mdynamic-no-pic: RS/6000 and PowerPC Options. - (line 439) + (line 508) * mea32: SPU Options. (line 55) * mea64: SPU Options. (line 55) * meabi: RS/6000 and PowerPC Options. - (line 604) + (line 685) * mearly-stop-bits: IA-64 Options. (line 100) * meb <1>: Score Options. (line 9) * meb <2>: Moxie Options. (line 7) @@ -49426,7 +50400,7 @@ look up both forms. * melf <1>: MMIX Options. (line 44) * melf: CRIS Options. (line 87) * memb: RS/6000 and PowerPC Options. - (line 599) + (line 680) * membedded-data: MIPS Options. (line 388) * memregs=: M32C Options. (line 21) * mep: V850 Options. (line 16) @@ -49444,19 +50418,20 @@ look up both forms. (line 220) * mfast-fp: Blackfin Options. (line 133) * mfast-indirect-calls: HPPA Options. (line 51) -* mfaster-structs: SPARC Options. (line 84) +* mfaster-structs: SPARC Options. (line 92) * mfdpic: FRV Options. (line 56) * mfentry: i386 and x86-64 Options. - (line 811) + (line 817) * mfix: DEC Alpha Options. (line 163) * mfix-24k: MIPS Options. (line 500) * mfix-and-continue: Darwin Options. (line 104) -* mfix-at697f: SPARC Options. (line 236) -* mfix-cortex-m3-ldrd: ARM Options. (line 302) +* mfix-at697f: SPARC Options. (line 244) +* mfix-cortex-m3-ldrd: ARM Options. (line 306) * mfix-r10000: MIPS Options. (line 527) * mfix-r4000: MIPS Options. (line 506) * mfix-r4400: MIPS Options. (line 520) * mfix-sb1: MIPS Options. (line 559) +* mfix-ut699: SPARC Options. (line 249) * mfix-vr4120: MIPS Options. (line 538) * mfix-vr4130: MIPS Options. (line 552) * mfixed-cc: FRV Options. (line 28) @@ -49464,11 +50439,11 @@ look up both forms. * mfixed-range <2>: SH Options. (line 343) * mfixed-range <3>: IA-64 Options. (line 105) * mfixed-range: HPPA Options. (line 58) -* mflat: SPARC Options. (line 20) +* mflat: SPARC Options. (line 22) * mflip-mips16: MIPS Options. (line 111) * mfloat-abi: ARM Options. (line 42) * mfloat-gprs: RS/6000 and PowerPC Options. - (line 190) + (line 259) * mfloat-ieee: DEC Alpha Options. (line 171) * mfloat-vax: DEC Alpha Options. (line 171) * mfloat32: PDP-11 Options. (line 52) @@ -49476,7 +50451,7 @@ look up both forms. * mflush-func: MIPS Options. (line 626) * mflush-func=NAME: M32R/D Options. (line 93) * mflush-trap=NUMBER: M32R/D Options. (line 86) -* mfmaf: SPARC Options. (line 230) +* mfmaf: SPARC Options. (line 238) * mfmovd: SH Options. (line 96) * mforce-no-pic: Xtensa Options. (line 41) * mfp-exceptions: MIPS Options. (line 653) @@ -49485,33 +50460,33 @@ look up both forms. * mfp-reg: DEC Alpha Options. (line 25) * mfp-rounding-mode: DEC Alpha Options. (line 85) * mfp-trap-mode: DEC Alpha Options. (line 63) -* mfp16-format: ARM Options. (line 163) +* mfp16-format: ARM Options. (line 164) * mfp32: MIPS Options. (line 221) * mfp64: MIPS Options. (line 224) * mfpmath <1>: i386 and x86-64 Options. - (line 226) + (line 232) * mfpmath: Optimize Options. (line 1898) * mfpr-32: FRV Options. (line 13) * mfpr-64: FRV Options. (line 16) * mfprnd: RS/6000 and PowerPC Options. (line 27) -* mfpu <1>: SPARC Options. (line 33) +* mfpu <1>: SPARC Options. (line 35) * mfpu <2>: RS/6000 and PowerPC Options. - (line 310) + (line 379) * mfpu <3>: PDP-11 Options. (line 9) -* mfpu: ARM Options. (line 143) +* mfpu: ARM Options. (line 144) * mfriz: RS/6000 and PowerPC Options. - (line 785) + (line 866) * mfsca: SH Options. (line 428) * mfsrra: SH Options. (line 437) * mfull-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mfused-madd <1>: Xtensa Options. (line 19) * mfused-madd <2>: SH Options. (line 419) * mfused-madd <3>: S/390 and zSeries Options. (line 137) * mfused-madd <4>: RS/6000 and PowerPC Options. - (line 363) + (line 432) * mfused-madd <5>: MIPS Options. (line 482) * mfused-madd: IA-64 Options. (line 88) * mg: VAX Options. (line 17) @@ -49520,7 +50495,7 @@ look up both forms. * mgas: HPPA Options. (line 74) * mgcc-abi: V850 Options. (line 148) * mgen-cell-microcode: RS/6000 and PowerPC Options. - (line 143) + (line 175) * mgeneral-regs-only: AArch64 Options. (line 13) * mgettrcost=NUMBER: SH Options. (line 360) * mghs: V850 Options. (line 127) @@ -49544,20 +50519,22 @@ look up both forms. * mhard-dfp: RS/6000 and PowerPC Options. (line 27) * mhard-float <1>: V850 Options. (line 113) -* mhard-float <2>: SPARC Options. (line 33) +* mhard-float <2>: SPARC Options. (line 35) * mhard-float <3>: S/390 and zSeries Options. (line 11) * mhard-float <4>: RS/6000 and PowerPC Options. - (line 296) + (line 365) * mhard-float <5>: MIPS Options. (line 227) * mhard-float <6>: MicroBlaze Options. (line 10) * mhard-float <7>: M680x0 Options. (line 197) * mhard-float: FRV Options. (line 19) -* mhard-quad-float: SPARC Options. (line 54) +* mhard-quad-float: SPARC Options. (line 56) * mhardlit: MCore Options. (line 10) * mhint-max-distance: SPU Options. (line 102) * mhint-max-nops: SPU Options. (line 96) * mhitachi: SH Options. (line 100) +* mhotpatch: S/390 and zSeries Options. + (line 174) * mhp-ld: HPPA Options. (line 122) * micplb: Blackfin Options. (line 178) * mid-shared-library: Blackfin Options. (line 81) @@ -49565,15 +50542,15 @@ look up both forms. * mieee: DEC Alpha Options. (line 39) * mieee-conformant: DEC Alpha Options. (line 134) * mieee-fp: i386 and x86-64 Options. - (line 281) + (line 287) * mieee-with-inexact: DEC Alpha Options. (line 52) * milp32: IA-64 Options. (line 121) * mimpure-text: Solaris 2 Options. (line 9) * mincoming-stack-boundary: i386 and x86-64 Options. - (line 486) + (line 492) * mindexed-addressing: SH Options. (line 350) * minline-all-stringops: i386 and x86-64 Options. - (line 759) + (line 765) * minline-float-divide-max-throughput: IA-64 Options. (line 58) * minline-float-divide-min-latency: IA-64 Options. (line 54) * minline-ic_invalidate: SH Options. (line 125) @@ -49584,15 +50561,15 @@ look up both forms. * minline-sqrt-max-throughput: IA-64 Options. (line 80) * minline-sqrt-min-latency: IA-64 Options. (line 76) * minline-stringops-dynamically: i386 and x86-64 Options. - (line 766) + (line 772) * minsert-sched-nops: RS/6000 and PowerPC Options. - (line 479) + (line 548) * mint-register: RX Options. (line 100) * mint16: PDP-11 Options. (line 40) * mint32 <1>: PDP-11 Options. (line 44) * mint32 <2>: H8/300 Options. (line 38) * mint32: CR16 Options. (line 22) -* mint8: AVR Options. (line 163) +* mint8: AVR Options. (line 159) * minterlink-mips16: MIPS Options. (line 118) * minvalid-symbols: SH Options. (line 386) * mio-volatile: MeP Options. (line 74) @@ -49607,7 +50584,7 @@ look up both forms. * mips64: MIPS Options. (line 96) * mips64r2: MIPS Options. (line 99) * misel: RS/6000 and PowerPC Options. - (line 161) + (line 193) * misize: SH Options. (line 137) * missue-rate=NUMBER: M32R/D Options. (line 79) * mivc2: MeP Options. (line 59) @@ -49618,7 +50595,7 @@ look up both forms. * ml: MeP Options. (line 78) * mlarge-data: DEC Alpha Options. (line 187) * mlarge-data-threshold: i386 and x86-64 Options. - (line 372) + (line 378) * mlarge-mem: SPU Options. (line 35) * mlarge-text: DEC Alpha Options. (line 205) * mleadz: MeP Options. (line 81) @@ -49629,9 +50606,9 @@ look up both forms. * mlinker-opt: HPPA Options. (line 84) * mlinux: CRIS Options. (line 91) * mlittle: RS/6000 and PowerPC Options. - (line 428) + (line 497) * mlittle-endian <1>: RS/6000 and PowerPC Options. - (line 428) + (line 497) * mlittle-endian <2>: MicroBlaze Options. (line 60) * mlittle-endian <3>: MCore Options. (line 39) * mlittle-endian <4>: IA-64 Options. (line 13) @@ -49646,7 +50623,7 @@ look up both forms. * mlong-calls <2>: MIPS Options. (line 468) * mlong-calls <3>: FRV Options. (line 99) * mlong-calls <4>: Blackfin Options. (line 121) -* mlong-calls <5>: ARM Options. (line 188) +* mlong-calls <5>: ARM Options. (line 189) * mlong-calls: Adapteva Epiphany Options. (line 55) * mlong-double-128: S/390 and zSeries Options. @@ -49654,15 +50631,15 @@ look up both forms. * mlong-double-64 <1>: S/390 and zSeries Options. (line 29) * mlong-double-64: i386 and x86-64 Options. - (line 361) + (line 367) * mlong-double-80: i386 and x86-64 Options. - (line 361) + (line 367) * mlong-jumps: V850 Options. (line 108) * mlong-load-store: HPPA Options. (line 65) * mlong32: MIPS Options. (line 313) * mlong64: MIPS Options. (line 308) * mlongcall: RS/6000 and PowerPC Options. - (line 676) + (line 757) * mlongcalls: Xtensa Options. (line 72) * mloop: V850 Options. (line 121) * mlow-64k: Blackfin Options. (line 70) @@ -49686,42 +50663,42 @@ look up both forms. * mmemcpy <1>: MIPS Options. (line 462) * mmemcpy: MicroBlaze Options. (line 13) * mmemory-latency: DEC Alpha Options. (line 268) -* mmemory-model: SPARC Options. (line 278) +* mmemory-model: SPARC Options. (line 290) * mmfcrf: RS/6000 and PowerPC Options. (line 27) * mmfpgpr: RS/6000 and PowerPC Options. (line 27) * mminimal-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mminmax: MeP Options. (line 87) * mmmx: i386 and x86-64 Options. - (line 565) + (line 571) * mmodel=large: M32R/D Options. (line 33) * mmodel=medium: M32R/D Options. (line 27) * mmodel=small: M32R/D Options. (line 18) * mmovbe: i386 and x86-64 Options. - (line 631) + (line 637) * mmt: MIPS Options. (line 301) * mmul: RL78 Options. (line 13) * mmul-bug-workaround: CRIS Options. (line 31) * mmuladd: FRV Options. (line 50) * mmulhw: RS/6000 and PowerPC Options. - (line 372) + (line 441) * mmult: MeP Options. (line 90) * mmult-bug: MN10300 Options. (line 9) * mmulti-cond-exec: FRV Options. (line 176) * mmulticore: Blackfin Options. (line 142) * mmultiple: RS/6000 and PowerPC Options. - (line 322) + (line 391) * mmvcle: S/390 and zSeries Options. (line 105) * mmvme: RS/6000 and PowerPC Options. - (line 580) + (line 661) * mn: H8/300 Options. (line 20) * mnested-cond-exec: FRV Options. (line 189) * mnhwloop: Score Options. (line 15) * mno-3dnow: i386 and x86-64 Options. - (line 565) + (line 571) * mno-4byte-functions: MCore Options. (line 27) * mno-8byte-align: V850 Options. (line 170) * mno-abicalls: MIPS Options. (line 155) @@ -49729,31 +50706,31 @@ look up both forms. * mno-ac0: PDP-11 Options. (line 20) * mno-address-space-conversion: SPU Options. (line 63) * mno-align-double: i386 and x86-64 Options. - (line 320) + (line 326) * mno-align-int: M680x0 Options. (line 267) * mno-align-loops: M32R/D Options. (line 76) * mno-align-stringops: i386 and x86-64 Options. - (line 754) + (line 760) * mno-altivec: RS/6000 and PowerPC Options. - (line 132) + (line 134) * mno-am33: MN10300 Options. (line 20) * mno-app-regs <1>: V850 Options. (line 185) * mno-app-regs: SPARC Options. (line 10) * mno-as100-syntax: RX Options. (line 76) * mno-atomic-updates: SPU Options. (line 78) * mno-avoid-indexed-addresses: RS/6000 and PowerPC Options. - (line 354) + (line 423) * mno-backchain: S/390 and zSeries Options. (line 35) * mno-base-addresses: MMIX Options. (line 54) * mno-bit-align: RS/6000 and PowerPC Options. - (line 386) + (line 455) * mno-bitfield: M680x0 Options. (line 231) * mno-branch-likely: MIPS Options. (line 642) * mno-branch-predict: MMIX Options. (line 49) * mno-bwx: DEC Alpha Options. (line 163) * mno-callgraph-data: MCore Options. (line 31) -* mno-cbcond: SPARC Options. (line 216) +* mno-cbcond: SPARC Options. (line 224) * mno-check-zero-division: MIPS Options. (line 441) * mno-cix: DEC Alpha Options. (line 163) * mno-clearbss: MicroBlaze Options. (line 16) @@ -49765,22 +50742,26 @@ look up both forms. * mno-const16: Xtensa Options. (line 10) * mno-crt0 <1>: Moxie Options. (line 14) * mno-crt0: MN10300 Options. (line 43) +* mno-crypto: RS/6000 and PowerPC Options. + (line 222) * mno-csync-anomaly: Blackfin Options. (line 66) * mno-data-align: CRIS Options. (line 55) * mno-debug: S/390 and zSeries Options. (line 112) +* mno-direct-move: RS/6000 and PowerPC Options. + (line 228) * mno-disable-callt: V850 Options. (line 92) * mno-div <1>: MCore Options. (line 15) * mno-div: M680x0 Options. (line 209) * mno-dlmzb: RS/6000 and PowerPC Options. - (line 379) + (line 448) * mno-double: FRV Options. (line 41) * mno-dsp: MIPS Options. (line 267) * mno-dspr2: MIPS Options. (line 273) * mno-dwarf2-asm: IA-64 Options. (line 94) * mno-dword: FRV Options. (line 35) * mno-eabi: RS/6000 and PowerPC Options. - (line 604) + (line 685) * mno-early-stop-bits: IA-64 Options. (line 100) * mno-eflags: FRV Options. (line 125) * mno-embedded-data: MIPS Options. (line 388) @@ -49791,28 +50772,28 @@ look up both forms. * mno-exr: H8/300 Options. (line 33) * mno-extern-sdata: MIPS Options. (line 350) * mno-fancy-math-387: i386 and x86-64 Options. - (line 309) -* mno-faster-structs: SPARC Options. (line 84) + (line 315) +* mno-faster-structs: SPARC Options. (line 92) * mno-fix: DEC Alpha Options. (line 163) * mno-fix-24k: MIPS Options. (line 500) * mno-fix-r10000: MIPS Options. (line 527) * mno-fix-r4000: MIPS Options. (line 506) * mno-fix-r4400: MIPS Options. (line 520) -* mno-flat: SPARC Options. (line 20) +* mno-flat: SPARC Options. (line 22) * mno-float: MIPS Options. (line 234) * mno-float32: PDP-11 Options. (line 48) * mno-float64: PDP-11 Options. (line 52) * mno-flush-func: M32R/D Options. (line 98) * mno-flush-trap: M32R/D Options. (line 90) -* mno-fmaf: SPARC Options. (line 230) +* mno-fmaf: SPARC Options. (line 238) * mno-fp-in-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mno-fp-regs: DEC Alpha Options. (line 25) * mno-fp-ret-in-387: i386 and x86-64 Options. - (line 299) + (line 305) * mno-fprnd: RS/6000 and PowerPC Options. (line 27) -* mno-fpu: SPARC Options. (line 38) +* mno-fpu: SPARC Options. (line 40) * mno-fsca: SH Options. (line 428) * mno-fsrra: SH Options. (line 437) * mno-fused-madd <1>: Xtensa Options. (line 19) @@ -49820,7 +50801,7 @@ look up both forms. * mno-fused-madd <3>: S/390 and zSeries Options. (line 137) * mno-fused-madd <4>: RS/6000 and PowerPC Options. - (line 363) + (line 432) * mno-fused-madd <5>: MIPS Options. (line 482) * mno-fused-madd: IA-64 Options. (line 88) * mno-gnu-as: IA-64 Options. (line 18) @@ -49834,16 +50815,16 @@ look up both forms. * mno-hardlit: MCore Options. (line 10) * mno-id-shared-library: Blackfin Options. (line 88) * mno-ieee-fp: i386 and x86-64 Options. - (line 281) + (line 287) * mno-inline-float-divide: IA-64 Options. (line 62) * mno-inline-int-divide: IA-64 Options. (line 73) * mno-inline-sqrt: IA-64 Options. (line 84) * mno-int16: PDP-11 Options. (line 44) * mno-int32: PDP-11 Options. (line 40) * mno-interlink-mips16: MIPS Options. (line 118) -* mno-interrupts: AVR Options. (line 169) +* mno-interrupts: AVR Options. (line 165) * mno-isel: RS/6000 and PowerPC Options. - (line 161) + (line 193) * mno-knuthdiv: MMIX Options. (line 33) * mno-leaf-id-shared-library: Blackfin Options. (line 98) * mno-libfuncs: MMIX Options. (line 10) @@ -49853,10 +50834,10 @@ look up both forms. * mno-long-calls <2>: MIPS Options. (line 468) * mno-long-calls <3>: HPPA Options. (line 135) * mno-long-calls <4>: Blackfin Options. (line 121) -* mno-long-calls: ARM Options. (line 188) +* mno-long-calls: ARM Options. (line 189) * mno-long-jumps: V850 Options. (line 108) * mno-longcall: RS/6000 and PowerPC Options. - (line 676) + (line 757) * mno-longcalls: Xtensa Options. (line 72) * mno-low-64k: Blackfin Options. (line 74) * mno-lsim <1>: MCore Options. (line 46) @@ -49875,16 +50856,16 @@ look up both forms. * mno-mips16: MIPS Options. (line 103) * mno-mips3d: MIPS Options. (line 296) * mno-mmx: i386 and x86-64 Options. - (line 565) + (line 571) * mno-mt: MIPS Options. (line 301) * mno-mul-bug-workaround: CRIS Options. (line 31) * mno-muladd: FRV Options. (line 53) * mno-mulhw: RS/6000 and PowerPC Options. - (line 372) + (line 441) * mno-mult-bug: MN10300 Options. (line 13) * mno-multi-cond-exec: FRV Options. (line 183) * mno-multiple: RS/6000 and PowerPC Options. - (line 322) + (line 391) * mno-mvcle: S/390 and zSeries Options. (line 105) * mno-nested-cond-exec: FRV Options. (line 195) @@ -49895,12 +50876,12 @@ look up both forms. * mno-packed-stack: S/390 and zSeries Options. (line 54) * mno-paired: RS/6000 and PowerPC Options. - (line 175) + (line 207) * mno-paired-single: MIPS Options. (line 284) * mno-pic: IA-64 Options. (line 26) * mno-pid: RX Options. (line 117) * mno-plt: MIPS Options. (line 182) -* mno-popc: SPARC Options. (line 223) +* mno-popc: SPARC Options. (line 231) * mno-popcntb: RS/6000 and PowerPC Options. (line 27) * mno-popcntd: RS/6000 and PowerPC Options. @@ -49909,6 +50890,10 @@ look up both forms. (line 110) * mno-postmodify: Adapteva Epiphany Options. (line 110) +* mno-power8-fusion: RS/6000 and PowerPC Options. + (line 234) +* mno-power8-vector: RS/6000 and PowerPC Options. + (line 240) * mno-powerpc-gfxopt: RS/6000 and PowerPC Options. (line 27) * mno-powerpc-gpopt: RS/6000 and PowerPC Options. @@ -49918,20 +50903,24 @@ look up both forms. * mno-prolog-function: V850 Options. (line 23) * mno-prologue-epilogue: CRIS Options. (line 71) * mno-prototype: RS/6000 and PowerPC Options. - (line 564) + (line 645) * mno-push-args: i386 and x86-64 Options. - (line 731) + (line 737) +* mno-quad-memory: RS/6000 and PowerPC Options. + (line 247) +* mno-quad-memory-atomic: RS/6000 and PowerPC Options. + (line 253) * mno-red-zone: i386 and x86-64 Options. - (line 848) + (line 854) * mno-register-names: IA-64 Options. (line 37) * mno-regnames: RS/6000 and PowerPC Options. - (line 670) + (line 751) * mno-relax: V850 Options. (line 103) * mno-relax-immediate: MCore Options. (line 19) * mno-relocatable: RS/6000 and PowerPC Options. - (line 402) + (line 471) * mno-relocatable-lib: RS/6000 and PowerPC Options. - (line 413) + (line 482) * mno-round-nearest: Adapteva Epiphany Options. (line 51) * mno-rtd: M680x0 Options. (line 262) @@ -49947,7 +50936,7 @@ look up both forms. * mno-sched-prefer-non-data-spec-insns: IA-64 Options. (line 168) * mno-sched-prolog: ARM Options. (line 33) * mno-sdata <1>: RS/6000 and PowerPC Options. - (line 651) + (line 732) * mno-sdata: IA-64 Options. (line 42) * mno-sep-data: Blackfin Options. (line 116) * mno-serialize-volatile: Xtensa Options. (line 35) @@ -49964,53 +50953,54 @@ look up both forms. * mno-soft-float: DEC Alpha Options. (line 10) * mno-space-regs: HPPA Options. (line 44) * mno-spe: RS/6000 and PowerPC Options. - (line 170) + (line 202) * mno-specld-anomaly: Blackfin Options. (line 56) * mno-split-addresses: MIPS Options. (line 426) * mno-sse: i386 and x86-64 Options. - (line 565) + (line 571) * mno-stack-align: CRIS Options. (line 55) -* mno-stack-bias: SPARC Options. (line 302) +* mno-stack-bias: SPARC Options. (line 314) * mno-strict-align <1>: RS/6000 and PowerPC Options. - (line 397) + (line 466) * mno-strict-align: M680x0 Options. (line 287) * mno-string: RS/6000 and PowerPC Options. - (line 333) + (line 402) * mno-sum-in-toc: RS/6000 and PowerPC Options. - (line 218) + (line 287) * mno-sym32: MIPS Options. (line 323) * mno-target-align: Xtensa Options. (line 59) * mno-text-section-literals: Xtensa Options. (line 47) * mno-tls-markers: RS/6000 and PowerPC Options. - (line 709) + (line 790) * mno-toc: RS/6000 and PowerPC Options. - (line 422) + (line 491) * mno-toplevel-symbols: MMIX Options. (line 40) * mno-tpf-trace: S/390 and zSeries Options. (line 131) -* mno-unaligned-access: ARM Options. (line 309) -* mno-unaligned-doubles: SPARC Options. (line 72) +* mno-unaligned-access: ARM Options. (line 313) +* mno-unaligned-doubles: SPARC Options. (line 74) * mno-uninit-const-in-rodata: MIPS Options. (line 396) * mno-update: RS/6000 and PowerPC Options. - (line 344) -* mno-v8plus: SPARC Options. (line 187) + (line 413) +* mno-user-mode: SPARC Options. (line 86) +* mno-v8plus: SPARC Options. (line 195) * mno-vect-double: Adapteva Epiphany Options. (line 116) -* mno-vis: SPARC Options. (line 194) -* mno-vis2: SPARC Options. (line 200) -* mno-vis3: SPARC Options. (line 208) +* mno-vis: SPARC Options. (line 202) +* mno-vis2: SPARC Options. (line 208) +* mno-vis3: SPARC Options. (line 216) * mno-vliw-branch: FRV Options. (line 170) * mno-volatile-asm-stop: IA-64 Options. (line 32) * mno-vrsave: RS/6000 and PowerPC Options. - (line 140) + (line 172) * mno-vsx: RS/6000 and PowerPC Options. - (line 184) + (line 216) * mno-warn-multiple-fast-interrupts: RX Options. (line 143) * mno-wide-bitfields: MCore Options. (line 23) * mno-xgot <1>: MIPS Options. (line 192) * mno-xgot: M680x0 Options. (line 319) * mno-xl-compat: RS/6000 and PowerPC Options. - (line 253) + (line 322) * mno-zdcbranch: SH Options. (line 403) * mno-zero-extend: MMIX Options. (line 27) * mnobitfield: M680x0 Options. (line 231) @@ -50025,7 +51015,7 @@ look up both forms. * mnosplit-lohi: Adapteva Epiphany Options. (line 110) * momit-leaf-frame-pointer <1>: i386 and x86-64 Options. - (line 788) + (line 794) * momit-leaf-frame-pointer <2>: Blackfin Options. (line 44) * momit-leaf-frame-pointer: AArch64 Options. (line 43) * mone-byte-bool: Darwin Options. (line 90) @@ -50040,32 +51030,36 @@ look up both forms. (line 54) * mpadstruct: SH Options. (line 140) * mpaired: RS/6000 and PowerPC Options. - (line 175) + (line 207) * mpaired-single: MIPS Options. (line 284) * mpc32: i386 and x86-64 Options. - (line 435) + (line 441) * mpc64: i386 and x86-64 Options. - (line 435) + (line 441) * mpc80: i386 and x86-64 Options. - (line 435) + (line 441) * mpcrel: M680x0 Options. (line 279) * mpdebug: CRIS Options. (line 35) * mpe: RS/6000 and PowerPC Options. - (line 273) + (line 342) * mpe-aligned-commons: i386 and x86-64 Windows Options. (line 59) -* mpic-register: ARM Options. (line 218) +* mpic-register: ARM Options. (line 219) * mpid: RX Options. (line 117) * mplt: MIPS Options. (line 182) * mpointers-to-nested-functions: RS/6000 and PowerPC Options. - (line 793) -* mpoke-function-name: ARM Options. (line 222) -* mpopc: SPARC Options. (line 223) + (line 874) +* mpoke-function-name: ARM Options. (line 226) +* mpopc: SPARC Options. (line 231) * mpopcntb: RS/6000 and PowerPC Options. (line 27) * mpopcntd: RS/6000 and PowerPC Options. (line 27) * mportable-runtime: HPPA Options. (line 70) +* mpower8-fusion: RS/6000 and PowerPC Options. + (line 234) +* mpower8-vector: RS/6000 and PowerPC Options. + (line 240) * mpowerpc-gfxopt: RS/6000 and PowerPC Options. (line 27) * mpowerpc-gpopt: RS/6000 and PowerPC Options. @@ -50073,52 +51067,56 @@ look up both forms. * mpowerpc64: RS/6000 and PowerPC Options. (line 27) * mprefer-avx128: i386 and x86-64 Options. - (line 608) + (line 614) * mprefer-short-insn-regs: Adapteva Epiphany Options. (line 13) * mprefergot: SH Options. (line 225) * mpreferred-stack-boundary: i386 and x86-64 Options. - (line 465) + (line 471) * mpretend-cmove: SH Options. (line 446) * mprioritize-restricted-insns: RS/6000 and PowerPC Options. - (line 451) + (line 520) * mprolog-function: V850 Options. (line 23) * mprologue-epilogue: CRIS Options. (line 71) * mprototype: RS/6000 and PowerPC Options. - (line 564) + (line 645) * mpt-fixed: SH Options. (line 364) * mpush-args: i386 and x86-64 Options. - (line 731) + (line 737) * MQ: Preprocessor Options. (line 265) +* mquad-memory: RS/6000 and PowerPC Options. + (line 247) +* mquad-memory-atomic: RS/6000 and PowerPC Options. + (line 253) * mr10k-cache-barrier: MIPS Options. (line 564) * mrecip <1>: RS/6000 and PowerPC Options. - (line 721) + (line 802) * mrecip: i386 and x86-64 Options. - (line 641) + (line 647) * mrecip-precision: RS/6000 and PowerPC Options. - (line 757) + (line 838) * mrecip=opt <1>: RS/6000 and PowerPC Options. - (line 734) + (line 815) * mrecip=opt: i386 and x86-64 Options. - (line 663) + (line 669) * mregister-names: IA-64 Options. (line 37) * mregnames: RS/6000 and PowerPC Options. - (line 670) + (line 751) * mregparm: i386 and x86-64 Options. - (line 402) + (line 408) * mrelax <1>: V850 Options. (line 103) * mrelax <2>: SH Options. (line 85) * mrelax <3>: RX Options. (line 95) * mrelax <4>: MN10300 Options. (line 46) * mrelax <5>: H8/300 Options. (line 9) -* mrelax: AVR Options. (line 173) +* mrelax: AVR Options. (line 169) * mrelax-immediate: MCore Options. (line 19) * mrelax-pic-calls: MIPS Options. (line 689) * mrelocatable: RS/6000 and PowerPC Options. - (line 402) + (line 471) * mrelocatable-lib: RS/6000 and PowerPC Options. - (line 413) + (line 482) * mrepeat: MeP Options. (line 96) * mreturn-pointer-on-d0: MN10300 Options. (line 36) * mrh850-abi: V850 Options. (line 127) @@ -50126,7 +51124,7 @@ look up both forms. (line 177) * mrtd <2>: M680x0 Options. (line 240) * mrtd: i386 and x86-64 Options. - (line 378) + (line 384) * mrtp: VxWorks Options. (line 11) * ms <1>: MeP Options. (line 100) * ms: H8/300 Options. (line 17) @@ -50134,11 +51132,11 @@ look up both forms. * msafe-dma: SPU Options. (line 17) * msafe-hints: SPU Options. (line 107) * msahf: i386 and x86-64 Options. - (line 621) + (line 627) * msatur: MeP Options. (line 105) * msave-acc-in-interrupts: RX Options. (line 109) * msave-toc-indirect: RS/6000 and PowerPC Options. - (line 805) + (line 886) * mscc: FRV Options. (line 140) * msched-ar-data-spec: IA-64 Options. (line 134) * msched-ar-in-data-spec: IA-64 Options. (line 155) @@ -50146,7 +51144,7 @@ look up both forms. * msched-br-in-data-spec: IA-64 Options. (line 148) * msched-control-spec: IA-64 Options. (line 140) * msched-costly-dep: RS/6000 and PowerPC Options. - (line 458) + (line 527) * msched-count-spec-in-critical-path: IA-64 Options. (line 182) * msched-fp-mem-deps-zero-cost: IA-64 Options. (line 198) * msched-in-control-spec: IA-64 Options. (line 162) @@ -50163,28 +51161,28 @@ look up both forms. * mscore7d: Score Options. (line 34) * msda: V850 Options. (line 40) * msdata <1>: RS/6000 and PowerPC Options. - (line 638) + (line 719) * msdata: IA-64 Options. (line 42) * msdata=all: C6X Options. (line 30) * msdata=data: RS/6000 and PowerPC Options. - (line 643) + (line 724) * msdata=default <1>: RS/6000 and PowerPC Options. - (line 638) + (line 719) * msdata=default: C6X Options. (line 22) * msdata=eabi: RS/6000 and PowerPC Options. - (line 618) + (line 699) * msdata=none <1>: RS/6000 and PowerPC Options. - (line 651) + (line 732) * msdata=none <2>: M32R/D Options. (line 40) * msdata=none: C6X Options. (line 35) * msdata=sdata: M32R/D Options. (line 49) * msdata=sysv: RS/6000 and PowerPC Options. - (line 629) + (line 710) * msdata=use: M32R/D Options. (line 53) * msdram <1>: MeP Options. (line 110) * msdram: Blackfin Options. (line 172) * msecure-plt: RS/6000 and PowerPC Options. - (line 150) + (line 182) * msel-sched-dont-check-control-spec: IA-64 Options. (line 203) * msep-data: Blackfin Options. (line 110) * mserialize-volatile: Xtensa Options. (line 35) @@ -50195,7 +51193,7 @@ look up both forms. * msim <1>: Xstormy16 Options. (line 9) * msim <2>: RX Options. (line 71) * msim <3>: RS/6000 and PowerPC Options. - (line 574) + (line 655) * msim <4>: RL78 Options. (line 7) * msim <5>: MeP Options. (line 114) * msim <6>: M32C Options. (line 13) @@ -50204,14 +51202,14 @@ look up both forms. * msim: Blackfin Options. (line 37) * msimnovec: MeP Options. (line 117) * msimple-fpu: RS/6000 and PowerPC Options. - (line 306) + (line 375) * msingle-exit: MMIX Options. (line 66) * msingle-float <1>: RS/6000 and PowerPC Options. - (line 302) + (line 371) * msingle-float: MIPS Options. (line 244) * msingle-pic-base <1>: RS/6000 and PowerPC Options. - (line 445) -* msingle-pic-base: ARM Options. (line 212) + (line 514) +* msingle-pic-base: ARM Options. (line 213) * msio: HPPA Options. (line 104) * mslow-bytes: MCore Options. (line 35) * msmall-data: DEC Alpha Options. (line 187) @@ -50226,38 +51224,38 @@ look up both forms. (line 67) * msmartmips: MIPS Options. (line 280) * msoft-float <1>: V850 Options. (line 113) -* msoft-float <2>: SPARC Options. (line 38) +* msoft-float <2>: SPARC Options. (line 40) * msoft-float <3>: S/390 and zSeries Options. (line 11) * msoft-float <4>: RS/6000 and PowerPC Options. - (line 296) + (line 365) * msoft-float <5>: PDP-11 Options. (line 13) * msoft-float <6>: MIPS Options. (line 230) * msoft-float <7>: MicroBlaze Options. (line 7) * msoft-float <8>: M680x0 Options. (line 203) * msoft-float <9>: i386 and x86-64 Options. - (line 286) + (line 292) * msoft-float <10>: HPPA Options. (line 90) * msoft-float <11>: FRV Options. (line 22) * msoft-float: DEC Alpha Options. (line 10) -* msoft-quad-float: SPARC Options. (line 58) -* msp8: AVR Options. (line 187) +* msoft-quad-float: SPARC Options. (line 60) +* msp8: AVR Options. (line 183) * mspace <1>: V850 Options. (line 30) * mspace: SH Options. (line 222) * mspe: RS/6000 and PowerPC Options. - (line 170) + (line 202) * mspecld-anomaly: Blackfin Options. (line 51) * msplit-addresses: MIPS Options. (line 426) * msplit-vecmove-early: Adapteva Epiphany Options. (line 127) * msse: i386 and x86-64 Options. - (line 565) + (line 571) * msse2avx: i386 and x86-64 Options. - (line 806) + (line 812) * msseregparm: i386 and x86-64 Options. - (line 413) + (line 419) * mstack-align: CRIS Options. (line 55) -* mstack-bias: SPARC Options. (line 302) +* mstack-bias: SPARC Options. (line 314) * mstack-check-l1: Blackfin Options. (line 77) * mstack-guard: S/390 and zSeries Options. (line 156) @@ -50267,20 +51265,20 @@ look up both forms. * mstack-size: S/390 and zSeries Options. (line 156) * mstackrealign: i386 and x86-64 Options. - (line 456) + (line 462) * mstdmain: SPU Options. (line 40) * mstrict-align <1>: RS/6000 and PowerPC Options. - (line 397) + (line 466) * mstrict-align <2>: M680x0 Options. (line 287) * mstrict-align: AArch64 Options. (line 38) -* mstrict-X: AVR Options. (line 200) +* mstrict-X: AVR Options. (line 196) * mstring: RS/6000 and PowerPC Options. - (line 333) + (line 402) * mstringop-strategy=ALG: i386 and x86-64 Options. - (line 770) -* mstructure-size-boundary: ARM Options. (line 169) + (line 776) +* mstructure-size-boundary: ARM Options. (line 170) * msvr4-struct-return: RS/6000 and PowerPC Options. - (line 538) + (line 607) * msym32: MIPS Options. (line 323) * msynci: MIPS Options. (line 674) * MT: Preprocessor Options. @@ -50293,47 +51291,47 @@ look up both forms. * mthread: i386 and x86-64 Windows Options. (line 26) * mthreads: i386 and x86-64 Options. - (line 746) -* mthumb: ARM Options. (line 244) + (line 752) +* mthumb: ARM Options. (line 248) * mthumb-interwork: ARM Options. (line 25) -* mtiny-stack: AVR Options. (line 214) +* mtiny-stack: AVR Options. (line 210) * mtiny=: MeP Options. (line 125) * mtls: FRV Options. (line 75) * mTLS: FRV Options. (line 72) * mtls-dialect <1>: i386 and x86-64 Options. - (line 724) -* mtls-dialect: ARM Options. (line 285) + (line 730) +* mtls-dialect: ARM Options. (line 289) * mtls-dialect=desc: AArch64 Options. (line 47) * mtls-dialect=traditional: AArch64 Options. (line 51) * mtls-direct-seg-refs: i386 and x86-64 Options. - (line 796) + (line 802) * mtls-markers: RS/6000 and PowerPC Options. - (line 709) + (line 790) * mtls-size: IA-64 Options. (line 112) * mtoc: RS/6000 and PowerPC Options. - (line 422) + (line 491) * mtomcat-stats: FRV Options. (line 209) * mtoplevel-symbols: MMIX Options. (line 40) -* mtp: ARM Options. (line 277) -* mtpcs-frame: ARM Options. (line 250) -* mtpcs-leaf-frame: ARM Options. (line 256) +* mtp: ARM Options. (line 281) +* mtpcs-frame: ARM Options. (line 254) +* mtpcs-leaf-frame: ARM Options. (line 260) * mtpf-trace: S/390 and zSeries Options. (line 131) * mtrap-precision: DEC Alpha Options. (line 109) -* mtune <1>: SPARC Options. (line 173) +* mtune <1>: SPARC Options. (line 181) * mtune <2>: S/390 and zSeries Options. (line 124) * mtune <3>: RS/6000 and PowerPC Options. - (line 110) + (line 112) * mtune <4>: MN10300 Options. (line 30) * mtune <5>: MIPS Options. (line 63) * mtune <6>: M680x0 Options. (line 70) * mtune <7>: IA-64 Options. (line 116) * mtune <8>: i386 and x86-64 Options. - (line 189) + (line 195) * mtune <9>: DEC Alpha Options. (line 259) * mtune <10>: CRIS Options. (line 16) -* mtune <11>: ARM Options. (line 105) +* mtune <11>: ARM Options. (line 90) * mtune: AArch64 Options. (line 82) * muclibc: GNU/Linux Options. (line 13) * muls: Score Options. (line 18) @@ -50343,8 +51341,8 @@ look up both forms. * multiply-enabled: LM32 Options. (line 15) * multiply_defined: Darwin Options. (line 196) * multiply_defined_unused: Darwin Options. (line 196) -* munaligned-access: ARM Options. (line 309) -* munaligned-doubles: SPARC Options. (line 72) +* munaligned-access: ARM Options. (line 313) +* munaligned-doubles: SPARC Options. (line 74) * municode: i386 and x86-64 Windows Options. (line 30) * muninit-const-in-rodata: MIPS Options. (line 396) @@ -50352,8 +51350,9 @@ look up both forms. * munix-asm: PDP-11 Options. (line 68) * munsafe-dma: SPU Options. (line 17) * mupdate: RS/6000 and PowerPC Options. - (line 344) + (line 413) * muser-enabled: LM32 Options. (line 21) +* muser-mode: SPARC Options. (line 86) * musermode: SH Options. (line 230) * mv850: V850 Options. (line 49) * mv850e: V850 Options. (line 79) @@ -50363,30 +51362,30 @@ look up both forms. * mv850e2v4: V850 Options. (line 57) * mv850e3v5: V850 Options. (line 52) * mv850es: V850 Options. (line 75) -* mv8plus: SPARC Options. (line 187) +* mv8plus: SPARC Options. (line 195) * mveclibabi <1>: RS/6000 and PowerPC Options. - (line 766) + (line 847) * mveclibabi: i386 and x86-64 Options. - (line 692) + (line 698) * mvect8-ret-in-mem: i386 and x86-64 Options. - (line 423) -* mvis: SPARC Options. (line 194) -* mvis2: SPARC Options. (line 200) -* mvis3: SPARC Options. (line 208) + (line 429) +* mvis: SPARC Options. (line 202) +* mvis2: SPARC Options. (line 208) +* mvis3: SPARC Options. (line 216) * mvliw-branch: FRV Options. (line 164) * mvms-return-codes: VMS Options. (line 9) * mvolatile-asm-stop: IA-64 Options. (line 32) * mvr4130-align: MIPS Options. (line 663) * mvrsave: RS/6000 and PowerPC Options. - (line 140) + (line 172) * mvsx: RS/6000 and PowerPC Options. - (line 184) + (line 216) * mvxworks: RS/6000 and PowerPC Options. - (line 595) + (line 676) * mvzeroupper: i386 and x86-64 Options. - (line 602) + (line 608) * mwarn-cell-microcode: RS/6000 and PowerPC Options. - (line 146) + (line 178) * mwarn-dynamicstack: S/390 and zSeries Options. (line 150) * mwarn-framesize: S/390 and zSeries Options. @@ -50398,17 +51397,17 @@ look up both forms. (line 35) * mwindows: i386 and x86-64 Windows Options. (line 41) -* mword-relocations: ARM Options. (line 296) +* mword-relocations: ARM Options. (line 300) * mwords-little-endian: ARM Options. (line 66) * mx32: i386 and x86-64 Options. - (line 835) + (line 841) * mxgot <1>: MIPS Options. (line 192) * mxgot: M680x0 Options. (line 319) * mxilinx-fpu: RS/6000 and PowerPC Options. - (line 317) + (line 386) * mxl-barrel-shift: MicroBlaze Options. (line 33) * mxl-compat: RS/6000 and PowerPC Options. - (line 253) + (line 322) * mxl-float-convert: MicroBlaze Options. (line 51) * mxl-float-sqrt: MicroBlaze Options. (line 54) * mxl-gp-opt: MicroBlaze Options. (line 45) @@ -50419,7 +51418,7 @@ look up both forms. * mxl-soft-mul: MicroBlaze Options. (line 27) * mxl-stack-check: MicroBlaze Options. (line 42) * myellowknife: RS/6000 and PowerPC Options. - (line 590) + (line 671) * mzarch: S/390 and zSeries Options. (line 95) * mzda: V850 Options. (line 45) @@ -50500,7 +51499,7 @@ look up both forms. * private_bundle: Darwin Options. (line 196) * pthread <1>: Solaris 2 Options. (line 31) * pthread: RS/6000 and PowerPC Options. - (line 716) + (line 797) * pthreads: Solaris 2 Options. (line 25) * Q: Debugging Options. (line 340) * Qn: System V Options. (line 18) @@ -50587,7 +51586,7 @@ look up both forms. * Wa: Assembler Options. (line 9) * Wabi: C++ Dialect Options. (line 362) -* Waddr-space-convert: AVR Options. (line 217) +* Waddr-space-convert: AVR Options. (line 213) * Waddress: Warning Options. (line 1177) * Waggregate-return: Warning Options. (line 1195) * Waggressive-loop-optimizations: Warning Options. (line 1200) @@ -50992,7 +51991,7 @@ Keyword Index * #pragma implementation, implied: C++ Interface. (line 46) * #pragma interface: C++ Interface. (line 20) * #pragma, reason for not using: Function Attributes. - (line 1870) + (line 1878) * $: Dollar Signs. (line 6) * % in constraint: Modifiers. (line 45) * %include: Spec Files. (line 27) @@ -51010,7 +52009,7 @@ Keyword Index * -nodefaultlibs and unresolved references: Link Options. (line 85) * -nostdlib and unresolved references: Link Options. (line 85) * .sdata/.sdata2 references (PowerPC): RS/6000 and PowerPC Options. - (line 662) + (line 743) * //: C++ Comments. (line 6) * 0 in constraint: Simple Constraints. (line 127) * < in constraint: Simple Constraints. (line 48) @@ -51021,9 +52020,9 @@ Keyword Index * ?: side effect: Conditionals. (line 20) * _ in variables in macros: Typeof. (line 46) * __atomic_add_fetch: __atomic Builtins. (line 169) -* __atomic_always_lock_free: __atomic Builtins. (line 242) +* __atomic_always_lock_free: __atomic Builtins. (line 247) * __atomic_and_fetch: __atomic Builtins. (line 173) -* __atomic_clear: __atomic Builtins. (line 219) +* __atomic_clear: __atomic Builtins. (line 221) * __atomic_compare_exchange: __atomic Builtins. (line 161) * __atomic_compare_exchange_n: __atomic Builtins. (line 138) * __atomic_exchange: __atomic Builtins. (line 130) @@ -51034,17 +52033,17 @@ Keyword Index * __atomic_fetch_or: __atomic Builtins. (line 197) * __atomic_fetch_sub: __atomic Builtins. (line 191) * __atomic_fetch_xor: __atomic Builtins. (line 195) -* __atomic_is_lock_free: __atomic Builtins. (line 256) +* __atomic_is_lock_free: __atomic Builtins. (line 261) * __atomic_load: __atomic Builtins. (line 98) * __atomic_load_n: __atomic Builtins. (line 89) * __atomic_nand_fetch: __atomic Builtins. (line 179) * __atomic_or_fetch: __atomic Builtins. (line 177) -* __atomic_signal_fence: __atomic Builtins. (line 234) +* __atomic_signal_fence: __atomic Builtins. (line 239) * __atomic_store: __atomic Builtins. (line 113) * __atomic_store_n: __atomic Builtins. (line 104) * __atomic_sub_fetch: __atomic Builtins. (line 171) * __atomic_test_and_set: __atomic Builtins. (line 210) -* __atomic_thread_fence: __atomic Builtins. (line 227) +* __atomic_thread_fence: __atomic Builtins. (line 232) * __atomic_xor_fetch: __atomic Builtins. (line 175) * __builtin___clear_cache: Other Builtins. (line 372) * __builtin___fprintf_chk: Object Size Checking. @@ -51146,6 +52145,8 @@ Keyword Index * __builtin_nans: Other Builtins. (line 509) * __builtin_nansf: Other Builtins. (line 513) * __builtin_nansl: Other Builtins. (line 516) +* __builtin_non_tx_store: S/390 System z Built-in Functions. + (line 104) * __builtin_object_size: Object Size Checking. (line 6) * __builtin_offsetof: Offsetof. (line 6) @@ -51205,9 +52206,27 @@ Keyword Index (line 96) * __builtin_set_thread_pointer: SH Built-in Functions. (line 10) +* __builtin_tabort: S/390 System z Built-in Functions. + (line 87) +* __builtin_tbegin: S/390 System z Built-in Functions. + (line 7) +* __builtin_tbegin_nofloat: S/390 System z Built-in Functions. + (line 59) +* __builtin_tbegin_retry: S/390 System z Built-in Functions. + (line 65) +* __builtin_tbegin_retry_nofloat: S/390 System z Built-in Functions. + (line 72) +* __builtin_tbeginc: S/390 System z Built-in Functions. + (line 78) +* __builtin_tend: S/390 System z Built-in Functions. + (line 82) * __builtin_thread_pointer: SH Built-in Functions. (line 20) * __builtin_trap: Other Builtins. (line 281) +* __builtin_tx_assist: S/390 System z Built-in Functions. + (line 92) +* __builtin_tx_nesting_depth: S/390 System z Built-in Functions. + (line 98) * __builtin_types_compatible_p: Other Builtins. (line 111) * __builtin_unreachable: Other Builtins. (line 288) * __builtin_va_arg_pack: Constructing Calls. (line 53) @@ -51274,6 +52293,8 @@ Keyword Index * _exit: Other Builtins. (line 6) * _Exit: Other Builtins. (line 6) * _Fract data type: Fixed-Point. (line 6) +* _HTM_FIRST_USER_ABORT_CODE: S/390 System z Built-in Functions. + (line 48) * _Sat data type: Fixed-Point. (line 6) * _xabort: X86 transactional memory intrinsics. (line 68) @@ -51314,7 +52335,7 @@ Keyword Index * alloca: Other Builtins. (line 6) * alloca vs variable-length arrays: Variable Length. (line 26) * Allow nesting in an interrupt handler on the Blackfin processor.: Function Attributes. - (line 935) + (line 943) * alternate keywords: Alternate Keywords. (line 6) * always_inline function attribute: Function Attributes. (line 91) @@ -51479,9 +52500,9 @@ Keyword Index * code generation conventions: Code Gen Options. (line 6) * code, mixed with declarations: Mixed Declarations. (line 6) * cold function attribute: Function Attributes. - (line 1158) + (line 1166) * cold label attribute: Function Attributes. - (line 1176) + (line 1184) * command options: Invoking GCC. (line 6) * comments, C++ style: C++ Comments. (line 6) * common attribute: Variable Attributes. @@ -51614,7 +52635,7 @@ Keyword Index * earlyclobber operand: Modifiers. (line 25) * eight-bit data on the H8/300, H8/300H, and H8S: Function Attributes. (line 346) -* EIND: AVR Options. (line 224) +* EIND: AVR Options. (line 220) * empty structures: Empty Structures. (line 6) * environment variables: Environment Variables. (line 6) @@ -51692,7 +52713,7 @@ Keyword Index * fmodf: Other Builtins. (line 6) * fmodl: Other Builtins. (line 6) * force_align_arg_pointer attribute: Function Attributes. - (line 1218) + (line 1226) * format function attribute: Function Attributes. (line 419) * format_arg function attribute: Function Attributes. @@ -51724,7 +52745,7 @@ Keyword Index * function versions: Function Multiversioning. (line 6) * function without a prologue/epilogue code: Function Attributes. - (line 912) + (line 920) * function, size of pointer to: Pointer Arith. (line 6) * functions called via pointer on the RS/6000 and PowerPC: Function Attributes. (line 808) @@ -51737,7 +52758,7 @@ Keyword Index * functions that behave like malloc: Function Attributes. (line 6) * functions that do not handle memory bank switching on 68HC11/68HC12: Function Attributes. - (line 925) + (line 933) * functions that do not pop the argument stack on the 386: Function Attributes. (line 6) * functions that do pop the argument stack on the 386: Function Attributes. @@ -51804,9 +52825,11 @@ Keyword Index * hosted environment: Standards. (line 13) * hosted implementation: Standards. (line 13) * hot function attribute: Function Attributes. - (line 1136) + (line 1144) * hot label attribute: Function Attributes. - (line 1148) + (line 1156) +* hotpatch attribute: Function Attributes. + (line 912) * HPPA Options: HPPA Options. (line 6) * HR fixed-suffix: Fixed-Point. (line 6) * hr fixed-suffix: Fixed-Point. (line 6) @@ -51859,7 +52882,7 @@ Keyword Index * interrupt handler functions: Function Attributes. (line 141) * interrupt handler functions on the AVR processors: Function Attributes. - (line 1313) + (line 1321) * interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors: Function Attributes. (line 735) * interrupt service routines on ARM: Function Attributes. @@ -52097,31 +53120,31 @@ Keyword Index * NFC: Warning Options. (line 1284) * NFKC: Warning Options. (line 1284) * NMI handler functions on the Blackfin processor: Function Attributes. - (line 940) + (line 948) * no_instrument_function function attribute: Function Attributes. - (line 946) + (line 954) * no_sanitize_address function attribute: Function Attributes. - (line 1186) + (line 1194) * no_split_stack function attribute: Function Attributes. - (line 951) + (line 959) * noclone function attribute: Function Attributes. - (line 968) + (line 976) * nocommon attribute: Variable Attributes. (line 105) * noinline function attribute: Function Attributes. - (line 957) + (line 965) * nomips16 attribute: Function Attributes. (line 839) * non-constant initializers: Initializers. (line 6) * non-static inline function: Inline. (line 85) * nonnull function attribute: Function Attributes. - (line 974) + (line 982) * noreturn function attribute: Function Attributes. - (line 998) + (line 1006) * nosave_low_regs attribute: Function Attributes. - (line 1048) + (line 1056) * nothrow function attribute: Function Attributes. - (line 1040) + (line 1048) * o in constraint: Simple Constraints. (line 23) * OBJC_INCLUDE_PATH: Environment Variables. (line 132) @@ -52139,7 +53162,7 @@ Keyword Index * OpenMP parallel: C Dialect Options. (line 256) * operand constraints, asm: Constraints. (line 6) * optimize function attribute: Function Attributes. - (line 1054) + (line 1062) * optimize options: Optimize Options. (line 6) * options to control diagnostics formatting: Language Independent Options. (line 6) @@ -52162,9 +53185,9 @@ Keyword Index * order of evaluation, side effects: Non-bugs. (line 196) * order of options: Invoking GCC. (line 30) * OS_main AVR function attribute: Function Attributes. - (line 1071) + (line 1079) * OS_task AVR function attribute: Function Attributes. - (line 1071) + (line 1079) * other register constraints: Simple Constraints. (line 163) * output file option: Overall Options. (line 191) * overloaded virtual function, warning: C++ Dialect Options. @@ -52175,7 +53198,7 @@ Keyword Index * parameter forward declaration: Variable Length. (line 59) * Pascal: G++ and GCC. (line 23) * pcs function attribute: Function Attributes. - (line 1096) + (line 1104) * PDP-11 Options: PDP-11 Options. (line 6) * PIC: Code Gen Options. (line 267) * picoChip options: picoChip Options. (line 6) @@ -52227,7 +53250,7 @@ Keyword Index * pragma, push_macro: Push/Pop Macro Pragmas. (line 11) * pragma, reason for not using: Function Attributes. - (line 1870) + (line 1878) * pragma, redefine_extname: Symbol-Renaming Pragmas. (line 12) * pragma, segment: Darwin Pragmas. (line 21) @@ -52252,7 +53275,7 @@ Keyword Index * promotion of formal parameters: Function Prototypes. (line 6) * pure function attribute: Function Attributes. - (line 1114) + (line 1122) * push address instruction: Simple Constraints. (line 154) * putchar: Other Builtins. (line 6) * puts: Other Builtins. (line 6) @@ -52263,10 +53286,10 @@ Keyword Index * R fixed-suffix: Fixed-Point. (line 6) * r fixed-suffix: Fixed-Point. (line 6) * r in constraint: Simple Constraints. (line 66) -* RAMPD: AVR Options. (line 340) -* RAMPX: AVR Options. (line 340) -* RAMPY: AVR Options. (line 340) -* RAMPZ: AVR Options. (line 340) +* RAMPD: AVR Options. (line 336) +* RAMPX: AVR Options. (line 336) +* RAMPY: AVR Options. (line 336) +* RAMPZ: AVR Options. (line 336) * ranges in case statements: Case Ranges. (line 6) * read-only strings: Incompatibilities. (line 9) * register variable after longjmp: Global Reg Vars. (line 65) @@ -52276,7 +53299,7 @@ Keyword Index * registers, global allocation: Explicit Reg Vars. (line 6) * registers, global variables in: Global Reg Vars. (line 6) * regparm attribute: Function Attributes. - (line 1194) + (line 1202) * relocation truncated to fit (ColdFire): M680x0 Options. (line 329) * relocation truncated to fit (MIPS): MIPS Options. (line 200) * remainder: Other Builtins. (line 6) @@ -52286,12 +53309,12 @@ Keyword Index * remquof: Other Builtins. (line 6) * remquol: Other Builtins. (line 6) * renesas attribute: Function Attributes. - (line 1226) + (line 1234) * reordering, warning: C++ Dialect Options. (line 533) * reporting bugs: Bugs. (line 6) * resbank attribute: Function Attributes. - (line 1230) + (line 1238) * rest argument (in macro): Variadic Macros. (line 6) * restricted pointers: Restricted Pointers. (line 6) @@ -52300,7 +53323,7 @@ Keyword Index * restricted this pointer: Restricted Pointers. (line 6) * returns_twice attribute: Function Attributes. - (line 1244) + (line 1252) * rindex: Other Builtins. (line 6) * rint: Other Builtins. (line 6) * rintf: Other Builtins. (line 6) @@ -52318,9 +53341,9 @@ Keyword Index * S/390 and zSeries Options: S/390 and zSeries Options. (line 6) * save all registers on the Blackfin, H8/300, H8/300H, and H8S: Function Attributes. - (line 1253) + (line 1261) * save volatile registers on the MicroBlaze: Function Attributes. - (line 1258) + (line 1266) * scalb: Other Builtins. (line 6) * scalbf: Other Builtins. (line 6) * scalbl: Other Builtins. (line 6) @@ -52336,11 +53359,11 @@ Keyword Index * Score Options: Score Options. (line 6) * search path: Directory Options. (line 6) * section function attribute: Function Attributes. - (line 1266) + (line 1274) * section variable attribute: Variable Attributes. (line 166) * sentinel function attribute: Function Attributes. - (line 1282) + (line 1290) * setjmp: Global Reg Vars. (line 65) * setjmp incompatibilities: Incompatibilities. (line 39) * shared strings: Incompatibilities. (line 9) @@ -52373,11 +53396,11 @@ Keyword Index * sizeof: Typeof. (line 6) * smaller data references: M32R/D Options. (line 57) * smaller data references (PowerPC): RS/6000 and PowerPC Options. - (line 662) + (line 743) * snprintf: Other Builtins. (line 6) * Solaris 2 options: Solaris 2 Options. (line 6) * sp_switch attribute: Function Attributes. - (line 1331) + (line 1339) * SPARC options: SPARC Options. (line 6) * Spec Files: Spec Files. (line 6) * specified registers: Explicit Reg Vars. (line 6) @@ -52396,7 +53419,7 @@ Keyword Index * sscanf: Other Builtins. (line 6) * sscanf, and constant strings: Incompatibilities. (line 17) * sseregparm attribute: Function Attributes. - (line 1211) + (line 1219) * statements inside expressions: Statement Exprs. (line 6) * static data in C++, declaring and defining: Static Definitions. (line 6) @@ -52423,6 +53446,8 @@ Keyword Index * strspn: Other Builtins. (line 6) * strstr: Other Builtins. (line 6) * struct: Unnamed Fields. (line 6) +* struct __htm_tdb: S/390 System z Built-in Functions. + (line 54) * structures: Incompatibilities. (line 146) * structures, constructor expression: Compound Literals. (line 6) * submodel options: Submodel Options. (line 6) @@ -52436,7 +53461,7 @@ Keyword Index (line 6) * syntax checking: Warning Options. (line 13) * syscall_linkage attribute: Function Attributes. - (line 1346) + (line 1354) * system headers, warnings from: Warning Options. (line 843) * sysv_abi attribute: Function Attributes. (line 881) @@ -52447,111 +53472,111 @@ Keyword Index * tanhl: Other Builtins. (line 6) * tanl: Other Builtins. (line 6) * target function attribute: Function Attributes. - (line 1353) + (line 1361) * target machine, specifying: Target Options. (line 6) * target options: Target Options. (line 6) * target("abm") attribute: Function Attributes. - (line 1379) + (line 1387) * target("aes") attribute: Function Attributes. - (line 1384) + (line 1392) * target("align-stringops") attribute: Function Attributes. - (line 1478) + (line 1486) * target("altivec") attribute: Function Attributes. - (line 1504) + (line 1512) * target("arch=ARCH") attribute: Function Attributes. - (line 1487) + (line 1495) * target("avoid-indexed-addresses") attribute: Function Attributes. - (line 1625) + (line 1633) * target("cld") attribute: Function Attributes. - (line 1449) + (line 1457) * target("cmpb") attribute: Function Attributes. - (line 1510) + (line 1518) * target("cpu=CPU") attribute: Function Attributes. - (line 1640) + (line 1648) * target("default") attribute: Function Attributes. - (line 1387) + (line 1395) * target("dlmzb") attribute: Function Attributes. - (line 1516) + (line 1524) * target("fancy-math-387") attribute: Function Attributes. - (line 1453) + (line 1461) * target("fma4") attribute: Function Attributes. - (line 1433) + (line 1441) * target("fpmath=FPMATH") attribute: Function Attributes. - (line 1495) + (line 1503) * target("fprnd") attribute: Function Attributes. - (line 1523) + (line 1531) * target("friz") attribute: Function Attributes. - (line 1616) + (line 1624) * target("fused-madd") attribute: Function Attributes. - (line 1458) + (line 1466) * target("hard-dfp") attribute: Function Attributes. - (line 1529) + (line 1537) * target("ieee-fp") attribute: Function Attributes. - (line 1463) + (line 1471) * target("inline-all-stringops") attribute: Function Attributes. - (line 1468) + (line 1476) * target("inline-stringops-dynamically") attribute: Function Attributes. - (line 1472) + (line 1480) * target("isel") attribute: Function Attributes. - (line 1535) + (line 1543) * target("longcall") attribute: Function Attributes. - (line 1635) + (line 1643) * target("lwp") attribute: Function Attributes. - (line 1441) + (line 1449) * target("mfcrf") attribute: Function Attributes. - (line 1539) + (line 1547) * target("mfpgpr") attribute: Function Attributes. - (line 1546) + (line 1554) * target("mmx") attribute: Function Attributes. - (line 1392) + (line 1400) * target("mulhw") attribute: Function Attributes. - (line 1553) + (line 1561) * target("multiple") attribute: Function Attributes. - (line 1560) + (line 1568) * target("paired") attribute: Function Attributes. - (line 1630) + (line 1638) * target("pclmul") attribute: Function Attributes. - (line 1396) + (line 1404) * target("popcnt") attribute: Function Attributes. - (line 1400) + (line 1408) * target("popcntb") attribute: Function Attributes. - (line 1571) + (line 1579) * target("popcntd") attribute: Function Attributes. - (line 1578) + (line 1586) * target("powerpc-gfxopt") attribute: Function Attributes. - (line 1584) + (line 1592) * target("powerpc-gpopt") attribute: Function Attributes. - (line 1590) + (line 1598) * target("recip") attribute: Function Attributes. - (line 1482) + (line 1490) * target("recip-precision") attribute: Function Attributes. - (line 1596) + (line 1604) * target("sse") attribute: Function Attributes. - (line 1404) + (line 1412) * target("sse2") attribute: Function Attributes. - (line 1408) + (line 1416) * target("sse3") attribute: Function Attributes. - (line 1412) + (line 1420) * target("sse4") attribute: Function Attributes. - (line 1416) + (line 1424) * target("sse4.1") attribute: Function Attributes. - (line 1421) + (line 1429) * target("sse4.2") attribute: Function Attributes. - (line 1425) + (line 1433) * target("sse4a") attribute: Function Attributes. - (line 1429) + (line 1437) * target("ssse3") attribute: Function Attributes. - (line 1445) + (line 1453) * target("string") attribute: Function Attributes. - (line 1602) + (line 1610) * target("tune=TUNE") attribute: Function Attributes. - (line 1491) + (line 1499) * target("update") attribute: Function Attributes. - (line 1565) + (line 1573) * target("vsx") attribute: Function Attributes. - (line 1608) + (line 1616) * target("xop") attribute: Function Attributes. - (line 1437) + (line 1445) * TC1: Standards. (line 13) * TC2: Standards. (line 13) * TC3: Standards. (line 13) @@ -52570,7 +53595,7 @@ Keyword Index * TILE-Gx options: TILE-Gx Options. (line 6) * TILEPro options: TILEPro Options. (line 6) * tiny data section on the H8/300H and H8S: Function Attributes. - (line 1669) + (line 1677) * TLS: Thread-Local. (line 6) * tls_model attribute: Variable Attributes. (line 235) @@ -52583,9 +53608,9 @@ Keyword Index * towupper: Other Builtins. (line 6) * traditional C language: C Dialect Options. (line 307) * trap_exit attribute: Function Attributes. - (line 1676) + (line 1684) * trapa_handler attribute: Function Attributes. - (line 1681) + (line 1689) * trunc: Other Builtins. (line 6) * truncf: Other Builtins. (line 6) * truncl: Other Builtins. (line 6) @@ -52620,7 +53645,7 @@ Keyword Index * unresolved references and -nodefaultlibs: Link Options. (line 85) * unresolved references and -nostdlib: Link Options. (line 85) * unused attribute.: Function Attributes. - (line 1685) + (line 1693) * UR fixed-suffix: Fixed-Point. (line 6) * ur fixed-suffix: Fixed-Point. (line 6) * use_debug_exception_return attribute: Function Attributes. @@ -52628,7 +53653,7 @@ Keyword Index * use_shadow_register_set attribute: Function Attributes. (line 703) * used attribute.: Function Attributes. - (line 1690) + (line 1698) * User stack pointer in interrupts on the Blackfin: Function Attributes. (line 754) * V in constraint: Simple Constraints. (line 43) @@ -52650,14 +53675,14 @@ Keyword Index * variadic macros: Variadic Macros. (line 6) * VAX options: VAX Options. (line 6) * version_id attribute: Function Attributes. - (line 1700) + (line 1708) * vfprintf: Other Builtins. (line 6) * vfscanf: Other Builtins. (line 6) * visibility attribute: Function Attributes. - (line 1710) + (line 1718) * VLAs: Variable Length. (line 6) * vliw attribute: Function Attributes. - (line 1803) + (line 1811) * void pointers, arithmetic: Pointer Arith. (line 6) * void, size of pointer to: Pointer Arith. (line 6) * volatile access <1>: C++ Volatiles. (line 6) @@ -52678,7 +53703,7 @@ Keyword Index * W floating point suffix: Floating Types. (line 6) * w floating point suffix: Floating Types. (line 6) * warn_unused_result attribute: Function Attributes. - (line 1809) + (line 1817) * warning for comparison of signed and unsigned values: Warning Options. (line 1156) * warning for overloaded virtual function: C++ Dialect Options. @@ -52693,9 +53718,9 @@ Keyword Index * warnings vs errors: Warnings and Errors. (line 6) * weak attribute: Function Attributes. - (line 1826) + (line 1834) * weakref attribute: Function Attributes. - (line 1835) + (line 1843) * whitespace: Incompatibilities. (line 112) * X in constraint: Simple Constraints. (line 124) * X3.159-1989: Standards. (line 13) @@ -52720,305 +53745,307 @@ Keyword Index  Tag Table: -Node: Top1920 -Node: G++ and GCC3686 -Node: Standards5755 -Node: Invoking GCC17933 -Node: Option Summary21678 -Node: Overall Options61417 -Node: Invoking G++75516 -Node: C Dialect Options77039 -Node: C++ Dialect Options92878 -Node: Objective-C and Objective-C++ Dialect Options120980 -Node: Language Independent Options131488 -Node: Warning Options133687 -Node: Debugging Options202888 -Node: Optimize Options260279 -Ref: Type-punning318948 -Node: Preprocessor Options397157 -Ref: Wtrigraphs401939 -Ref: dashMF406687 -Ref: fdollars-in-identifiers417551 -Node: Assembler Options427818 -Node: Link Options428510 -Ref: Link Options-Footnote-1439754 -Node: Directory Options440088 -Node: Spec Files446647 -Node: Target Options468045 -Node: Submodel Options468444 -Node: AArch64 Options470137 -Node: Adapteva Epiphany Options474011 -Node: ARM Options479962 -Node: AVR Options495607 -Node: Blackfin Options515951 -Node: C6X Options523966 -Node: CRIS Options525509 -Node: CR16 Options529253 -Node: Darwin Options530160 -Node: DEC Alpha Options537593 -Node: FR30 Options549181 -Node: FRV Options549746 -Node: GNU/Linux Options556465 -Node: H8/300 Options557726 -Node: HPPA Options559176 -Node: i386 and x86-64 Options568660 -Node: i386 and x86-64 Windows Options605501 -Node: IA-64 Options608357 -Node: LM32 Options616421 -Node: M32C Options616945 -Node: M32R/D Options618219 -Node: M680x0 Options621765 -Node: MCore Options635811 -Node: MeP Options637314 -Node: MicroBlaze Options641273 -Node: MIPS Options644069 -Node: MMIX Options672969 -Node: MN10300 Options675451 -Node: Moxie Options677994 -Node: PDP-11 Options678365 -Node: picoChip Options680057 -Node: PowerPC Options682198 -Node: RL78 Options682419 -Node: RS/6000 and PowerPC Options683081 -Node: RX Options717931 -Node: S/390 and zSeries Options725265 -Node: Score Options733187 -Node: SH Options734029 -Node: Solaris 2 Options752884 -Node: SPARC Options754115 -Node: SPU Options766821 -Node: System V Options771758 -Node: TILE-Gx Options772584 -Node: TILEPro Options773508 -Node: V850 Options774012 -Node: VAX Options780725 -Node: VMS Options781260 -Node: VxWorks Options782071 -Node: x86-64 Options783226 -Node: Xstormy16 Options783444 -Node: Xtensa Options783733 -Node: zSeries Options788044 -Node: Code Gen Options788240 -Node: Environment Variables818074 -Node: Precompiled Headers826075 -Node: C Implementation832083 -Node: Translation implementation833752 -Node: Environment implementation834326 -Node: Identifiers implementation834876 -Node: Characters implementation835930 -Node: Integers implementation838736 -Node: Floating point implementation840561 -Node: Arrays and pointers implementation843490 -Ref: Arrays and pointers implementation-Footnote-1844925 -Node: Hints implementation845049 -Node: Structures unions enumerations and bit-fields implementation846515 -Node: Qualifiers implementation848501 -Node: Declarators implementation850273 -Node: Statements implementation850615 -Node: Preprocessing directives implementation850942 -Node: Library functions implementation853047 -Node: Architecture implementation853687 -Node: Locale-specific behavior implementation854390 -Node: C++ Implementation854695 -Node: Conditionally-supported behavior855977 -Node: Exception handling856487 -Node: C Extensions856896 -Node: Statement Exprs861890 -Node: Local Labels866349 -Node: Labels as Values869322 -Ref: Labels as Values-Footnote-1871721 -Node: Nested Functions871904 -Node: Constructing Calls875862 -Node: Typeof880580 -Node: Conditionals883888 -Node: __int128884778 -Node: Long Long885302 -Node: Complex886778 -Node: Floating Types889367 -Node: Half-Precision890495 -Node: Decimal Float892677 -Node: Hex Floats894532 -Node: Fixed-Point895568 -Node: Named Address Spaces898850 -Ref: AVR Named Address Spaces899531 -Node: Zero Length904737 -Node: Empty Structures908024 -Node: Variable Length908430 -Node: Variadic Macros911106 -Node: Escaped Newlines913484 -Node: Subscripting914323 -Node: Pointer Arith915049 -Node: Initializers915617 -Node: Compound Literals916113 -Node: Designated Inits919474 -Node: Case Ranges923106 -Node: Cast to Union923787 -Node: Mixed Declarations924878 -Node: Function Attributes925388 -Node: Attribute Syntax1011269 -Node: Function Prototypes1021660 -Node: C++ Comments1023441 -Node: Dollar Signs1023960 -Node: Character Escapes1024425 -Node: Variable Attributes1024719 -Ref: AVR Variable Attributes1038386 -Ref: MeP Variable Attributes1041047 -Ref: i386 Variable Attributes1042993 -Node: Type Attributes1048657 -Ref: MeP Type Attributes1062545 -Ref: i386 Type Attributes1062819 -Ref: PowerPC Type Attributes1063510 -Ref: SPU Type Attributes1064372 -Node: Alignment1064663 -Node: Inline1066033 -Node: Volatiles1071008 -Node: Extended Asm1073890 -Ref: Example of asm with clobbered asm reg1079794 -Ref: Extended asm with goto1089501 -Node: Constraints1097352 -Node: Simple Constraints1098436 -Node: Multi-Alternative1105757 -Node: Modifiers1107474 -Node: Machine Constraints1110488 -Node: Asm Labels1159452 -Node: Explicit Reg Vars1161128 -Node: Global Reg Vars1162731 -Node: Local Reg Vars1167227 -Node: Alternate Keywords1169644 -Node: Incomplete Enums1171130 -Node: Function Names1171886 -Node: Return Address1174047 -Node: Vector Extensions1177554 -Node: Offsetof1183729 -Node: __sync Builtins1184542 -Node: __atomic Builtins1190012 -Node: x86 specific memory model extensions for transactional memory1201298 -Node: Object Size Checking1202535 -Node: Other Builtins1208024 -Node: Target Builtins1237168 -Node: Alpha Built-in Functions1238308 -Node: ARM iWMMXt Built-in Functions1241317 -Node: ARM NEON Intrinsics1248297 -Node: AVR Built-in Functions1456716 -Node: Blackfin Built-in Functions1459786 -Node: FR-V Built-in Functions1460403 -Node: Argument Types1461262 -Node: Directly-mapped Integer Functions1463014 -Node: Directly-mapped Media Functions1464096 -Node: Raw read/write Functions1471128 -Node: Other Built-in Functions1472040 -Node: X86 Built-in Functions1473224 -Node: X86 transactional memory intrinsics1532192 -Node: MIPS DSP Built-in Functions1534866 -Node: MIPS Paired-Single Support1547374 -Node: MIPS Loongson Built-in Functions1548873 -Node: Paired-Single Arithmetic1555393 -Node: Paired-Single Built-in Functions1556341 -Node: MIPS-3D Built-in Functions1559008 -Node: Other MIPS Built-in Functions1564385 -Node: picoChip Built-in Functions1564909 -Node: PowerPC Built-in Functions1566258 -Node: PowerPC AltiVec/VSX Built-in Functions1567672 -Node: RX Built-in Functions1677659 -Node: SH Built-in Functions1681662 -Node: SPARC VIS Built-in Functions1683043 -Node: SPU Built-in Functions1688647 -Node: TI C6X Built-in Functions1690463 -Node: TILE-Gx Built-in Functions1691487 -Node: TILEPro Built-in Functions1692604 -Node: Target Format Checks1693671 -Node: Solaris Format Checks1694103 -Node: Darwin Format Checks1694529 -Node: Pragmas1695347 -Node: ARM Pragmas1696057 -Node: M32C Pragmas1696660 -Node: MeP Pragmas1697734 -Node: RS/6000 and PowerPC Pragmas1699803 -Node: Darwin Pragmas1700544 -Node: Solaris Pragmas1701611 -Node: Symbol-Renaming Pragmas1702772 -Node: Structure-Packing Pragmas1704326 -Node: Weak Pragmas1705976 -Node: Diagnostic Pragmas1706710 -Node: Visibility Pragmas1709817 -Node: Push/Pop Macro Pragmas1710569 -Node: Function Specific Option Pragmas1711541 -Node: Unnamed Fields1713798 -Node: Thread-Local1716026 -Node: C99 Thread-Local Edits1718131 -Node: C++98 Thread-Local Edits1720143 -Node: Binary constants1723587 -Node: C++ Extensions1724258 -Node: C++ Volatiles1725969 -Node: Restricted Pointers1728317 -Node: Vague Linkage1729908 -Node: C++ Interface1733532 -Ref: C++ Interface-Footnote-11737818 -Node: Template Instantiation1737954 -Node: Bound member functions1744541 -Node: C++ Attributes1746073 -Node: Function Multiversioning1748729 -Node: Namespace Association1750544 -Node: Type Traits1751924 -Node: Java Exceptions1758412 -Node: Deprecated Features1759802 -Node: Backwards Compatibility1762767 -Node: Objective-C1764119 -Node: GNU Objective-C runtime API1764728 -Node: Modern GNU Objective-C runtime API1765735 -Node: Traditional GNU Objective-C runtime API1768172 -Node: Executing code before main1768900 -Node: What you can and what you cannot do in +load1771638 -Node: Type encoding1774028 -Node: Legacy type encoding1779104 -Node: @encode1780195 -Node: Method signatures1780736 -Node: Garbage Collection1782731 -Node: Constant string objects1785420 -Node: compatibility_alias1787928 -Node: Exceptions1788650 -Node: Synchronization1791361 -Node: Fast enumeration1792545 -Node: Using fast enumeration1792857 -Node: c99-like fast enumeration syntax1794068 -Node: Fast enumeration details1794771 -Node: Fast enumeration protocol1797112 -Node: Messaging with the GNU Objective-C runtime1800264 -Node: Dynamically registering methods1801635 -Node: Forwarding hook1803326 -Node: Compatibility1806366 -Node: Gcov1812933 -Node: Gcov Intro1813466 -Node: Invoking Gcov1816184 -Node: Gcov and Optimization1829095 -Node: Gcov Data Files1832095 -Node: Cross-profiling1833490 -Node: Trouble1835341 -Node: Actual Bugs1836753 -Node: Interoperation1837200 -Node: Incompatibilities1844092 -Node: Fixed Headers1852243 -Node: Standard Libraries1853906 -Node: Disappointments1855278 -Node: C++ Misunderstandings1859636 -Node: Static Definitions1860447 -Node: Name lookup1861500 -Ref: Name lookup-Footnote-11866278 -Node: Temporaries1866465 -Node: Copy Assignment1868441 -Node: Non-bugs1870248 -Node: Warnings and Errors1880755 -Node: Bugs1882517 -Node: Bug Criteria1883081 -Node: Bug Reporting1885291 -Node: Service1885512 -Node: Contributing1886331 -Node: Funding1887071 -Node: GNU Project1889560 -Node: Copying1890206 -Node: GNU Free Documentation License1927734 -Node: Contributors1952871 -Node: Option Index1990273 -Node: Keyword Index2180269 +Node: Top1934 +Node: G++ and GCC3700 +Node: Standards5769 +Node: Invoking GCC17947 +Node: Option Summary21692 +Node: Overall Options61821 +Node: Invoking G++76059 +Node: C Dialect Options77582 +Node: C++ Dialect Options93421 +Node: Objective-C and Objective-C++ Dialect Options121523 +Node: Language Independent Options132031 +Node: Warning Options134230 +Node: Debugging Options203431 +Node: Optimize Options260822 +Ref: Type-punning319491 +Node: Preprocessor Options397700 +Ref: Wtrigraphs402482 +Ref: dashMF407230 +Ref: fdollars-in-identifiers418094 +Node: Assembler Options428361 +Node: Link Options429053 +Ref: Link Options-Footnote-1440297 +Node: Directory Options440631 +Node: Spec Files447190 +Node: Target Options468588 +Node: Submodel Options468987 +Node: AArch64 Options470680 +Node: Adapteva Epiphany Options474554 +Node: ARM Options480505 +Node: AVR Options496355 +Node: Blackfin Options516473 +Node: C6X Options524488 +Node: CRIS Options526031 +Node: CR16 Options529775 +Node: Darwin Options530682 +Node: DEC Alpha Options538115 +Node: FR30 Options549703 +Node: FRV Options550268 +Node: GNU/Linux Options556987 +Node: H8/300 Options558248 +Node: HPPA Options559698 +Node: i386 and x86-64 Options569182 +Node: i386 and x86-64 Windows Options606268 +Node: IA-64 Options609124 +Node: LM32 Options617188 +Node: M32C Options617712 +Node: M32R/D Options618986 +Node: M680x0 Options622532 +Node: MCore Options636578 +Node: MeP Options638081 +Node: MicroBlaze Options642040 +Node: MIPS Options644836 +Node: MMIX Options673736 +Node: MN10300 Options676218 +Node: Moxie Options678761 +Node: PDP-11 Options679132 +Node: picoChip Options680824 +Node: PowerPC Options682965 +Node: RL78 Options683186 +Node: RS/6000 and PowerPC Options683848 +Node: RX Options722869 +Node: S/390 and zSeries Options730203 +Node: Score Options738763 +Node: SH Options739605 +Node: Solaris 2 Options758460 +Node: SPARC Options759691 +Node: SPU Options772941 +Node: System V Options777878 +Node: TILE-Gx Options778704 +Node: TILEPro Options779628 +Node: V850 Options780132 +Node: VAX Options786845 +Node: VMS Options787380 +Node: VxWorks Options788191 +Node: x86-64 Options789346 +Node: Xstormy16 Options789564 +Node: Xtensa Options789853 +Node: zSeries Options794164 +Node: Code Gen Options794360 +Node: Environment Variables824194 +Node: Precompiled Headers832195 +Node: C Implementation838203 +Node: Translation implementation839872 +Node: Environment implementation840446 +Node: Identifiers implementation840996 +Node: Characters implementation842050 +Node: Integers implementation844856 +Node: Floating point implementation846681 +Node: Arrays and pointers implementation849610 +Ref: Arrays and pointers implementation-Footnote-1851045 +Node: Hints implementation851169 +Node: Structures unions enumerations and bit-fields implementation852635 +Node: Qualifiers implementation854621 +Node: Declarators implementation856393 +Node: Statements implementation856735 +Node: Preprocessing directives implementation857062 +Node: Library functions implementation859167 +Node: Architecture implementation859807 +Node: Locale-specific behavior implementation860510 +Node: C++ Implementation860815 +Node: Conditionally-supported behavior862097 +Node: Exception handling862607 +Node: C Extensions863016 +Node: Statement Exprs868010 +Node: Local Labels872469 +Node: Labels as Values875442 +Ref: Labels as Values-Footnote-1877841 +Node: Nested Functions878024 +Node: Constructing Calls881982 +Node: Typeof886700 +Node: Conditionals890008 +Node: __int128890898 +Node: Long Long891422 +Node: Complex892898 +Node: Floating Types895487 +Node: Half-Precision896615 +Node: Decimal Float898797 +Node: Hex Floats900652 +Node: Fixed-Point901688 +Node: Named Address Spaces904970 +Ref: AVR Named Address Spaces905651 +Node: Zero Length910857 +Node: Empty Structures914144 +Node: Variable Length914550 +Node: Variadic Macros917226 +Node: Escaped Newlines919604 +Node: Subscripting920443 +Node: Pointer Arith921169 +Node: Initializers921737 +Node: Compound Literals922233 +Node: Designated Inits925594 +Node: Case Ranges929226 +Node: Cast to Union929907 +Node: Mixed Declarations930998 +Node: Function Attributes931508 +Node: Attribute Syntax1017836 +Node: Function Prototypes1028227 +Node: C++ Comments1030008 +Node: Dollar Signs1030527 +Node: Character Escapes1030992 +Node: Variable Attributes1031286 +Ref: AVR Variable Attributes1044953 +Ref: MeP Variable Attributes1047614 +Ref: i386 Variable Attributes1049560 +Node: Type Attributes1055224 +Ref: MeP Type Attributes1069112 +Ref: i386 Type Attributes1069386 +Ref: PowerPC Type Attributes1070077 +Ref: SPU Type Attributes1070939 +Node: Alignment1071230 +Node: Inline1072600 +Node: Volatiles1077575 +Node: Extended Asm1080457 +Ref: Example of asm with clobbered asm reg1086361 +Ref: Extended asm with goto1096068 +Node: Constraints1103919 +Node: Simple Constraints1105003 +Node: Multi-Alternative1112324 +Node: Modifiers1114041 +Node: Machine Constraints1117055 +Node: Asm Labels1167278 +Node: Explicit Reg Vars1168954 +Node: Global Reg Vars1170557 +Node: Local Reg Vars1175053 +Node: Alternate Keywords1177470 +Node: Incomplete Enums1178956 +Node: Function Names1179712 +Node: Return Address1181873 +Node: Vector Extensions1185380 +Node: Offsetof1191555 +Node: __sync Builtins1192368 +Node: __atomic Builtins1197838 +Node: x86 specific memory model extensions for transactional memory1209477 +Node: Object Size Checking1210739 +Node: Other Builtins1216228 +Node: Target Builtins1245372 +Node: Alpha Built-in Functions1246611 +Node: ARM iWMMXt Built-in Functions1249620 +Node: ARM NEON Intrinsics1256600 +Node: AVR Built-in Functions1465019 +Node: Blackfin Built-in Functions1468089 +Node: FR-V Built-in Functions1468706 +Node: Argument Types1469565 +Node: Directly-mapped Integer Functions1471317 +Node: Directly-mapped Media Functions1472399 +Node: Raw read/write Functions1479431 +Node: Other Built-in Functions1480343 +Node: X86 Built-in Functions1481527 +Node: X86 transactional memory intrinsics1540495 +Node: MIPS DSP Built-in Functions1543169 +Node: MIPS Paired-Single Support1555677 +Node: MIPS Loongson Built-in Functions1557176 +Node: Paired-Single Arithmetic1563696 +Node: Paired-Single Built-in Functions1564644 +Node: MIPS-3D Built-in Functions1567311 +Node: Other MIPS Built-in Functions1572688 +Node: picoChip Built-in Functions1573212 +Node: PowerPC Built-in Functions1574561 +Node: PowerPC AltiVec/VSX Built-in Functions1578373 +Node: PowerPC Hardware Transactional Memory Built-in Functions1711271 +Node: RX Built-in Functions1717812 +Node: S/390 System z Built-in Functions1721845 +Node: SH Built-in Functions1727082 +Node: SPARC VIS Built-in Functions1728475 +Node: SPU Built-in Functions1734079 +Node: TI C6X Built-in Functions1735895 +Node: TILE-Gx Built-in Functions1736919 +Node: TILEPro Built-in Functions1738036 +Node: Target Format Checks1739103 +Node: Solaris Format Checks1739535 +Node: Darwin Format Checks1739961 +Node: Pragmas1740779 +Node: ARM Pragmas1741489 +Node: M32C Pragmas1742092 +Node: MeP Pragmas1743166 +Node: RS/6000 and PowerPC Pragmas1745235 +Node: Darwin Pragmas1745976 +Node: Solaris Pragmas1747043 +Node: Symbol-Renaming Pragmas1748204 +Node: Structure-Packing Pragmas1749758 +Node: Weak Pragmas1751408 +Node: Diagnostic Pragmas1752142 +Node: Visibility Pragmas1755249 +Node: Push/Pop Macro Pragmas1756001 +Node: Function Specific Option Pragmas1756973 +Node: Unnamed Fields1759230 +Node: Thread-Local1761458 +Node: C99 Thread-Local Edits1763563 +Node: C++98 Thread-Local Edits1765575 +Node: Binary constants1769019 +Node: C++ Extensions1769690 +Node: C++ Volatiles1771401 +Node: Restricted Pointers1773749 +Node: Vague Linkage1775340 +Node: C++ Interface1778964 +Ref: C++ Interface-Footnote-11783250 +Node: Template Instantiation1783386 +Node: Bound member functions1789973 +Node: C++ Attributes1791505 +Node: Function Multiversioning1794161 +Node: Namespace Association1795976 +Node: Type Traits1797356 +Node: Java Exceptions1803844 +Node: Deprecated Features1805234 +Node: Backwards Compatibility1808199 +Node: Objective-C1809551 +Node: GNU Objective-C runtime API1810160 +Node: Modern GNU Objective-C runtime API1811167 +Node: Traditional GNU Objective-C runtime API1813604 +Node: Executing code before main1814332 +Node: What you can and what you cannot do in +load1817070 +Node: Type encoding1819460 +Node: Legacy type encoding1824536 +Node: @encode1825627 +Node: Method signatures1826168 +Node: Garbage Collection1828163 +Node: Constant string objects1830852 +Node: compatibility_alias1833360 +Node: Exceptions1834082 +Node: Synchronization1836793 +Node: Fast enumeration1837977 +Node: Using fast enumeration1838289 +Node: c99-like fast enumeration syntax1839500 +Node: Fast enumeration details1840203 +Node: Fast enumeration protocol1842544 +Node: Messaging with the GNU Objective-C runtime1845696 +Node: Dynamically registering methods1847067 +Node: Forwarding hook1848758 +Node: Compatibility1851798 +Node: Gcov1858365 +Node: Gcov Intro1858898 +Node: Invoking Gcov1861616 +Node: Gcov and Optimization1874527 +Node: Gcov Data Files1877527 +Node: Cross-profiling1878922 +Node: Trouble1880773 +Node: Actual Bugs1882185 +Node: Interoperation1882632 +Node: Incompatibilities1889524 +Node: Fixed Headers1897675 +Node: Standard Libraries1899338 +Node: Disappointments1900710 +Node: C++ Misunderstandings1905068 +Node: Static Definitions1905879 +Node: Name lookup1906932 +Ref: Name lookup-Footnote-11911710 +Node: Temporaries1911897 +Node: Copy Assignment1913873 +Node: Non-bugs1915680 +Node: Warnings and Errors1926187 +Node: Bugs1927949 +Node: Bug Criteria1928513 +Node: Bug Reporting1930723 +Node: Service1930944 +Node: Contributing1931763 +Node: Funding1932503 +Node: GNU Project1934992 +Node: Copying1935638 +Node: GNU Free Documentation License1973166 +Node: Contributors1998303 +Node: Option Index2035705 +Node: Keyword Index2228711  End Tag Table diff --git a/gcc-4.8/gcc/doc/gccinstall.info b/gcc-4.8/gcc/doc/gccinstall.info index 30f065533..9dcfde6f4 100644 --- a/gcc-4.8/gcc/doc/gccinstall.info +++ b/gcc-4.8/gcc/doc/gccinstall.info @@ -1,5 +1,5 @@ -This is doc/gccinstall.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/install.texi. +This is doc/gccinstall.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/install.texi. Copyright (C) 1988-2013 Free Software Foundation, Inc. @@ -207,7 +207,7 @@ simplest way to install the libraries. GNU Multiple Precision Library (GMP) version 4.3.2 (or later) Necessary to build GCC. If a GMP source distribution is found in a subdirectory of your GCC sources named `gmp', it will be built - together with GCC. Alternatively, if GMP is already installed but + together with GCC. Alternatively, if GMP is already installed but it is not in your library search path, you will have to configure with the `--with-gmp' configure option. See also `--with-gmp-lib' and `--with-gmp-include'. @@ -561,7 +561,7 @@ option. between cross and native configurations. `--with-specs=SPECS' - Specify additional command line driver SPECS. This can be + Specify additional command line driver SPECS. This can be useful if you need to turn on a non-standard feature by default without modifying the compiler's source code, for instance @@ -1435,13 +1435,13 @@ option. `--with-boot-ldflags=FLAGS' This option may be used to set linker flags to be used when linking - stage 2 and later when bootstrapping GCC. If neither + stage 2 and later when bootstrapping GCC. If neither -with-boot-libs nor -with-host-libstdcxx is set to a value, then the default is `-static-libstdc++ -static-libgcc'. `--with-boot-libs=LIBS' This option may be used to set libraries to be used when linking - stage 2 and later when bootstrapping GCC. The default is the + stage 2 and later when bootstrapping GCC. The default is the argument to `--with-host-libstdcxx', if specified. `--with-debug-prefix-map=MAP' @@ -1730,19 +1730,19 @@ General Options `--with-arch-directory=ARCH' Specifies the name to use for the `jre/lib/ARCH' directory in the - SDK environment created when -enable-java-home is passed. Typical + SDK environment created when -enable-java-home is passed. Typical names for this directory include i386, amd64, ia64, etc. `--with-os-directory=DIR' - Specifies the OS directory for the SDK include directory. This is + Specifies the OS directory for the SDK include directory. This is set to auto detect, and is typically 'linux'. `--with-origin-name=NAME' - Specifies the JPackage origin name. This defaults to the 'gcj' in + Specifies the JPackage origin name. This defaults to the 'gcj' in java-1.5.0-gcj. `--with-arch-suffix=SUFFIX' - Specifies the suffix for the sdk directory. Defaults to the empty + Specifies the suffix for the sdk directory. Defaults to the empty string. Examples include '.x86_64' in 'java-1.5.0-gcj-1.5.0.0.x86_64'. @@ -1750,7 +1750,7 @@ General Options Specifies where to install the SDK. Default is $(prefix)/lib/jvm. `--with-jvm-jar-dir=DIR' - Specifies where to install jars. Default is + Specifies where to install jars. Default is $(prefix)/lib/jvm-exports. `--with-python-dir=DIR' @@ -1758,7 +1758,7 @@ General Options aot-compile. DIR should not include the prefix used in installation. For example, if the Python modules are to be installed in /usr/lib/python2.5/site-packages, then - -with-python-dir=/lib/python2.5/site-packages should be passed. If + -with-python-dir=/lib/python2.5/site-packages should be passed. If this is not specified, then the Python modules are installed in $(prefix)/share/python. @@ -1769,7 +1769,7 @@ General Options Build the gcjwebplugin web browser plugin. `--enable-static-libjava' - Build static libraries in libjava. The default is to only build + Build static libraries in libjava. The default is to only build shared libraries. `ansi' @@ -2161,7 +2161,7 @@ disable building the Ada front end. `ADA_INCLUDE_PATH' and `ADA_OBJECT_PATH' environment variables must not be set when building the Ada compiler, the Ada tools, or the Ada -runtime libraries. You can check that your build environment is clean +runtime libraries. You can check that your build environment is clean by verifying that `gnatls -v' lists only one explicit path in each section. @@ -2628,7 +2628,7 @@ tools can also be obtained from: Blackfin ======== -The Blackfin processor, an Analog Devices DSP. *Note Blackfin Options: +The Blackfin processor, an Analog Devices DSP. *Note Blackfin Options: (gcc)Blackfin Options, More information, and a version of binutils with support for this @@ -2637,7 +2637,7 @@ processor, is available at `http://blackfin.uclinux.org' CR16 ==== -The CR16 CompactRISC architecture is a 16-bit architecture. This +The CR16 CompactRISC architecture is a 16-bit architecture. This architecture is used in embedded applications. *Note CR16 Options: (gcc)CR16 Options, @@ -3056,7 +3056,7 @@ assembler change that sometimes produces corrupt assembly files causing AIX linker errors. The bug breaks GCC bootstrap on AIX and can cause compilation failures with existing GCC installations. An AIX iFix for AIX 5.3 is available (APAR IZ98385 for AIX 5.3 TL10, APAR IZ98477 for -AIX 5.3 TL11 and IZ98134 for AIX 5.3 TL12). AIX 5.3 TL11 SP8, AIX 5.3 +AIX 5.3 TL11 and IZ98134 for AIX 5.3 TL12). AIX 5.3 TL11 SP8, AIX 5.3 TL12 SP5, AIX 6.1 TL04 SP11, AIX 6.1 TL05 SP7, AIX 6.1 TL06 SP6, AIX 6.1 TL07 and AIX 7.1 TL01 should include the fix. @@ -3246,7 +3246,7 @@ use the `--with-divide=breaks' `configure' option when configuring GCC. The default is to use traps on systems that support them. The assembler from GNU binutils 2.17 and earlier has a bug in the way -it sorts relocations for REL targets (o32, o64, EABI). This can cause +it sorts relocations for REL targets (o32, o64, EABI). This can cause bad code to be generated for simple C++ programs. Also the linker from GNU binutils versions prior to 2.17 has a bug which causes the runtime linker stubs in very large programs, like `libgcj.so', to be @@ -3373,7 +3373,7 @@ been removed in GCC 4.6. though you can download the Sun Studio compilers for free. In Solaris 10 and 11, GCC 3.4.3 is available as `/usr/sfw/bin/gcc'. Solaris 11 also provides GCC 4.5.2 as `/usr/gcc/4.5/bin/gcc'. Alternatively, you -can install a pre-built GCC to bootstrap and install GCC. See the +can install a pre-built GCC to bootstrap and install GCC. See the binaries page for details. The Solaris 2 `/bin/sh' will often fail to configure `libstdc++-v3', @@ -3522,7 +3522,7 @@ library or the MPC library on a Solaris 7 or later system, the canonical target triplet must be specified as the `build' parameter on the configure line. This target triplet can be obtained by invoking `./config.guess' in the toplevel source directory of GCC (and not that -of GMP or MPFR or MPC). For example on a Solaris 9 system: +of GMP or MPFR or MPC). For example on a Solaris 9 system: % ./configure --build=sparc-sun-solaris2.9 --prefix=xxx @@ -3530,7 +3530,7 @@ sparc-sun-solaris2.10 ===================== There is a bug in older versions of the Sun assembler which breaks -thread-local storage (TLS). A typical error message is +thread-local storage (TLS). A typical error message is ld: fatal: relocation error: R_SPARC_TLS_LE_HIX22: file /var/tmp//ccamPA1v.o: symbol : bad symbol type SECT: symbol type must be TLS @@ -3689,7 +3689,7 @@ and which C libraries are used. * MinGW *-*-mingw32: MinGW is a native GCC port for the Win32 subsystem that provides a subset of POSIX. - * MKS i386-pc-mks: NuTCracker from MKS. See + * MKS i386-pc-mks: NuTCracker from MKS. See `http://www.mkssoftware.com/' for more information. Intel 64-bit versions @@ -3742,7 +3742,7 @@ version 2.20 or above if building your own. =========== The Interix target is used by OpenNT, Interix, Services For UNIX (SFU), -and Subsystem for UNIX-based Applications (SUA). Applications compiled +and Subsystem for UNIX-based Applications (SUA). Applications compiled with this target run in the Interix subsystem, which is separate from the Win32 subsystem. This target was last known to work in GCC 3.3. @@ -4354,7 +4354,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -4375,7 +4375,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -4422,7 +4422,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -4474,93 +4474,93 @@ Concept Index  Tag Table: -Node: Top1733 -Node: Installing GCC2291 -Node: Prerequisites3928 -Node: Downloading the source14255 -Node: Configuration15809 -Ref: with-gnu-as30815 -Ref: with-as31713 -Ref: with-gnu-ld33126 -Node: Building80044 -Node: Testing95529 -Node: Final install103401 -Node: Binaries108715 -Node: Specific110227 -Ref: alpha-x-x110737 -Ref: alpha-dec-osf51111226 -Ref: amd64-x-solaris210111751 -Ref: arm-x-eabi111854 -Ref: avr112065 -Ref: bfin112705 -Ref: cr16112947 -Ref: cris113362 -Ref: dos114178 -Ref: epiphany-x-elf114501 -Ref: x-x-freebsd114606 -Ref: h8300-hms116443 -Ref: hppa-hp-hpux116795 -Ref: hppa-hp-hpux10119166 -Ref: hppa-hp-hpux11119579 -Ref: x-x-linux-gnu125238 -Ref: ix86-x-linux125431 -Ref: ix86-x-solaris29125744 -Ref: ix86-x-solaris210126523 -Ref: ia64-x-linux127714 -Ref: ia64-x-hpux128484 -Ref: x-ibm-aix129039 -Ref: iq2000-x-elf135902 -Ref: lm32-x-elf136042 -Ref: lm32-x-uclinux136146 -Ref: m32c-x-elf136274 -Ref: m32r-x-elf136376 -Ref: m68k-x-x136478 -Ref: m68k-x-uclinux137516 -Ref: mep-x-elf137762 -Ref: microblaze-x-elf137872 -Ref: mips-x-x137991 -Ref: mips-sgi-irix5140387 -Ref: mips-sgi-irix6140467 -Ref: moxie-x-elf140654 -Ref: powerpc-x-x140701 -Ref: powerpc-x-darwin140906 -Ref: powerpc-x-elf141400 -Ref: powerpc-x-linux-gnu141485 -Ref: powerpc-x-netbsd141580 -Ref: powerpc-x-eabisim141668 -Ref: powerpc-x-eabi141794 -Ref: powerpcle-x-elf141870 -Ref: powerpcle-x-eabisim141962 -Ref: powerpcle-x-eabi142095 -Ref: rl78-x-elf142178 -Ref: rx-x-elf142284 -Ref: s390-x-linux142483 -Ref: s390x-x-linux142555 -Ref: s390x-ibm-tpf142642 -Ref: x-x-solaris2142773 -Ref: sparc-x-x147536 -Ref: sparc-sun-solaris2148038 -Ref: sparc-sun-solaris210150792 -Ref: sparc-x-linux151168 -Ref: sparc64-x-solaris2151393 -Ref: sparcv9-x-solaris2152046 -Ref: c6x-x-x152133 -Ref: tilegx-*-linux152224 -Ref: tilepro-*-linux152343 -Ref: x-x-vxworks152464 -Ref: x86-64-x-x153986 -Ref: x86-64-x-solaris210154314 -Ref: xtensa-x-elf154976 -Ref: xtensa-x-linux155647 -Ref: windows155988 -Ref: x-x-cygwin157925 -Ref: x-x-interix158478 -Ref: x-x-mingw32158787 -Ref: older159013 -Ref: elf161130 -Node: Old161388 -Node: Configurations164525 -Node: GNU Free Documentation License168066 -Node: Concept Index193213 +Node: Top1747 +Node: Installing GCC2305 +Node: Prerequisites3942 +Node: Downloading the source14269 +Node: Configuration15823 +Ref: with-gnu-as30829 +Ref: with-as31727 +Ref: with-gnu-ld33140 +Node: Building80058 +Node: Testing95543 +Node: Final install103415 +Node: Binaries108729 +Node: Specific110241 +Ref: alpha-x-x110751 +Ref: alpha-dec-osf51111240 +Ref: amd64-x-solaris210111765 +Ref: arm-x-eabi111868 +Ref: avr112079 +Ref: bfin112719 +Ref: cr16112961 +Ref: cris113376 +Ref: dos114192 +Ref: epiphany-x-elf114515 +Ref: x-x-freebsd114620 +Ref: h8300-hms116457 +Ref: hppa-hp-hpux116809 +Ref: hppa-hp-hpux10119180 +Ref: hppa-hp-hpux11119593 +Ref: x-x-linux-gnu125252 +Ref: ix86-x-linux125445 +Ref: ix86-x-solaris29125758 +Ref: ix86-x-solaris210126537 +Ref: ia64-x-linux127728 +Ref: ia64-x-hpux128498 +Ref: x-ibm-aix129053 +Ref: iq2000-x-elf135916 +Ref: lm32-x-elf136056 +Ref: lm32-x-uclinux136160 +Ref: m32c-x-elf136288 +Ref: m32r-x-elf136390 +Ref: m68k-x-x136492 +Ref: m68k-x-uclinux137530 +Ref: mep-x-elf137776 +Ref: microblaze-x-elf137886 +Ref: mips-x-x138005 +Ref: mips-sgi-irix5140401 +Ref: mips-sgi-irix6140481 +Ref: moxie-x-elf140668 +Ref: powerpc-x-x140715 +Ref: powerpc-x-darwin140920 +Ref: powerpc-x-elf141414 +Ref: powerpc-x-linux-gnu141499 +Ref: powerpc-x-netbsd141594 +Ref: powerpc-x-eabisim141682 +Ref: powerpc-x-eabi141808 +Ref: powerpcle-x-elf141884 +Ref: powerpcle-x-eabisim141976 +Ref: powerpcle-x-eabi142109 +Ref: rl78-x-elf142192 +Ref: rx-x-elf142298 +Ref: s390-x-linux142497 +Ref: s390x-x-linux142569 +Ref: s390x-ibm-tpf142656 +Ref: x-x-solaris2142787 +Ref: sparc-x-x147550 +Ref: sparc-sun-solaris2148052 +Ref: sparc-sun-solaris210150806 +Ref: sparc-x-linux151182 +Ref: sparc64-x-solaris2151407 +Ref: sparcv9-x-solaris2152060 +Ref: c6x-x-x152147 +Ref: tilegx-*-linux152238 +Ref: tilepro-*-linux152357 +Ref: x-x-vxworks152478 +Ref: x86-64-x-x154000 +Ref: x86-64-x-solaris210154328 +Ref: xtensa-x-elf154990 +Ref: xtensa-x-linux155661 +Ref: windows156002 +Ref: x-x-cygwin157939 +Ref: x-x-interix158492 +Ref: x-x-mingw32158801 +Ref: older159027 +Ref: elf161144 +Node: Old161402 +Node: Configurations164539 +Node: GNU Free Documentation License168080 +Node: Concept Index193227  End Tag Table diff --git a/gcc-4.8/gcc/doc/gccint.info b/gcc-4.8/gcc/doc/gccint.info index e41c572a0..83f533215 100644 --- a/gcc-4.8/gcc/doc/gccint.info +++ b/gcc-4.8/gcc/doc/gccint.info @@ -1,5 +1,5 @@ -This is doc/gccint.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/doc/gccint.texi. +This is doc/gccint.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/doc/gccint.texi. Copyright (C) 1988-2013 Free Software Foundation, Inc. @@ -57,7 +57,7 @@ Introduction This manual documents the internals of the GNU compilers, including how to port them to new targets and some information about how to write front ends for new languages. It corresponds to the compilers -(GCC) version 4.8.1. The use of the GNU compilers is documented in a +(GCC) version 4.8.3. The use of the GNU compilers is documented in a separate manual. *Note Introduction: (gcc)Top. This manual is mainly a reference manual rather than a tutorial. It @@ -3132,7 +3132,7 @@ that contain parts of GCC and its runtime libraries: The Ada runtime library. `libatomic' - The runtime support library for atomic operations (e.g. for + The runtime support library for atomic operations (e.g. for `__sync' and `__atomic'). `libcpp' @@ -3600,7 +3600,7 @@ languages that are not enabled by default in stage1. For example, `make f951' will build a Fortran compiler even in the stage1 build directory. - ---------- Footnotes ---------- + ---------- Footnotes ---------- (1) Except if the compiler was buggy and miscompiled some of the files that were not modified. In this case, it's best to use `make restrap'. @@ -4935,6 +4935,12 @@ specified for the particular test in an earlier `dg-options' or 7.2.3.8 PowerPC-specific attributes ................................... +`dfp_hw' + PowerPC target supports executing hardware DFP instructions. + +`p8vector_hw' + PowerPC target supports executing VSX instructions (ISA 2.07). + `powerpc64' Test system supports executing 64-bit instructions. @@ -4944,12 +4950,24 @@ specified for the particular test in an earlier `dg-options' or `powerpc_altivec_ok' PowerPC target supports `-maltivec'. +`powerpc_eabi_ok' + PowerPC target supports `-meabi'. + +`powerpc_elfv2' + PowerPC target supports `-mabi=elfv2'. + `powerpc_fprs' PowerPC target supports floating-point registers. `powerpc_hard_double' PowerPC target supports hardware double-precision floating-point. +`powerpc_htm_ok' + PowerPC target supports `-mhtm' + +`powerpc_p8vector_ok' + PowerPC target supports `-mpower8-vector' + `powerpc_ppu_ok' PowerPC target supports `-mcpu=cell'. @@ -4963,10 +4981,6 @@ specified for the particular test in an earlier `dg-options' or `powerpc_spu' PowerPC target supports PowerPC SPU. -`spu_auto_overlay' - SPU target has toolchain that supports automatic overlay - generation. - `powerpc_vsx_ok' PowerPC target supports `-mvsx'. @@ -4974,9 +4988,19 @@ specified for the particular test in an earlier `dg-options' or Including the options used to compile this particular test, the PowerPC target supports PowerPC 405. +`ppc_recip_hw' + PowerPC target supports executing reciprocal estimate instructions. + +`spu_auto_overlay' + SPU target has toolchain that supports automatic overlay + generation. + `vmx_hw' PowerPC target supports executing AltiVec instructions. +`vsx_hw' + PowerPC target supports executing VSX instructions (ISA 2.06). + 7.2.3.9 Other hardware attributes ................................. @@ -5086,8 +5110,8 @@ specified for the particular test in an earlier `dg-options' or non-empty string. `simulator' - Test system runs executables on a simulator (i.e. slowly) rather - than hardware (i.e. fast). + Test system runs executables on a simulator (i.e. slowly) rather + than hardware (i.e. fast). `stdint_types' Target has the basic signed and unsigned C types in `stdint.h'. @@ -6951,7 +6975,7 @@ run after gimplification and what source files they are located in. Range Propagation, J. R. C. Patterson, PLDI '95). In contrast to Patterson's algorithm, this implementation does not propagate branch probabilities nor it uses more than a single range per SSA - name. This means that the current implementation cannot be used + name. This means that the current implementation cannot be used for branch prediction (though adapting it would not be difficult). The pass is located in `tree-vrp.c' and is described by `pass_vrp'. @@ -6971,7 +6995,7 @@ run after gimplification and what source files they are located in. * Control dependence dead code elimination This pass is a stronger form of dead code elimination that can - eliminate unnecessary control flow statements. It is located in + eliminate unnecessary control flow statements. It is located in `tree-ssa-dce.c' and is described by `pass_cd_dce'. * Tail call elimination @@ -7027,7 +7051,7 @@ run after gimplification and what source files they are located in. If a function always returns the same local variable, and that local variable is an aggregate type, then the variable is replaced with the return value for the function (i.e., the function's - DECL_RESULT). This is equivalent to the C++ named return value + DECL_RESULT). This is equivalent to the C++ named return value optimization applied to GIMPLE. The pass is located in `tree-nrv.c' and is described by `pass_nrv'. @@ -8265,10 +8289,10 @@ object of `BITS_PER_UNIT' bits (*note Storage Layout::). "Double Integer" mode represents an eight-byte integer. `TImode' - "Tetra Integer" (?) mode represents a sixteen-byte integer. + "Tetra Integer" (?) mode represents a sixteen-byte integer. `OImode' - "Octa Integer" (?) mode represents a thirty-two-byte integer. + "Octa Integer" (?) mode represents a thirty-two-byte integer. `QFmode' "Quarter-Floating" mode represents a quarter-precision (single @@ -8279,7 +8303,7 @@ object of `BITS_PER_UNIT' bits (*note Storage Layout::). floating point number. `TQFmode' - "Three-Quarter-Floating" (?) mode represents a + "Three-Quarter-Floating" (?) mode represents a three-quarter-precision (three byte) floating point number. `SFmode' @@ -8840,7 +8864,7 @@ registers and to main memory. `subreg's come in two distinct flavors, each having its own usage and rules: - Paradoxical subregs + Paradoxical subregs When M1 is strictly wider than M2, the `subreg' expression is called "paradoxical". The canonical test for this class of `subreg' is: @@ -8885,7 +8909,7 @@ registers and to main memory. bytes to an unknown value assuming `SUBREG_PROMOTED_VAR_P' is false. - Normal subregs + Normal subregs When M1 is at least as narrow as M2 the `subreg' expression is called "normal". @@ -11108,12 +11132,12 @@ case label. Objective-C++ front ends by allowing efficient comparison between two type nodes in `same_type_p': if the `TYPE_CANONICAL' values of the types are equal, the types are equivalent; otherwise, the types - are not equivalent. The notion of equivalence for canonical types + are not equivalent. The notion of equivalence for canonical types is the same as the notion of type equivalence in the language - itself. For instance, + itself. For instance, When `TYPE_CANONICAL' is `NULL_TREE', there is no canonical type - for the given type node. In this case, comparison between this + for the given type node. In this case, comparison between this type and any other type requires the compiler to perform a deep, "structural" comparison to see if the two type nodes have the same form and properties. @@ -11124,7 +11148,7 @@ case label. canonical type. Similarly, `I*' and a typedef `IP' (defined to `I*') will has `int*' as their canonical type. When building a new type node, be sure to set `TYPE_CANONICAL' to the appropriate - canonical type. If the new type is a compound type (built from + canonical type. If the new type is a compound type (built from other types), and any of those other types require structural equality, use `SET_TYPE_STRUCTURAL_EQUALITY' to ensure that the new type also requires structural equality. Finally, if for some @@ -12663,7 +12687,7 @@ clauses used by the OpenMP API `http://www.openmp.org/'. which is implicitly private to each thread. Bounds `N1' and `N2' and the increment expression `INCR' are required to be loop invariant integer expressions that are evaluated without any - synchronization. The evaluation order, frequency of evaluation and + synchronization. The evaluation order, frequency of evaluation and side-effects are unspecified by the standard. `OMP_SECTIONS' @@ -12711,7 +12735,7 @@ clauses used by the OpenMP API `http://www.openmp.org/'. `OMP_RETURN' This does not represent any OpenMP directive, it is an artificial - marker to indicate the end of the body of an OpenMP. It is used by + marker to indicate the end of the body of an OpenMP. It is used by the flow graph (`tree-cfg.c') and OpenMP region building code (`omp-low.c'). @@ -13740,7 +13764,7 @@ at McGill University, though we have made some different choices. For one thing, SIMPLE doesn't support `goto'. Temporaries are introduced to hold intermediate values needed to -compute complex expressions. Additionally, all the control structures +compute complex expressions. Additionally, all the control structures used in GENERIC are lowered into conditional jumps, lexical scopes are removed and exception regions are converted into an on the side exception region tree. @@ -13751,7 +13775,7 @@ tuples out of the original GENERIC expressions. One of the early implementation strategies used for the GIMPLE representation was to use the same internal data structures used by -front ends to represent parse trees. This simplified implementation +front ends to represent parse trees. This simplified implementation because we could leverage existing functionality and interfaces. However, GIMPLE is a much more restrictive representation than abstract syntax trees (AST), therefore it does not require the full structural @@ -13812,14 +13836,14 @@ File: gccint.info, Node: Tuple representation, Next: GIMPLE instruction set, GIMPLE instructions are tuples of variable size divided in two groups: a header describing the instruction and its locations, and a variable -length body with all the operands. Tuples are organized into a +length body with all the operands. Tuples are organized into a hierarchy with 3 main classes of tuples. 12.1.1 `gimple_statement_base' (gsbase) --------------------------------------- This is the root of the hierarchy, it holds basic information needed by -most GIMPLE statements. There are some fields that may not be relevant +most GIMPLE statements. There are some fields that may not be relevant to every GIMPLE statement, but those were moved into the base structure to take advantage of holes left by other fields (thus making the structure more compact). The structure takes 4 words (32 bytes) on 64 @@ -13845,12 +13869,12 @@ Total size 32 bytes * `code' Main identifier for a GIMPLE instruction. * `subcode' Used to distinguish different variants of the same basic - instruction or provide flags applicable to a given code. The + instruction or provide flags applicable to a given code. The `subcode' flags field has different uses depending on the code of the instruction, but mostly it distinguishes instructions of the - same family. The most prominent use of this field is in + same family. The most prominent use of this field is in assignments, where subcode indicates the operation done on the RHS - of the assignment. For example, a = b + c is encoded as + of the assignment. For example, a = b + c is encoded as `GIMPLE_ASSIGN '. * `no_warning' Bitflag to indicate whether a warning has already @@ -13865,7 +13889,7 @@ Total size 32 bytes bit holes left by the previous fields. * `plf' Pass Local Flags. This 2-bit mask can be used as general - purpose markers by any pass. Passes are responsible for clearing + purpose markers by any pass. Passes are responsible for clearing and setting these two flags accordingly. * `modified' Bitflag to indicate whether the statement has been @@ -13881,11 +13905,11 @@ Total size 32 bytes memory). * `uid' This is an unsigned integer used by passes that want to - assign IDs to every statement. These IDs must be assigned and used + assign IDs to every statement. These IDs must be assigned and used by each pass. * `location' This is a `location_t' identifier to specify source code - location for this statement. It is inherited from the front end. + location for this statement. It is inherited from the front end. * `num_ops' Number of operands that this statement has. This specifies the size of the operand vector embedded in the tuple. @@ -13902,8 +13926,8 @@ Total size 32 bytes This tuple is actually split in two: `gimple_statement_with_ops_base' and `gimple_statement_with_ops'. This is needed to accommodate the way -the operand vector is allocated. The operand vector is defined to be an -array of 1 element. So, to allocate a dynamic number of operands, the +the operand vector is allocated. The operand vector is defined to be an +array of 1 element. So, to allocate a dynamic number of operands, the memory allocator (`gimple_alloc') simply allocates enough memory to hold the structure itself plus `N - 1' operands which run "off the end" of the structure. For example, to allocate space for a tuple with 3 @@ -13925,7 +13949,7 @@ Total size 48 + 8 * `num_ops' bytes * `def_ops' Array of pointers into the operand array indicating all the slots that contain a variable written-to by the statement. - This array is also used for immediate use chaining. Note that it + This array is also used for immediate use chaining. Note that it would be possible to not rely on this array, but the changes required to implement this are pretty invasive. @@ -13956,11 +13980,11 @@ Field Size (bits) Total size 80 + 8 * `num_ops' bytes * `vdef_ops' Similar to `def_ops' but for `VDEF' operators. There is - one entry per memory symbol written by this statement. This is + one entry per memory symbol written by this statement. This is used to maintain the memory SSA use-def and def-def chains. * `vuse_ops' Similar to `use_ops' but for `VUSE' operators. There is - one entry per memory symbol loaded by this statement. This is used + one entry per memory symbol loaded by this statement. This is used to maintain the memory SSA use-def chains. * `stores' Bitset with all the UIDs for the symbols written-to by the @@ -13974,7 +13998,7 @@ Total size 80 + 8 * `num_ops' bytes memory utilization further by removing these sets). All the other tuples are defined in terms of these three basic ones. -Each tuple will add some fields. The main gimple type is defined to be +Each tuple will add some fields. The main gimple type is defined to be the union of all these structures (`GTY' markers elided for clarity): union gimple_statement_d @@ -14111,9 +14135,9 @@ value is explicitly loaded into a temporary first. Similarly, storing the value of an expression to a memory variable goes through a temporary. - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) These restrictions are derived from those in Morgan 4.8. + (1) These restrictions are derived from those in Morgan 4.8.  File: gccint.info, Node: Operands, Next: Manipulating GIMPLE statements, Prev: Temporaries, Up: GIMPLE @@ -14190,7 +14214,7 @@ branch assigning to the same temporary. So, a = T1; The GIMPLE level if-conversion pass re-introduces `?:' expression, if -appropriate. It is used to vectorize loops with conditions using vector +appropriate. It is used to vectorize loops with conditions using vector conditional operations. Note that in GIMPLE, `if' statements are represented using @@ -14336,7 +14360,7 @@ exhaustive): -- GIMPLE function: bool is_gimple_ip_invariant (tree t) Return true if t is an interprocedural invariant. This means that - t is a valid invariant in all functions (e.g. it can be an address + t is a valid invariant in all functions (e.g. it can be an address of a global variable but not of a local one). -- GIMPLE function: bool is_gimple_ip_invariant_address (tree t) @@ -14838,7 +14862,7 @@ File: gccint.info, Node: `GIMPLE_CALL', Next: `GIMPLE_CATCH', Prev: `GIMPLE_B -- GIMPLE function: void gimple_call_set_tail (gimple s) Mark call statement `S' as being a tail call (i.e., a call just - before the exit of a function). These calls are candidate for tail + before the exit of a function). These calls are candidate for tail call optimization. -- GIMPLE function: bool gimple_call_tail_p (gimple s) @@ -15219,7 +15243,7 @@ File: gccint.info, Node: `GIMPLE_OMP_FOR', Next: `GIMPLE_OMP_MASTER', Prev: ` gimple_seq pre_body, enum tree_code omp_for_cond) Build a `GIMPLE_OMP_FOR' statement. `BODY' is sequence of statements inside the for loop. `CLAUSES', are any of the `OMP' - loop construct's clauses: private, firstprivate, lastprivate, + loop construct's clauses: private, firstprivate, lastprivate, reductions, ordered, schedule, and nowait. `PRE_BODY' is the sequence of statements that are loop invariant. `INDEX' is the index variable. `INITIAL' is the initial value of `INDEX'. @@ -16454,7 +16478,7 @@ File: gccint.info, Node: SSA, Next: Alias analysis, Prev: SSA Operands, Up: Most of the tree optimizers rely on the data flow information provided by the Static Single Assignment (SSA) form. We implement the SSA form as described in `R. Cytron, J. Ferrante, B. Rosen, M. Wegman, and K. -Zadeck. Efficiently Computing Static Single Assignment Form and the +Zadeck. Efficiently Computing Static Single Assignment Form and the Control Dependence Graph. ACM Transactions on Programming Languages and Systems, 13(4):451-490, October 1991'. @@ -16816,10 +16840,10 @@ disambiguate explicit and implicit memory references. walking statements related to a reference ref. `walk_non_aliased_vuses' walks over dominating memory defining statements and calls back if the statement does not clobber ref - providing the non-aliased VUSE. The walk stops at the first + providing the non-aliased VUSE. The walk stops at the first clobbering statement or if asked to. `walk_aliased_vdefs' walks over dominating memory defining statements and calls back on each - statement clobbering ref providing its aliasing VDEF. The walk + statement clobbering ref providing its aliasing VDEF. The walk stops if asked to. @@ -17133,7 +17157,7 @@ File: gccint.info, Node: LCSSA, Next: Scalar evolutions, Prev: Loop manipulat ========================= Throughout the loop optimizations on tree level, one extra condition is -enforced on the SSA form: No SSA name is used outside of the loop in +enforced on the SSA form: No SSA name is used outside of the loop in that it is defined. The SSA form satisfying this condition is called "loop-closed SSA form" - LCSSA. To enforce LCSSA, PHI nodes must be created at the exits of the loops for the SSA names that are used @@ -17360,9 +17384,9 @@ and mapping this order to the elements of this array avoids costly queries to the loop body representation. Three types of data references are currently handled: ARRAY_REF, -INDIRECT_REF and COMPONENT_REF. The data structure for the data +INDIRECT_REF and COMPONENT_REF. The data structure for the data reference is `data_reference', where `data_reference_p' is a name of a -pointer to the data reference structure. The structure contains the +pointer to the data reference structure. The structure contains the following elements: * `base_object_info': Provides information about the base object of @@ -17377,10 +17401,10 @@ following elements: * `first_location_in_loop': Provides information about the first location accessed by the data reference in the loop and about the access function used to represent evolution relative to this - location. This data is used to support pointers, and is not used - for arrays (for which we have base objects). Pointer accesses are + location. This data is used to support pointers, and is not used + for arrays (for which we have base objects). Pointer accesses are represented as a one-dimensional access that starts from the first - location accessed in the loop. For example: + location accessed in the loop. For example: for1 i for2 j @@ -17461,7 +17485,7 @@ File: gccint.info, Node: Lambda, Next: Omega, Prev: Dependency analysis, Up: Lambda is a framework that allows transformations of loops using non-singular matrix based transformations of the iteration space and -loop bounds. This allows compositions of skewing, scaling, interchange, +loop bounds. This allows compositions of skewing, scaling, interchange, and reversal transformations. These transformations are often used to improve cache behavior or remove inner loop dependencies to allow parallelization and vectorization to take place. @@ -17588,7 +17612,7 @@ all the basic blocks in lexicographical order, except `ENTRY_BLOCK' and lexicographical order, including `ENTRY_BLOCK' and `EXIT_BLOCK'. The functions `post_order_compute' and `inverted_post_order_compute' -can be used to compute topological orders of the CFG. The orders are +can be used to compute topological orders of the CFG. The orders are stored as vectors of basic block indices. The `BASIC_BLOCK' array can be used to iterate each basic block by index. Dominator traversals are also possible using `walk_dominator_tree'. Given two basic blocks A @@ -18019,7 +18043,7 @@ available, including the following: This function inserts a statement before the `gimple_stmt_iterator' passed in. The final parameter determines whether the statement iterator is updated to point to the newly inserted statement, or - left pointing to the original statement. + left pointing to the original statement. `gsi_remove' This function removes the `gimple_stmt_iterator' passed in and @@ -19934,7 +19958,7 @@ _picoChip family--`picochip.h'_ 16-bit signed integer. -_PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ +_PowerPC and IBM RS6000--`config/rs6000/constraints.md'_ `b' Address base register @@ -19948,17 +19972,64 @@ _PowerPC and IBM RS6000--`config/rs6000/rs6000.h'_ `v' Altivec vector register + `wa' + Any VSX register if the -mvsx option was used or NO_REGS. + `wd' - VSX vector register to hold vector double data + VSX vector register to hold vector double data or NO_REGS. `wf' - VSX vector register to hold vector float data + VSX vector register to hold vector float data or NO_REGS. + + `wg' + If `-mmfpgpr' was used, a floating point register or NO_REGS. + + `wl' + Floating point register if the LFIWAX instruction is enabled + or NO_REGS. + + `wm' + VSX register if direct move instructions are enabled, or + NO_REGS. + + `wn' + No register (NO_REGS). + + `wr' + General purpose register if 64-bit instructions are enabled + or NO_REGS. `ws' - VSX vector register to hold scalar float data + VSX vector register to hold scalar double values or NO_REGS. - `wa' - Any VSX register + `wt' + VSX vector register to hold 128 bit integer or NO_REGS. + + `wu' + Altivec register to use for float/32-bit int loads/stores or + NO_REGS. + + `wv' + Altivec register to use for double loads/stores or NO_REGS. + + `ww' + FP or VSX register to perform float operations under `-mvsx' + or NO_REGS. + + `wx' + Floating point register if the STFIWX instruction is enabled + or NO_REGS. + + `wy' + VSX vector register to hold scalar float values or NO_REGS. + + `wz' + Floating point register if the LFIWZX instruction is enabled + or NO_REGS. + + `wQ' + A memory address that will work with the `lq' and `stq' + instructions. `h' `MQ', `CTR', or `LINK' register @@ -20400,7 +20471,7 @@ _Blackfin family--`config/bfin/constraints.md'_ M register `c' - Registers used for circular buffering, i.e. I, B, or L + Registers used for circular buffering, i.e. I, B, or L registers. `C' @@ -21784,7 +21855,7 @@ in the machine description files: definitions with more than one alternative. Otherwise the insn pattern should be disabled or enabled using the insn condition.) - E.g. the following two patterns could easily be merged using the + E.g. the following two patterns could easily be merged using the `enabled' attribute: @@ -21882,27 +21953,27 @@ constraint matches. expression, obeying the same rules as the RTL expressions in predicate definitions. *Note Defining Predicates::, for details. If it evaluates true, the constraint matches; if it evaluates - false, it doesn't. Constraint expressions should indicate which + false, it doesn't. Constraint expressions should indicate which RTL codes they might match, just like predicate expressions. `match_test' C expressions have access to the following variables: - OP + OP The RTL object defining the operand. - MODE + MODE The machine mode of OP. - IVAL + IVAL `INTVAL (OP)', if OP is a `const_int'. - HVAL + HVAL `CONST_DOUBLE_HIGH (OP)', if OP is an integer `const_double'. - LVAL + LVAL `CONST_DOUBLE_LOW (OP)', if OP is an integer `const_double'. - RVAL + RVAL `CONST_DOUBLE_REAL_VALUE (OP)', if OP is a floating-point `const_double'. @@ -21966,7 +22037,7 @@ that match `const_double's or `const_int's. Each docstring in a constraint definition should be one or more complete sentences, marked up in Texinfo format. _They are currently -unused._ In the future they will be copied into the GCC manual, in +unused._ In the future they will be copied into the GCC manual, in *note Machine Constraints::, replacing the hand-maintained tables currently found in that section. Also, in the future the compiler may use this to give more helpful diagnostics when poor choice of `asm' @@ -22002,7 +22073,7 @@ not contain angle brackets or underscores are left unchanged. Underscores are doubled, each `<' is replaced with `_l', and each `>' with `_g'. Here are some examples: - *Original* *Mangled* + *Original* *Mangled* `x' `x' `P42x' `P42x' `P4_x' `P4__x' @@ -22373,36 +22444,36 @@ pattern to accomplish a certain task. the result. `reduc_smin_M', `reduc_smax_M' - Find the signed minimum/maximum of the elements of a vector. The + Find the signed minimum/maximum of the elements of a vector. The vector is operand 1, and the scalar result is stored in the least - significant bits of operand 0 (also a vector). The output and + significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `reduc_umin_M', `reduc_umax_M' - Find the unsigned minimum/maximum of the elements of a vector. The + Find the unsigned minimum/maximum of the elements of a vector. The vector is operand 1, and the scalar result is stored in the least - significant bits of operand 0 (also a vector). The output and + significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `reduc_splus_M' - Compute the sum of the signed elements of a vector. The vector is + Compute the sum of the signed elements of a vector. The vector is operand 1, and the scalar result is stored in the least significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `reduc_uplus_M' - Compute the sum of the unsigned elements of a vector. The vector + Compute the sum of the unsigned elements of a vector. The vector is operand 1, and the scalar result is stored in the least - significant bits of operand 0 (also a vector). The output and + significant bits of operand 0 (also a vector). The output and input vector should have the same modes. `sdot_prodM' `udot_prodM' Compute the sum of the products of two signed/unsigned elements. - Operand 1 and operand 2 are of the same mode. Their product, which - is of a wider mode, is computed and added to operand 3. Operand 3 - is of a mode equal or wider than the mode of the product. The + Operand 1 and operand 2 are of the same mode. Their product, which + is of a wider mode, is computed and added to operand 3. Operand 3 + is of a mode equal or wider than the mode of the product. The result is placed in operand 0, which is of the same mode as operand 3. @@ -22421,7 +22492,7 @@ pattern to accomplish a certain task. output and input vectors should have the same modes. `vec_pack_trunc_M' - Narrow (demote) and merge the elements of two vectors. Operands 1 + Narrow (demote) and merge the elements of two vectors. Operands 1 and 2 are vectors of the same mode having N integral or floating point elements of size S. Operand 0 is the resulting vector in which 2*N elements of size N/2 are concatenated after narrowing @@ -22452,7 +22523,7 @@ pattern to accomplish a certain task. `vec_unpacku_hi_M', `vec_unpacku_lo_M' Extract and widen (promote) the high/low part of a vector of unsigned integral elements. The input vector (operand 1) has N - elements of size S. Widen (promote) the high/low elements of the + elements of size S. Widen (promote) the high/low elements of the vector using zero extension and place the resulting N/2 values of size 2*S in the output vector (operand 0). @@ -22834,7 +22905,7 @@ pattern to accomplish a certain task. Optional operands 5 and 6 specify expected alignment and size of block respectively. The expected alignment differs from alignment in operand 4 in a way that the blocks are not required to be - aligned according to it in all cases. This expected alignment is + aligned according to it in all cases. This expected alignment is also in bytes, just like operand 4. Expected size, when unknown, is set to `(const_int -1)'. @@ -22859,7 +22930,7 @@ pattern to accomplish a certain task. Block set instruction. The destination string is the first operand, given as a `mem:BLK' whose address is in mode `Pmode'. The number of bytes to set is the second operand, in mode M. The - value to initialize the memory with is the third operand. Targets + value to initialize the memory with is the third operand. Targets that only support the clearing of memory should reject any value that is not the constant 0. See `movmemM' for a discussion of the choice of mode. @@ -22872,7 +22943,7 @@ pattern to accomplish a certain task. Optional operands 5 and 6 specify expected alignment and size of block respectively. The expected alignment differs from alignment in operand 4 in a way that the blocks are not required to be - aligned according to it in all cases. This expected alignment is + aligned according to it in all cases. This expected alignment is also in bytes, just like operand 4. Expected size, when unknown, is set to `(const_int -1)'. @@ -23150,7 +23221,7 @@ pattern to accomplish a certain task. target and branching around an assignment of zero to the target--or a libcall. If the predicate for operand 1 only rejects some operators, it will also try reordering the operands and/or - inverting the result value (e.g. by an exclusive OR). These + inverting the result value (e.g. by an exclusive OR). These possibilities could be cheaper or equivalent to the instructions used for the `cstoreMODE4' pattern followed by those required to convert a positive result from `STORE_FLAG_VALUE' to 1; in this @@ -23845,7 +23916,7 @@ pattern to accomplish a certain task. `atomic_orMODE', `atomic_andMODE' `atomic_xorMODE', `atomic_nandMODE' These patterns emit code for an atomic operation on memory with - memory model semantics. Operand 0 is the memory on which the + memory model semantics. Operand 0 is the memory on which the atomic operation is performed. Operand 1 is the second operand to the binary operator. Operand 2 is the memory model to be used by the operation. @@ -23859,7 +23930,7 @@ pattern to accomplish a certain task. `atomic_fetch_orMODE', `atomic_fetch_andMODE' `atomic_fetch_xorMODE', `atomic_fetch_nandMODE' These patterns emit code for an atomic operation on memory with - memory model semantics, and return the original value. Operand 0 + memory model semantics, and return the original value. Operand 0 is an output operand which contains the value of the memory location before the operation was performed. Operand 1 is the memory on which the atomic operation is performed. Operand 2 is @@ -24057,7 +24128,7 @@ distinct signed and unsigned flavors) as in the x86 or SPARC, and the case where there are distinct signed and unsigned compare instructions and only one set of conditional branch instructions as in the PowerPC. - ---------- Footnotes ---------- + ---------- Footnotes ---------- (1) `note' insns can separate them, though. @@ -24308,7 +24379,7 @@ for RTL generation and it can produce more than one RTL insn. RTL insns directly by calling routines such as `emit_insn', etc. Any such insns precede the ones that come from the RTL template. - * Optionally, a vector containing the values of attributes. *Note + * Optionally, a vector containing the values of attributes. *Note Insn Attributes::. Every RTL insn emitted by a `define_expand' must match some @@ -25023,7 +25094,7 @@ The `enabled' attribute can be used to conditionally enable or disable insn alternatives (*note Disable Insn Alternatives::). The `predicable' attribute, together with a suitable `define_cond_exec' (*note Conditional Execution::), can be used to automatically generate -conditional variants of instruction patterns. The compiler internally +conditional variants of instruction patterns. The compiler internally uses the names `ce_enabled' and `nonce_enabled', so they should not be used elsewhere as alternative names. @@ -25071,12 +25142,12 @@ attributes are not free to use for other purposes: `length' The `length' attribute is used to calculate the length of emitted code chunks. This is especially important when verifying branch - distances. *Note Insn Lengths::. + distances. *Note Insn Lengths::. `enabled' The `enabled' attribute can be defined to prevent certain alternatives of an insn definition from being used during code - generation. *Note Disable Insn Alternatives::. + generation. *Note Disable Insn Alternatives::. For each of these special attributes, the corresponding `HAVE_ATTR_NAME' `#define' is also written when the attribute is not @@ -25181,14 +25252,14 @@ Attribute value expressions must have one of the following forms: The test is true if C expression C-EXPR is true. In non-constant attributes, C-EXPR has access to the following variables: - INSN + INSN The rtl instruction under test. - WHICH_ALTERNATIVE + WHICH_ALTERNATIVE The `define_insn' alternative that INSN matches. *Note Output Statement::. - OPERANDS + OPERANDS An array of INSN's rtl operands. C-EXPR behaves like the condition in a C `if' statement, so there @@ -25589,7 +25660,7 @@ there must be no insn for which tests in two `define_delay' expressions are both true. For example, if we have a machine that requires one delay slot for -branches but two for calls, no delay slot can contain a branch or call +branches but two for calls, no delay slot can contain a branch or call insn, and any valid insn in the delay slot for the branch can be annulled if the branch is true, we might represent this as follows: @@ -26009,9 +26080,9 @@ construction (define_insn_reservation "simple" 2 (eq_attr "type" "int") "(i0_pipeline | i1_pipeline), finish") - ---------- Footnotes ---------- + ---------- Footnotes ---------- - (1) However, the size of the automaton depends on processor + (1) However, the size of the automaton depends on processor complexity. To limit this effect, machine descriptions can split orthogonal parts of the machine description among several automata: but then, since each of these must be stepped independently, this does @@ -26129,7 +26200,7 @@ source RTL template is not matched against the input-template of the `define_subst'. In such case the copy is deleted. `define_subst' can be used only in `define_insn' and `define_expand', -it cannot be used in other expressions (e.g. in +it cannot be used in other expressions (e.g. in `define_insn_and_split'). * Menu: @@ -27306,11 +27377,11 @@ You can control the compilation driver. and the machine suffix. 10. The macro `STANDARD_STARTFILE_PREFIX_1', but only if this is a - native compiler, or we have a target system root. The default for + native compiler, or we have a target system root. The default for this macro is `/lib/'. 11. The macro `STANDARD_STARTFILE_PREFIX_2', but only if this is a - native compiler, or we have a target system root. The default for + native compiler, or we have a target system root. The default for this macro is `/usr/lib/'.  @@ -27404,22 +27475,22 @@ Here are run-time target specifications. -- C Target Hook: tree TARGET_OBJC_CONSTRUCT_STRING_OBJECT (tree STRING) Targets may provide a string object type that can be used within - and between C, C++ and their respective Objective-C dialects. A + and between C, C++ and their respective Objective-C dialects. A string object might, for example, embed encoding and length - information. These objects are considered opaque to the compiler - and handled as references. An ideal implementation makes the + information. These objects are considered opaque to the compiler + and handled as references. An ideal implementation makes the composition of the string object match that of the Objective-C `NSString' (`NXString' for GNUStep), allowing efficient - interworking between C-only and Objective-C code. If a target + interworking between C-only and Objective-C code. If a target implements string objects then this hook should return a reference to such an object constructed from the normal `C' string - representation provided in STRING. At present, the hook is used by + representation provided in STRING. At present, the hook is used by Objective-C only, to obtain a common-format string object when the target provides one. -- C Target Hook: void TARGET_OBJC_DECLARE_UNRESOLVED_CLASS_REFERENCE (const char *CLASSNAME) - Declare that Objective C class CLASSNAME is referenced by the + Declare that Objective C class CLASSNAME is referenced by the current TU. -- C Target Hook: void TARGET_OBJC_DECLARE_CLASS_DEFINITION (const @@ -27816,7 +27887,7 @@ expressions that refer to static variables, such as the `target_flags'. -- Target Hook: HOST_WIDE_INT TARGET_VECTOR_ALIGNMENT (const_tree TYPE) This hook can be used to define the alignment for a vector of type - TYPE, in order to comply with a platform ABI. The default is to + TYPE, in order to comply with a platform ABI. The default is to require natural alignment for vector types. The alignment returned by this hook must be a power-of-two multiple of the default alignment of the vector element type. @@ -28469,7 +28540,7 @@ languages, rather than to fundamental aspects of storage layout. By default, the vtable entries are void pointers, the so the alignment is the same as pointer alignment. The value of this macro specifies the alignment of the vtable entry in bits. It - should be defined only when special alignment is necessary. */ + should be defined only when special alignment is necessary. */ -- Macro: TARGET_VTABLE_DATA_ENTRY_DISTANCE There are a few non-descriptor entries in the vtable at offsets @@ -29131,7 +29202,7 @@ return. class to use when it is necessary to rename a register in class RCLASS to another class, or perhaps NO_REGS, if no preferred register class is found or hook `preferred_rename_class' is not - implemented. Sometimes returning a more restrictive class makes + implemented. Sometimes returning a more restrictive class makes better code. For example, on ARM, thumb-2 instructions using `LO_REGS' may be smaller than instructions using `GENERIC_REGS'. By returning `LO_REGS' from `preferred_rename_class', code size @@ -29276,7 +29347,7 @@ return. If copying a register of RELOAD_CLASS from/to X requires an intermediate register, the hook `secondary_reload' should return the register class required for this intermediate register. If no - intermediate register is required, it should return NO_REGS. If + intermediate register is required, it should return NO_REGS. If more than one intermediate register is required, describe the one that is closest in the copy chain to the reload register. @@ -29475,12 +29546,12 @@ return. -- Target Hook: bool TARGET_LRA_P (void) A target hook which returns true if we use LRA instead of reload - pass. It means that LRA was ported to the target. The default + pass. It means that LRA was ported to the target. The default version of this target hook returns always false. -- Target Hook: int TARGET_REGISTER_PRIORITY (int) A target hook which returns the register priority number to which - the register HARD_REGNO belongs to. The bigger the number, the + the register HARD_REGNO belongs to. The bigger the number, the more preferable the hard register usage (when all other conditions are the same). This hook can be used to prefer some hard register over others in LRA. For example, some x86-64 register @@ -30812,7 +30883,7 @@ the stack. **PNAME, tree *PTREE) This target hook is used in function `c_common_nodes_and_builtins' to iterate through the target specific builtin types for va_list. - The variable IDX is used as iterator. PNAME has to be a pointer to + The variable IDX is used as iterator. PNAME has to be a pointer to a `const char *' and PTREE a pointer to a `tree' typed variable. The arguments PNAME and PTREE are used to store the result of this macro and are set to the name of the va_list builtin type and its @@ -30827,7 +30898,7 @@ the stack. -- Target Hook: tree TARGET_CANONICAL_VA_LIST_TYPE (tree TYPE) This hook returns the va_list type of the calling convention - specified by the type of TYPE. If TYPE is not a valid va_list + specified by the type of TYPE. If TYPE is not a valid va_list type, it returns `NULL_TREE'. -- Target Hook: tree TARGET_GIMPLIFY_VA_ARG_EXPR (tree VALIST, tree @@ -32139,7 +32210,7 @@ This is about addressing modes. The autovectorizer, when vectorizing a load operation from an address ADDR that may be unaligned, will generate two vector loads - from the two aligned addresses around ADDR. It then generates a + from the two aligned addresses around ADDR. It then generates a `REALIGN_LOAD' operation to extract the relevant data from the two loaded vectors. The first two arguments to `REALIGN_LOAD', V1 and V2, are the two vectors, each of size VS, and the third argument, @@ -32250,7 +32321,7 @@ TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES (void) -- Target Hook: void TARGET_VECTORIZE_DESTROY_COST_DATA (void *DATA) This hook should release DATA and any related data structures - allocated by TARGET_VECTORIZE_INIT_COST. The default releases the + allocated by TARGET_VECTORIZE_INIT_COST. The default releases the accumulator. -- Target Hook: tree TARGET_VECTORIZE_BUILTIN_TM_LOAD (tree) @@ -32507,7 +32578,7 @@ File: gccint.info, Node: MODE_CC Condition Codes, Next: Cond Exec Macros, Pre are the left and right operands of the comparison, respectively. If OP0_PRESERVE_VALUE is `true' the implementation is not allowed to change the value of OP0 since the value might be used in RTXs - which aren't comparisons. E.g. the implementation is not allowed + which aren't comparisons. E.g. the implementation is not allowed to swap operands in that case. GCC will not assume that the comparison resulting from this macro @@ -32692,7 +32763,7 @@ on the target machine. Parameter SPEED_P is true when the branch in question should be optimized for speed. When it is false, `BRANCH_COST' should return a value optimal for code size rather than performance. - PREDICTABLE_P is true for well-predicted branches. On many + PREDICTABLE_P is true for well-predicted branches. On many architectures the `BRANCH_COST' can be reduced then. Here are additional macros which do not specify precise relative costs, @@ -33520,7 +33591,7 @@ target does not provide them. -- Target Hook: section * TARGET_ASM_TM_CLONE_TABLE_SECTION (void) Return the section that should be used for transactional memory - clone tables. + clone tables. -- Target Hook: section * TARGET_ASM_SELECT_RTX_SECTION (enum machine_mode MODE, rtx X, unsigned HOST_WIDE_INT ALIGN) @@ -36414,7 +36485,7 @@ File: gccint.info, Node: C++ ABI, Next: Named Address Spaces, Prev: PCH Targe in the same manner as `__cxa_atexit' to register C++ static destructors. This requires that `atexit'-registered functions in shared libraries are run in the correct order when the libraries - are unloaded. The default is to return false. + are unloaded. The default is to return false. -- Target Hook: void TARGET_CXX_ADJUST_CLASS_AT_DEFINITION (tree TYPE) TYPE is a C++ class (i.e., RECORD_TYPE or UNION_TYPE) that has @@ -37032,10 +37103,10 @@ Here are several miscellaneous parameters. -- Macro: TARGET_POSIX_IO Define this macro if the target supports the following POSIX file - functions, access, mkdir and file locking with fcntl / F_SETLKW. + functions, access, mkdir and file locking with fcntl / F_SETLKW. Defining `TARGET_POSIX_IO' will enable the test coverage code to use file locking when exiting a program, which avoids race - conditions if the program has forked. It will also create + conditions if the program has forked. It will also create directories at run-time for cross-profiling. -- Macro: MAX_CONDITIONAL_EXECUTE @@ -37186,7 +37257,7 @@ Here are several miscellaneous parameters. low-overhead loop, otherwise return a string explaining why doloop could not be applied. - Many targets use special registers for low-overhead looping. For + Many targets use special registers for low-overhead looping. For any instruction that clobbers these this function should return a string indicating the reason why the doloop could not be applied. By default, the RTL loop optimizer does not use a present doloop @@ -37208,10 +37279,10 @@ Here are several miscellaneous parameters. -- Target Hook: bool TARGET_CAN_FOLLOW_JUMP (const_rtx FOLLOWER, const_rtx FOLLOWEE) - FOLLOWER and FOLLOWEE are JUMP_INSN instructions; return true if - FOLLOWER may be modified to follow FOLLOWEE; false, if it can't. + FOLLOWER and FOLLOWEE are JUMP_INSN instructions; return true if + FOLLOWER may be modified to follow FOLLOWEE; false, if it can't. For example, on some targets, certain kinds of branches can't be - made to follow through a hot/cold partitioning. + made to follow through a hot/cold partitioning. -- Target Hook: bool TARGET_COMMUTATIVE_P (const_rtx X, int OUTER_CODE) This target hook returns `true' if X is considered to be @@ -37340,9 +37411,9 @@ Here are several miscellaneous parameters. -- Target Hook: unsigned TARGET_LOOP_UNROLL_ADJUST (unsigned NUNROLL, struct loop *LOOP) This target hook returns a new value for the number of times LOOP - should be unrolled. The parameter NUNROLL is the number of times - the loop is to be unrolled. The parameter LOOP is a pointer to the - loop, which is going to be checked for unrolling. This target hook + should be unrolled. The parameter NUNROLL is the number of times + the loop is to be unrolled. The parameter LOOP is a pointer to the + loop, which is going to be checked for unrolling. This target hook is required only when the target has special constraints like maximum number of memory accesses. @@ -37474,13 +37545,13 @@ Here are several miscellaneous parameters. -- Macro: TARGET_USE_JCR_SECTION This macro determines whether to use the JCR section to register - Java classes. By default, TARGET_USE_JCR_SECTION is defined to 1 + Java classes. By default, TARGET_USE_JCR_SECTION is defined to 1 if both SUPPORTS_WEAK and TARGET_HAVE_NAMED_SECTIONS are true, else 0. -- Macro: OBJC_JBLEN This macro determines the size of the objective C jump buffer for - the NeXT runtime. By default, OBJC_JBLEN is defined to an + the NeXT runtime. By default, OBJC_JBLEN is defined to an innocuous value. -- Macro: LIBGCC2_UNWIND_ATTRIBUTE @@ -37516,7 +37587,7 @@ Here are several miscellaneous parameters. synthesize a constant. If there is another constant already in a register that is close enough in value then it is preferable that the new constant is computed from this register using immediate - addition or subtraction. We accomplish this through CSE. Besides + addition or subtraction. We accomplish this through CSE. Besides the value of the constant we also add a lower and an upper constant anchor to the available expressions. These are then queried when encountering new constants. The anchors are computed @@ -37535,7 +37606,7 @@ Here are several miscellaneous parameters. -- Target Hook: unsigned HOST_WIDE_INT TARGET_MEMMODEL_CHECK (unsigned HOST_WIDE_INT VAL) - Validate target specific memory model mask bits. When NULL no + Validate target specific memory model mask bits. When NULL no target specific memory model bits are allowed. -- Target Hook: unsigned char TARGET_ATOMIC_TEST_AND_SET_TRUEVAL @@ -38600,7 +38671,7 @@ In these snippets, there is only one type `T', but there could be more. gt_pch_nx (&(tp->fld), op, cookie); } - Support for user-defined types is currently limited. The following + Support for user-defined types is currently limited. The following restrictions apply: 1. Type `TP' and all the argument types `T' must be marked with `GTY'. @@ -38697,9 +38768,9 @@ File: gccint.info, Node: Invoking the garbage collector, Next: Troubleshooting 22.5 How to invoke the garbage collector ======================================== -The GCC garbage collector GGC is only invoked explicitly. In contrast +The GCC garbage collector GGC is only invoked explicitly. In contrast with many other garbage collectors, it is not implicitly invoked by -allocation routines when a lot of memory has been consumed. So the only +allocation routines when a lot of memory has been consumed. So the only way to have GGC reclaim storage is to call the `ggc_collect' function explicitly. This call is an expensive operation, as it may have to scan the entire heap. Beware that local variables (on the GCC call @@ -38830,7 +38901,7 @@ this is enough: ---------------------------- Every plugin should export a function called `plugin_init' that is -called right after the plugin is loaded. This function is responsible +called right after the plugin is loaded. This function is responsible for registering all the callbacks required by the plugin and do any other required initialization. @@ -38872,7 +38943,7 @@ following structure: }; The function `plugin_default_version_check' takes two pointers to such -structure and compare them field by field. It can be used by the +structure and compare them field by field. It can be used by the plugin's `plugin_init' function. The version of GCC used to compile the plugin can be found in the @@ -38977,12 +39048,12 @@ File: gccint.info, Node: Plugins pass, Next: Plugins GC, Prev: Plugin API, U 23.3 Interacting with the pass manager ====================================== -There needs to be a way to add/reorder/remove passes dynamically. This +There needs to be a way to add/reorder/remove passes dynamically. This is useful for both analysis plugins (plugging in after a certain pass such as CFG or an IPA pass) and optimization plugins. Basic support for inserting new passes or replacing existing passes is -provided. A plugin registers a new pass with GCC by calling +provided. A plugin registers a new pass with GCC by calling `register_callback' with the `PLUGIN_PASS_MANAGER_SETUP' event and a pointer to a `struct register_pass_info' object defined as follows @@ -39031,19 +39102,19 @@ File: gccint.info, Node: Plugins GC, Next: Plugins description, Prev: Plugins =============================================== Some plugins may want to be informed when GGC (the GCC Garbage -Collector) is running. They can register callbacks for the +Collector) is running. They can register callbacks for the `PLUGIN_GGC_START' and `PLUGIN_GGC_END' events (for which the callback is called with a null `gcc_data') to be notified of the start or end of the GCC garbage collection. - Some plugins may need to have GGC mark additional data. This can be + Some plugins may need to have GGC mark additional data. This can be done by registering a callback (called with a null `gcc_data') for the `PLUGIN_GGC_MARKING' event. Such callbacks can call the `ggc_set_mark' routine, preferably through the `ggc_mark' macro (and conversely, these routines should usually not be used in plugins outside of the `PLUGIN_GGC_MARKING' event). - Some plugins may need to add extra GGC root tables, e.g. to handle + Some plugins may need to add extra GGC root tables, e.g. to handle their own `GTY'-ed data. This can be done with the `PLUGIN_REGISTER_GGC_ROOTS' pseudo-event with a null callback and the extra root table (of type `struct ggc_root_tab*') as `user_data'. @@ -39064,7 +39135,7 @@ File: gccint.info, Node: Plugins description, Next: Plugins attr, Prev: Plugi 23.5 Giving information about a plugin ====================================== -A plugin should give some information to the user about itself. This +A plugin should give some information to the user about itself. This uses the following structure: struct plugin_info @@ -39390,7 +39461,7 @@ dealing with the reading/writing of each section are described below. * Symbol table (`.gnu.lto_.symtab') This table replaces the ELF symbol table for functions and - variables represented in the LTO IL. Symbols used and exported by + variables represented in the LTO IL. Symbols used and exported by the optimized assembly code of "fat" objects might not match the ones used and exported by the intermediate code. This table is necessary because the intermediate code is less optimized and thus @@ -39716,7 +39787,7 @@ made. The linker plugin obtains the symbol resolution information which specifies which symbols provided by the claimed objects are bound from the rest of a binary being linked. - Currently, the linker plugin works only in combination with the Gold + Currently, the linker plugin works only in combination with the Gold linker, but a GNU ld implementation is under development. GCC is designed to be independent of the rest of the toolchain and @@ -40301,7 +40372,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -40329,7 +40400,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -40402,7 +40473,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -40416,7 +40487,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -40427,7 +40498,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -40454,19 +40525,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -40479,7 +40550,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -40952,7 +41023,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -40973,7 +41044,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -41020,7 +41091,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover Texts, -replace the "with...Texts." line with this: +replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -41980,7 +42051,7 @@ GCC version 4.1: and improvements. * Thomas Fitzsimmons for lots of upgrades to the gtk+ AWT and Cairo - 2D support. Lots of imageio framework additions, lots of AWT and + 2D support. Lots of imageio framework additions, lots of AWT and Free Swing bug fixes. * Jeroen Frijters for `ClassLoader' and nio cleanups, serialization @@ -42015,7 +42086,7 @@ GCC version 4.1: * Ito Kazumitsu for `NetworkInterface' implementation and updates. * Roman Kennke for `BoxLayout', `GrayFilter' and `SplitPane', plus - bug fixes all over. Lots of Free Swing work including styled text. + bug fixes all over. Lots of Free Swing work including styled text. * Simon Kitching for `String' cleanups and optimization suggestions. @@ -49400,373 +49471,373 @@ Concept Index  Tag Table: -Node: Top1828 -Node: Contributing4916 -Node: Portability5657 -Node: Interface7445 -Node: Libgcc10485 -Node: Integer library routines12326 -Node: Soft float library routines19168 -Node: Decimal float library routines31105 -Node: Fixed-point fractional library routines46862 -Node: Exception handling routines147260 -Node: Miscellaneous routines148367 -Node: Languages150487 -Node: Source Tree152036 -Node: Configure Terms152618 -Node: Top Level155576 -Node: gcc Directory159150 -Node: Subdirectories160100 -Node: Configuration162267 -Node: Config Fragments162987 -Node: System Config164216 -Node: Configuration Files165152 -Node: Build167977 -Node: Makefile168389 -Ref: Makefile-Footnote-1175192 -Ref: Makefile-Footnote-2175337 -Node: Library Files175409 -Node: Headers175971 -Node: Documentation178054 -Node: Texinfo Manuals178913 -Node: Man Page Generation181246 -Node: Miscellaneous Docs183161 -Node: Front End184555 -Node: Front End Directory188248 -Node: Front End Config189568 -Node: Front End Makefile192394 -Node: Back End196176 -Node: Testsuites199973 -Node: Test Idioms200904 -Node: Test Directives204301 -Node: Directives204828 -Node: Selectors215138 -Node: Effective-Target Keywords216496 -Ref: arm_neon_ok224055 -Ref: arm_neonv2_ok224213 -Ref: arm_neon_fp16_ok224385 -Node: Add Options234186 -Node: Require Support235383 -Node: Final Actions237890 -Node: Ada Tests243057 -Node: C Tests244389 -Node: libgcj Tests248812 -Node: LTO Testing249939 -Node: gcov Testing251586 -Node: profopt Testing254573 -Node: compat Testing256288 -Node: Torture Tests260528 -Node: Options262145 -Node: Option file format262585 -Node: Option properties269575 -Node: Passes282454 -Node: Parsing pass283198 -Node: Gimplification pass286728 -Node: Pass manager288561 -Node: Tree SSA passes290355 -Node: RTL passes312827 -Node: RTL325958 -Node: RTL Objects328146 -Node: RTL Classes332020 -Node: Accessors337018 -Node: Special Accessors339412 -Node: Flags345182 -Node: Machine Modes359906 -Node: Constants372218 -Node: Regs and Memory378948 -Node: Arithmetic396849 -Node: Comparisons406939 -Node: Bit-Fields411231 -Node: Vector Operations412783 -Node: Conversions414665 -Node: RTL Declarations419163 -Node: Side Effects419984 -Node: Incdec436584 -Node: Assembler439919 -Node: Debug Information441464 -Node: Insns442662 -Node: Calls469156 -Node: Sharing471749 -Node: Reading RTL474859 -Node: GENERIC475851 -Node: Deficiencies477724 -Node: Tree overview477965 -Node: Macros and Functions482092 -Node: Identifiers482917 -Node: Containers484528 -Node: Types485685 -Node: Declarations497781 -Node: Working with declarations498276 -Node: Internal structure503882 -Node: Current structure hierarchy504266 -Node: Adding new DECL node types506360 -Node: Attributes510433 -Node: Expression trees511678 -Node: Constant expressions513431 -Node: Storage References517650 -Node: Unary and Binary Expressions521169 -Node: Vectors541031 -Node: Statements545758 -Node: Basic Statements546278 -Node: Blocks550785 -Node: Statement Sequences552189 -Node: Empty Statements552522 -Node: Jumps553096 -Node: Cleanups553749 -Node: OpenMP555517 -Node: Functions561357 -Node: Function Basics561828 -Node: Function Properties565513 -Node: Language-dependent trees568295 -Node: C and C++ Trees569181 -Node: Types for C++572085 -Node: Namespaces577063 -Node: Classes580170 -Node: Functions for C++585248 -Node: Statements for C++591501 -Node: C++ Expressions599549 -Node: Java Trees601050 -Node: GIMPLE601163 -Node: Tuple representation604784 -Node: GIMPLE instruction set613060 -Node: GIMPLE Exception Handling614728 -Node: Temporaries616642 -Ref: Temporaries-Footnote-1617957 -Node: Operands618020 -Node: Compound Expressions618782 -Node: Compound Lvalues619016 -Node: Conditional Expressions619778 -Node: Logical Operators620436 -Node: Manipulating GIMPLE statements627193 -Node: Tuple specific accessors633127 -Node: `GIMPLE_ASM'633946 -Node: `GIMPLE_ASSIGN'636579 -Node: `GIMPLE_BIND'640685 -Node: `GIMPLE_CALL'642492 -Node: `GIMPLE_CATCH'646762 -Node: `GIMPLE_COND'647906 -Node: `GIMPLE_DEBUG'650694 -Node: `GIMPLE_EH_FILTER'654077 -Node: `GIMPLE_LABEL'655565 -Node: `GIMPLE_NOP'656540 -Node: `GIMPLE_OMP_ATOMIC_LOAD'656909 -Node: `GIMPLE_OMP_ATOMIC_STORE'657819 -Node: `GIMPLE_OMP_CONTINUE'658458 -Node: `GIMPLE_OMP_CRITICAL'659808 -Node: `GIMPLE_OMP_FOR'660745 -Node: `GIMPLE_OMP_MASTER'664260 -Node: `GIMPLE_OMP_ORDERED'664643 -Node: `GIMPLE_OMP_PARALLEL'665043 -Node: `GIMPLE_OMP_RETURN'667815 -Node: `GIMPLE_OMP_SECTION'668465 -Node: `GIMPLE_OMP_SECTIONS'669131 -Node: `GIMPLE_OMP_SINGLE'670737 -Node: `GIMPLE_PHI'671674 -Node: `GIMPLE_RESX'672960 -Node: `GIMPLE_RETURN'673679 -Node: `GIMPLE_SWITCH'674247 -Node: `GIMPLE_TRY'676047 -Node: `GIMPLE_WITH_CLEANUP_EXPR'677837 -Node: GIMPLE sequences678720 -Node: Sequence iterators681926 -Node: Adding a new GIMPLE statement code690382 -Node: Statement and operand traversals691658 -Node: Tree SSA694258 -Node: Annotations696044 -Node: SSA Operands696570 -Node: SSA711101 -Node: Alias analysis723221 -Node: Memory model727001 -Node: Loop Analysis and Representation728364 -Node: Loop representation729545 -Node: Loop querying736465 -Node: Loop manipulation739298 -Node: LCSSA741666 -Node: Scalar evolutions743738 -Node: loop-iv746982 -Node: Number of iterations748908 -Node: Dependency analysis751717 -Node: Lambda758085 -Node: Omega759756 -Node: Control Flow761321 -Node: Basic Blocks763087 -Node: Edges768378 -Node: Profile information777010 -Node: Maintaining the CFG781694 -Node: Liveness information787556 -Node: Machine Desc789682 -Node: Overview792245 -Node: Patterns794286 -Node: Example797724 -Node: RTL Template799159 -Node: Output Template809814 -Node: Output Statement813779 -Node: Predicates818118 -Node: Machine-Independent Predicates821036 -Node: Defining Predicates825981 -Node: Constraints831946 -Node: Simple Constraints833428 -Node: Multi-Alternative846284 -Node: Class Preferences849125 -Node: Modifiers850017 -Node: Machine Constraints854263 -Node: Disable Insn Alternatives904313 -Node: Define Constraints907215 -Node: C Constraint Interface914002 -Node: Standard Names917643 -Ref: shift patterns940194 -Ref: prologue instruction pattern985134 -Ref: window_save instruction pattern985627 -Ref: epilogue instruction pattern985902 -Node: Pattern Ordering1003473 -Node: Dependent Patterns1004709 -Node: Jump Patterns1006329 -Ref: Jump Patterns-Footnote-11008473 -Node: Looping Patterns1008519 -Node: Insn Canonicalizations1013247 -Node: Expander Definitions1017838 -Node: Insn Splitting1026050 -Node: Including Patterns1035652 -Node: Peephole Definitions1037432 -Node: define_peephole1038685 -Node: define_peephole21045016 -Node: Insn Attributes1048083 -Node: Defining Attributes1049189 -Ref: define_enum_attr1052400 -Node: Expressions1053435 -Node: Tagging Insns1060184 -Node: Attr Example1064537 -Node: Insn Lengths1066911 -Node: Constant Attributes1069970 -Node: Delay Slots1071139 -Node: Processor pipeline description1074363 -Ref: Processor pipeline description-Footnote-11093176 -Node: Conditional Execution1093498 -Node: Define Subst1096560 -Node: Define Subst Example1098594 -Node: Define Subst Pattern Matching1101588 -Node: Define Subst Output Template1102813 -Node: Constant Definitions1104883 -Ref: define_enum1108665 -Node: Iterators1109153 -Node: Mode Iterators1109731 -Node: Defining Mode Iterators1110709 -Node: Substitutions1112203 -Node: Examples1114444 -Node: Code Iterators1115892 -Node: Int Iterators1118171 -Node: Subst Iterators1120629 -Node: Target Macros1122321 -Node: Target Structure1125409 -Node: Driver1127524 -Node: Run-time Target1146307 -Node: Per-Function Data1155460 -Node: Storage Layout1158225 -Node: Type Layout1184300 -Node: Registers1199627 -Node: Register Basics1200601 -Node: Allocation Order1206106 -Node: Values in Registers1208552 -Node: Leaf Functions1216041 -Node: Stack Registers1218899 -Node: Register Classes1220171 -Node: Old Constraints1250176 -Node: Stack and Calling1257328 -Node: Frame Layout1257862 -Node: Exception Handling1268742 -Node: Stack Checking1274964 -Node: Frame Registers1279777 -Node: Elimination1288036 -Node: Stack Arguments1292265 -Node: Register Arguments1299127 -Node: Scalar Return1319443 -Node: Aggregate Return1325529 -Node: Caller Saves1329739 -Node: Function Entry1330917 -Node: Profiling1342021 -Node: Tail Calls1343720 -Node: Stack Smashing Protection1345623 -Node: Varargs1347251 -Node: Trampolines1353947 -Node: Library Calls1359990 -Node: Addressing Modes1364929 -Node: Anchored Addresses1384963 -Node: Condition Code1387612 -Node: CC0 Condition Codes1389741 -Node: MODE_CC Condition Codes1392987 -Node: Cond Exec Macros1399508 -Node: Costs1399854 -Node: Scheduling1416323 -Node: Sections1435729 -Node: PIC1451427 -Node: Assembler Format1453487 -Node: File Framework1454625 -Ref: TARGET_HAVE_SWITCHABLE_BSS_SECTIONS1461566 -Node: Data Output1464831 -Node: Uninitialized Data1472607 -Node: Label Output1477618 -Node: Initialization1500586 -Node: Macros for Initialization1506548 -Node: Instruction Output1513271 -Node: Dispatch Tables1523773 -Node: Exception Region Output1528151 -Node: Alignment Output1534834 -Node: Debugging Info1539379 -Node: All Debuggers1540049 -Node: DBX Options1542904 -Node: DBX Hooks1548353 -Node: File Names and DBX1549662 -Node: SDB and DWARF1551774 -Node: VMS Debug1557846 -Node: Floating Point1558433 -Node: Mode Switching1562909 -Node: Target Attributes1566905 -Node: Emulated TLS1575219 -Node: MIPS Coprocessors1578609 -Node: PCH Target1579906 -Node: C++ ABI1581748 -Node: Named Address Spaces1586540 -Node: Misc1591479 -Ref: TARGET_SHIFT_TRUNCATION_MASK1598221 -Node: Host Config1643387 -Node: Host Common1644455 -Node: Filesystem1646834 -Node: Host Misc1650949 -Node: Fragments1653398 -Node: Target Fragment1654593 -Node: Host Fragment1665226 -Node: Collect21665466 -Node: Header Dirs1668102 -Node: Type Information1669525 -Node: GTY Options1672748 -Node: User GC1687069 -Node: GGC Roots1690796 -Node: Files1691512 -Node: Invoking the garbage collector1694219 -Node: Troubleshooting1695722 -Node: Plugins1696798 -Node: Plugins loading1697916 -Node: Plugin API1698785 -Node: Plugins pass1705814 -Node: Plugins GC1707783 -Node: Plugins description1709443 -Node: Plugins attr1709978 -Node: Plugins recording1711863 -Node: Plugins gate1712713 -Node: Plugins tracking1713304 -Node: Plugins building1713892 -Node: LTO1715678 -Node: LTO Overview1716539 -Node: LTO object file layout1722371 -Node: IPA1727003 -Node: WHOPR1735968 -Node: Internal flags1740659 -Node: Funding1741871 -Node: GNU Project1744354 -Node: Copying1745003 -Node: GNU Free Documentation License1782534 -Node: Contributors1807674 -Node: Option Index1845079 -Node: Concept Index1845883 +Node: Top1842 +Node: Contributing4930 +Node: Portability5671 +Node: Interface7459 +Node: Libgcc10499 +Node: Integer library routines12340 +Node: Soft float library routines19182 +Node: Decimal float library routines31119 +Node: Fixed-point fractional library routines46876 +Node: Exception handling routines147274 +Node: Miscellaneous routines148381 +Node: Languages150501 +Node: Source Tree152050 +Node: Configure Terms152632 +Node: Top Level155590 +Node: gcc Directory159164 +Node: Subdirectories160114 +Node: Configuration162281 +Node: Config Fragments163001 +Node: System Config164230 +Node: Configuration Files165166 +Node: Build167991 +Node: Makefile168403 +Ref: Makefile-Footnote-1175206 +Ref: Makefile-Footnote-2175351 +Node: Library Files175423 +Node: Headers175985 +Node: Documentation178068 +Node: Texinfo Manuals178927 +Node: Man Page Generation181260 +Node: Miscellaneous Docs183175 +Node: Front End184569 +Node: Front End Directory188262 +Node: Front End Config189582 +Node: Front End Makefile192408 +Node: Back End196190 +Node: Testsuites199987 +Node: Test Idioms200918 +Node: Test Directives204315 +Node: Directives204842 +Node: Selectors215152 +Node: Effective-Target Keywords216510 +Ref: arm_neon_ok224069 +Ref: arm_neonv2_ok224227 +Ref: arm_neon_fp16_ok224399 +Node: Add Options234770 +Node: Require Support235967 +Node: Final Actions238474 +Node: Ada Tests243641 +Node: C Tests244973 +Node: libgcj Tests249396 +Node: LTO Testing250523 +Node: gcov Testing252170 +Node: profopt Testing255157 +Node: compat Testing256872 +Node: Torture Tests261112 +Node: Options262729 +Node: Option file format263169 +Node: Option properties270159 +Node: Passes283038 +Node: Parsing pass283782 +Node: Gimplification pass287312 +Node: Pass manager289145 +Node: Tree SSA passes290939 +Node: RTL passes313411 +Node: RTL326542 +Node: RTL Objects328730 +Node: RTL Classes332604 +Node: Accessors337602 +Node: Special Accessors339996 +Node: Flags345766 +Node: Machine Modes360490 +Node: Constants372802 +Node: Regs and Memory379532 +Node: Arithmetic397433 +Node: Comparisons407523 +Node: Bit-Fields411815 +Node: Vector Operations413367 +Node: Conversions415249 +Node: RTL Declarations419747 +Node: Side Effects420568 +Node: Incdec437168 +Node: Assembler440503 +Node: Debug Information442048 +Node: Insns443246 +Node: Calls469740 +Node: Sharing472333 +Node: Reading RTL475443 +Node: GENERIC476435 +Node: Deficiencies478308 +Node: Tree overview478549 +Node: Macros and Functions482676 +Node: Identifiers483501 +Node: Containers485112 +Node: Types486269 +Node: Declarations498365 +Node: Working with declarations498860 +Node: Internal structure504466 +Node: Current structure hierarchy504850 +Node: Adding new DECL node types506944 +Node: Attributes511017 +Node: Expression trees512262 +Node: Constant expressions514015 +Node: Storage References518234 +Node: Unary and Binary Expressions521753 +Node: Vectors541615 +Node: Statements546342 +Node: Basic Statements546862 +Node: Blocks551369 +Node: Statement Sequences552773 +Node: Empty Statements553106 +Node: Jumps553680 +Node: Cleanups554333 +Node: OpenMP556101 +Node: Functions561941 +Node: Function Basics562412 +Node: Function Properties566097 +Node: Language-dependent trees568879 +Node: C and C++ Trees569765 +Node: Types for C++572669 +Node: Namespaces577647 +Node: Classes580754 +Node: Functions for C++585832 +Node: Statements for C++592085 +Node: C++ Expressions600133 +Node: Java Trees601634 +Node: GIMPLE601747 +Node: Tuple representation605368 +Node: GIMPLE instruction set613644 +Node: GIMPLE Exception Handling615312 +Node: Temporaries617226 +Ref: Temporaries-Footnote-1618541 +Node: Operands618604 +Node: Compound Expressions619366 +Node: Compound Lvalues619600 +Node: Conditional Expressions620362 +Node: Logical Operators621020 +Node: Manipulating GIMPLE statements627777 +Node: Tuple specific accessors633711 +Node: `GIMPLE_ASM'634530 +Node: `GIMPLE_ASSIGN'637163 +Node: `GIMPLE_BIND'641269 +Node: `GIMPLE_CALL'643076 +Node: `GIMPLE_CATCH'647346 +Node: `GIMPLE_COND'648490 +Node: `GIMPLE_DEBUG'651278 +Node: `GIMPLE_EH_FILTER'654661 +Node: `GIMPLE_LABEL'656149 +Node: `GIMPLE_NOP'657124 +Node: `GIMPLE_OMP_ATOMIC_LOAD'657493 +Node: `GIMPLE_OMP_ATOMIC_STORE'658403 +Node: `GIMPLE_OMP_CONTINUE'659042 +Node: `GIMPLE_OMP_CRITICAL'660392 +Node: `GIMPLE_OMP_FOR'661329 +Node: `GIMPLE_OMP_MASTER'664844 +Node: `GIMPLE_OMP_ORDERED'665227 +Node: `GIMPLE_OMP_PARALLEL'665627 +Node: `GIMPLE_OMP_RETURN'668399 +Node: `GIMPLE_OMP_SECTION'669049 +Node: `GIMPLE_OMP_SECTIONS'669715 +Node: `GIMPLE_OMP_SINGLE'671321 +Node: `GIMPLE_PHI'672258 +Node: `GIMPLE_RESX'673544 +Node: `GIMPLE_RETURN'674263 +Node: `GIMPLE_SWITCH'674831 +Node: `GIMPLE_TRY'676631 +Node: `GIMPLE_WITH_CLEANUP_EXPR'678421 +Node: GIMPLE sequences679304 +Node: Sequence iterators682510 +Node: Adding a new GIMPLE statement code690966 +Node: Statement and operand traversals692242 +Node: Tree SSA694842 +Node: Annotations696628 +Node: SSA Operands697154 +Node: SSA711685 +Node: Alias analysis723805 +Node: Memory model727585 +Node: Loop Analysis and Representation728948 +Node: Loop representation730129 +Node: Loop querying737049 +Node: Loop manipulation739882 +Node: LCSSA742250 +Node: Scalar evolutions744322 +Node: loop-iv747566 +Node: Number of iterations749492 +Node: Dependency analysis752301 +Node: Lambda758669 +Node: Omega760340 +Node: Control Flow761905 +Node: Basic Blocks763671 +Node: Edges768962 +Node: Profile information777594 +Node: Maintaining the CFG782278 +Node: Liveness information788140 +Node: Machine Desc790266 +Node: Overview792829 +Node: Patterns794870 +Node: Example798308 +Node: RTL Template799743 +Node: Output Template810398 +Node: Output Statement814363 +Node: Predicates818702 +Node: Machine-Independent Predicates821620 +Node: Defining Predicates826565 +Node: Constraints832530 +Node: Simple Constraints834012 +Node: Multi-Alternative846868 +Node: Class Preferences849709 +Node: Modifiers850601 +Node: Machine Constraints854847 +Node: Disable Insn Alternatives906156 +Node: Define Constraints909058 +Node: C Constraint Interface915845 +Node: Standard Names919486 +Ref: shift patterns942037 +Ref: prologue instruction pattern986977 +Ref: window_save instruction pattern987470 +Ref: epilogue instruction pattern987745 +Node: Pattern Ordering1005316 +Node: Dependent Patterns1006552 +Node: Jump Patterns1008172 +Ref: Jump Patterns-Footnote-11010316 +Node: Looping Patterns1010362 +Node: Insn Canonicalizations1015090 +Node: Expander Definitions1019681 +Node: Insn Splitting1027893 +Node: Including Patterns1037495 +Node: Peephole Definitions1039275 +Node: define_peephole1040528 +Node: define_peephole21046859 +Node: Insn Attributes1049926 +Node: Defining Attributes1051032 +Ref: define_enum_attr1054243 +Node: Expressions1055278 +Node: Tagging Insns1062027 +Node: Attr Example1066380 +Node: Insn Lengths1068754 +Node: Constant Attributes1071813 +Node: Delay Slots1072982 +Node: Processor pipeline description1076206 +Ref: Processor pipeline description-Footnote-11095019 +Node: Conditional Execution1095341 +Node: Define Subst1098403 +Node: Define Subst Example1100437 +Node: Define Subst Pattern Matching1103431 +Node: Define Subst Output Template1104656 +Node: Constant Definitions1106726 +Ref: define_enum1110508 +Node: Iterators1110996 +Node: Mode Iterators1111574 +Node: Defining Mode Iterators1112552 +Node: Substitutions1114046 +Node: Examples1116287 +Node: Code Iterators1117735 +Node: Int Iterators1120014 +Node: Subst Iterators1122472 +Node: Target Macros1124164 +Node: Target Structure1127252 +Node: Driver1129367 +Node: Run-time Target1148150 +Node: Per-Function Data1157303 +Node: Storage Layout1160068 +Node: Type Layout1186143 +Node: Registers1201470 +Node: Register Basics1202444 +Node: Allocation Order1207949 +Node: Values in Registers1210395 +Node: Leaf Functions1217884 +Node: Stack Registers1220742 +Node: Register Classes1222014 +Node: Old Constraints1252019 +Node: Stack and Calling1259171 +Node: Frame Layout1259705 +Node: Exception Handling1270585 +Node: Stack Checking1276807 +Node: Frame Registers1281620 +Node: Elimination1289879 +Node: Stack Arguments1294108 +Node: Register Arguments1300970 +Node: Scalar Return1321286 +Node: Aggregate Return1327372 +Node: Caller Saves1331582 +Node: Function Entry1332760 +Node: Profiling1343864 +Node: Tail Calls1345563 +Node: Stack Smashing Protection1347466 +Node: Varargs1349094 +Node: Trampolines1355790 +Node: Library Calls1361833 +Node: Addressing Modes1366772 +Node: Anchored Addresses1386806 +Node: Condition Code1389455 +Node: CC0 Condition Codes1391584 +Node: MODE_CC Condition Codes1394830 +Node: Cond Exec Macros1401351 +Node: Costs1401697 +Node: Scheduling1418166 +Node: Sections1437572 +Node: PIC1453270 +Node: Assembler Format1455330 +Node: File Framework1456468 +Ref: TARGET_HAVE_SWITCHABLE_BSS_SECTIONS1463409 +Node: Data Output1466674 +Node: Uninitialized Data1474450 +Node: Label Output1479461 +Node: Initialization1502429 +Node: Macros for Initialization1508391 +Node: Instruction Output1515114 +Node: Dispatch Tables1525616 +Node: Exception Region Output1529994 +Node: Alignment Output1536677 +Node: Debugging Info1541222 +Node: All Debuggers1541892 +Node: DBX Options1544747 +Node: DBX Hooks1550196 +Node: File Names and DBX1551505 +Node: SDB and DWARF1553617 +Node: VMS Debug1559689 +Node: Floating Point1560276 +Node: Mode Switching1564752 +Node: Target Attributes1568748 +Node: Emulated TLS1577062 +Node: MIPS Coprocessors1580452 +Node: PCH Target1581749 +Node: C++ ABI1583591 +Node: Named Address Spaces1588383 +Node: Misc1593322 +Ref: TARGET_SHIFT_TRUNCATION_MASK1600064 +Node: Host Config1645230 +Node: Host Common1646298 +Node: Filesystem1648677 +Node: Host Misc1652792 +Node: Fragments1655241 +Node: Target Fragment1656436 +Node: Host Fragment1667069 +Node: Collect21667309 +Node: Header Dirs1669945 +Node: Type Information1671368 +Node: GTY Options1674591 +Node: User GC1688912 +Node: GGC Roots1692639 +Node: Files1693355 +Node: Invoking the garbage collector1696062 +Node: Troubleshooting1697565 +Node: Plugins1698641 +Node: Plugins loading1699759 +Node: Plugin API1700628 +Node: Plugins pass1707657 +Node: Plugins GC1709626 +Node: Plugins description1711286 +Node: Plugins attr1711821 +Node: Plugins recording1713706 +Node: Plugins gate1714556 +Node: Plugins tracking1715147 +Node: Plugins building1715735 +Node: LTO1717521 +Node: LTO Overview1718382 +Node: LTO object file layout1724214 +Node: IPA1728846 +Node: WHOPR1737811 +Node: Internal flags1742502 +Node: Funding1743714 +Node: GNU Project1746197 +Node: Copying1746846 +Node: GNU Free Documentation License1784377 +Node: Contributors1809517 +Node: Option Index1846922 +Node: Concept Index1847726  End Tag Table diff --git a/gcc-4.8/gcc/doc/gcj-dbtool.1 b/gcc-4.8/gcc/doc/gcj-dbtool.1 index 95332141f..e3ce1acb1 100644 --- a/gcc-4.8/gcc/doc/gcj-dbtool.1 +++ b/gcc-4.8/gcc/doc/gcj-dbtool.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCJ-DBTOOL 1" -.TH GCJ-DBTOOL 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCJ-DBTOOL 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/gcj.1 b/gcc-4.8/gcc/doc/gcj.1 index 1de730eee..2d7c4e612 100644 --- a/gcc-4.8/gcc/doc/gcj.1 +++ b/gcc-4.8/gcc/doc/gcj.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCJ 1" -.TH GCJ 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCJ 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -147,7 +155,7 @@ of the same options as gcc. This manual only documents the options specific to \fBgcj\fR. .SH "OPTIONS" .IX Header "OPTIONS" -.SS "Input and output files" +.Sh "Input and output files" .IX Subsection "Input and output files" A \fBgcj\fR command is like a \fBgcc\fR command, in that it consists of a number of options and file names. The following kinds @@ -195,7 +203,7 @@ but not when using \f(CW\*(C`\-C\*(C'\fR or \f(CW\*(C`\-\-resource\*(C'\fR. (This is an extension beyond the what plain \fBgcc\fR allows.) (If more than one input file is specified, all must currently be \f(CW\*(C`.java\*(C'\fR files, though we hope to fix this.) -.SS "Input Options" +.Sh "Input Options" .IX Subsection "Input Options" \&\fBgcj\fR has options to control where it looks to find files it needs. For instance, \fBgcj\fR might need to load a class that is referenced @@ -269,7 +277,7 @@ issue an error if it isn't found. .IX Item "-fsource=VERSION" This option is used to choose the source version accepted by \&\fBgcj\fR. The default is \fB1.5\fR. -.SS "Encodings" +.Sh "Encodings" .IX Subsection "Encodings" The Java programming language uses Unicode throughout. In an effort to integrate well with other locales, \fBgcj\fR allows \fI.java\fR files @@ -292,7 +300,7 @@ to platform (since they are not standardized anywhere). However, \&\fBgcj\fR implements the encoding named \fB\s-1UTF\-8\s0\fR internally, so if you choose to use this for your source files you can be assured that it will work on every host. -.SS "Warnings" +.Sh "Warnings" .IX Subsection "Warnings" \&\fBgcj\fR implements several warnings. As with other generic \&\fBgcc\fR warnings, if an option of the form \f(CW\*(C`\-Wfoo\*(C'\fR enables a @@ -322,7 +330,7 @@ This is the same as \fBgcc\fR's \f(CW\*(C`\-Wunused\*(C'\fR. .IX Item "-Wall" This is the same as \f(CW\*(C`\-Wredundant\-modifiers \-Wextraneous\-semicolon \&\-Wunused\*(C'\fR. -.SS "Linking" +.Sh "Linking" .IX Subsection "Linking" To turn a Java application into an executable program, you need to link it with the needed libraries, just as for C or \*(C+. @@ -383,7 +391,7 @@ link time, it can omit the referred to classes. The result is usually runtime. Caution must be used when using this option. For more details see: <\fBhttp://gcc.gnu.org/wiki/Statically%20linking%20libgcj\fR> -.SS "Code Generation" +.Sh "Code Generation" .IX Subsection "Code Generation" In addition to the many \fBgcc\fR options controlling code generation, \&\fBgcj\fR has several options specific to itself. @@ -517,7 +525,7 @@ with \f(CW\*(C`\-freduced\-reflection\*(C'\fR. a \f(CW\*(C`SecurityManager\*(C'\fR may not work properly. Also calling \&\f(CW\*(C`Class.forName()\*(C'\fR may fail if the calling method has no reflection meta-data. -.SS "Configure-time Options" +.Sh "Configure-time Options" .IX Subsection "Configure-time Options" Some \fBgcj\fR code generations options affect the resulting \s-1ABI\s0, and so can only be meaningfully given when \f(CW\*(C`libgcj\*(C'\fR, the runtime diff --git a/gcc-4.8/gcc/doc/gcj.info b/gcc-4.8/gcc/doc/gcj.info index 5d089f3f8..a892e6757 100644 --- a/gcc-4.8/gcc/doc/gcj.info +++ b/gcc-4.8/gcc/doc/gcj.info @@ -1,5 +1,5 @@ -This is doc/gcj.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/java/gcj.texi. +This is doc/gcj.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/java/gcj.texi. Copyright (C) 2001-2013 Free Software Foundation, Inc. @@ -570,7 +570,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -598,7 +598,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -671,7 +671,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -685,7 +685,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -696,7 +696,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -723,19 +723,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -748,7 +748,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -1221,7 +1221,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -1242,7 +1242,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -1289,7 +1289,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -1679,7 +1679,7 @@ In addition to the many `gcc' options controlling code generation, Note that, at present, `-findirect-dispatch' can only be used when compiling `.class' files. It will not work when compiling from source. CNI also does not yet work with the binary compatibility - ABI. These restrictions will be lifted in some future release. + ABI. These restrictions will be lifted in some future release. However, if you compile CNI code with the standard ABI, you can call it from code built with the binary compatibility ABI. @@ -1701,7 +1701,7 @@ In addition to the many `gcc' options controlling code generation, environment. When set all meta-data except for that which is needed to obtain correct runtime semantics is eliminated. - For code that does not use reflection (i.e. serialization, RMI, + For code that does not use reflection (i.e. serialization, RMI, CORBA or call methods in the `java.lang.reflect' package), `-freduced-reflection' will result in proper operation with a savings in executable code size. @@ -1773,8 +1773,8 @@ against us. So, there are caveats to using `gcj'. * Menu: -* Limitations:: -* Extensions:: +* Limitations:: +* Extensions::  File: gcj.info, Node: Limitations, Next: Extensions, Up: Compatibility @@ -1866,7 +1866,7 @@ have been added are to facilitate this functionality. particular `GCJ_PROPERTIES' holds a list of assignments to global properties, such as would be set with the `-D' option to `java'. For instance, `java.compiler=gcj' is a valid (but currently - meaningless) setting. + meaningless) setting.  @@ -1959,7 +1959,7 @@ been compiled and put into a shared library on the class path. Equivalent to `-Xmx'. `-noverify' - Do not verify compliance of bytecode with the VM specification. In + Do not verify compliance of bytecode with the VM specification. In addition, this option disables type verification which is otherwise performed on BC-ABI compiled code. @@ -2492,7 +2492,7 @@ C++ pointer, so for instance a Java `java.lang.String' becomes, in C++, Every Java class or interface has a corresponding `Class' instance. These can be accessed in CNI via the static `class$' field of a class. The `class$' field is of type `Class' (and not `Class *'), so you will -typically take the address of it. +typically take the address of it. Here is how you can refer to the class of `String', which in Java would be written `String.class': @@ -3139,13 +3139,13 @@ File: gcj.info, Node: Invocation, Next: Reflection, Prev: Synchronization, U ================ CNI permits C++ applications to make calls into Java classes, in -addition to allowing Java code to call into C++. Several functions, +addition to allowing Java code to call into C++. Several functions, known as the "invocation API", are provided to support this. -- Function: jint JvCreateJavaVM (JvVMInitArgs* VM_ARGS) - Initializes the Java runtime. This function performs essential + Initializes the Java runtime. This function performs essential initialization of the threads interface, garbage collector, - exception handling and other key aspects of the runtime. It must + exception handling and other key aspects of the runtime. It must be called once by an application with a non-Java `main()' function, before any other Java or CNI calls are made. It is safe, but not recommended, to call `JvCreateJavaVM()' more than @@ -3200,9 +3200,9 @@ known as the "invocation API", are provided to support this. thread object is returned. -- Function: jint JvDetachCurrentThread () - Unregisters a thread from the Java runtime. This should be called + Unregisters a thread from the Java runtime. This should be called by threads that were attached using `JvAttachCurrentThread()', - after they have finished making calls to Java code. This ensures + after they have finished making calls to Java code. This ensures that any resources associated with the thread become eligible for garbage collection. This function returns `0' upon success, or `-1' if the current thread is not attached. @@ -3212,7 +3212,7 @@ known as the "invocation API", are provided to support this. If an exception is thrown from Java code called using the invocation API, and no handler for the exception can be found, the runtime will -abort the application. In order to make the application more robust, it +abort the application. In order to make the application more robust, it is recommended that code which uses the invocation API be wrapped by a top-level try/catch block that catches all Java exceptions. @@ -3506,7 +3506,7 @@ normally not be found in other core libraries for the java language. `java.net.PlainDatagramSocketImpl'. `gnu.gcj.progname' - The class or binary name that was used to invoke the program. This + The class or binary name that was used to invoke the program. This will be the name of the "main" class in the case where the `gij' front end is used, or the program binary name in the case where an application is compiled to a native binary. @@ -3519,7 +3519,7 @@ normally not be found in other core libraries for the java language. `gnu.gcj.runtime.NameFinder.use_addr2line' Whether an external process, `addr2line', should be used to - determine line number information when tracing the stack. Setting + determine line number information when tracing the stack. Setting this to `false' may suppress line numbers when printing stack traces and when using the java.util.logging infrastructure. However, performance may improve significantly for applications @@ -3641,51 +3641,51 @@ Index  Tag Table: -Node: Top2715 -Node: Copying4134 -Node: GNU Free Documentation License41684 -Node: Invoking gcj66827 -Node: Input and output files67590 -Node: Input Options69116 -Node: Encodings72390 -Node: Warnings73596 -Node: Linking74709 -Node: Code Generation77648 -Node: Configure-time Options84428 -Node: Compatibility86168 -Node: Limitations86652 -Node: Extensions88234 -Node: Invoking jcf-dump91328 -Node: Invoking gij92273 -Node: Invoking gcj-dbtool95524 -Node: Invoking jv-convert97990 -Node: Invoking grmic99069 -Node: Invoking gc-analyze100455 -Node: Invoking aot-compile101896 -Node: Invoking rebuild-gcj-db102845 -Node: About CNI103155 -Node: Basic concepts104614 -Node: Packages107510 -Node: Primitive types109838 -Node: Reference types111516 -Node: Interfaces112605 -Node: Objects and Classes113516 -Node: Class Initialization115711 -Node: Object allocation118053 -Node: Memory allocation118843 -Node: Arrays119475 -Node: Methods122285 -Node: Strings125106 -Node: Mixing with C++126610 -Node: Exception Handling130081 -Node: Synchronization131715 -Node: Invocation133705 -Node: Reflection138641 -Node: System properties139102 -Node: Standard Properties139979 -Node: GNU Classpath Properties144411 -Node: libgcj Runtime Properties145458 -Node: Resources149960 -Node: Index150774 +Node: Top2729 +Node: Copying4148 +Node: GNU Free Documentation License41698 +Node: Invoking gcj66841 +Node: Input and output files67604 +Node: Input Options69130 +Node: Encodings72404 +Node: Warnings73610 +Node: Linking74723 +Node: Code Generation77662 +Node: Configure-time Options84442 +Node: Compatibility86182 +Node: Limitations86666 +Node: Extensions88248 +Node: Invoking jcf-dump91342 +Node: Invoking gij92287 +Node: Invoking gcj-dbtool95538 +Node: Invoking jv-convert98004 +Node: Invoking grmic99083 +Node: Invoking gc-analyze100469 +Node: Invoking aot-compile101910 +Node: Invoking rebuild-gcj-db102859 +Node: About CNI103169 +Node: Basic concepts104628 +Node: Packages107524 +Node: Primitive types109852 +Node: Reference types111530 +Node: Interfaces112619 +Node: Objects and Classes113530 +Node: Class Initialization115725 +Node: Object allocation118067 +Node: Memory allocation118857 +Node: Arrays119489 +Node: Methods122299 +Node: Strings125120 +Node: Mixing with C++126624 +Node: Exception Handling130095 +Node: Synchronization131729 +Node: Invocation133719 +Node: Reflection138655 +Node: System properties139116 +Node: Standard Properties139993 +Node: GNU Classpath Properties144425 +Node: libgcj Runtime Properties145472 +Node: Resources149974 +Node: Index150788  End Tag Table diff --git a/gcc-4.8/gcc/doc/gcov.1 b/gcc-4.8/gcc/doc/gcov.1 index 145b71a34..27cb28aaf 100644 --- a/gcc-4.8/gcc/doc/gcov.1 +++ b/gcc-4.8/gcc/doc/gcov.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GCOV 1" -.TH GCOV 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GCOV 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -579,7 +587,7 @@ profiling code first attempts to read in an existing \fI.gcda\fR file; if the file doesn't match the executable (differing number of basic block counts) it will ignore the contents of the file. It then adds in the new execution counts and finally writes the data to the file. -.SS "Using \fBgcov\fP with \s-1GCC\s0 Optimization" +.Sh "Using \fBgcov\fP with \s-1GCC\s0 Optimization" .IX Subsection "Using gcov with GCC Optimization" If you plan to use \fBgcov\fR to help optimize your code, you must first compile your program with two special \s-1GCC\s0 options: diff --git a/gcc-4.8/gcc/doc/gfdl.7 b/gcc-4.8/gcc/doc/gfdl.7 index 46f4005fd..dc99bad35 100644 --- a/gcc-4.8/gcc/doc/gfdl.7 +++ b/gcc-4.8/gcc/doc/gfdl.7 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GFDL 7" -.TH GFDL 7 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GFDL 7 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -133,9 +141,9 @@ gfdl \- GNU Free Documentation License .SH "DESCRIPTION" .IX Header "DESCRIPTION" -.SS "\s-1GNU\s0 Free Documentation License" +.Sh "\s-1GNU\s0 Free Documentation License" .IX Subsection "GNU Free Documentation License" -.SS "Version 1.3, 3 November 2008" +.Sh "Version 1.3, 3 November 2008" .IX Subsection "Version 1.3, 3 November 2008" .Vb 2 \& Copyright (c) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. @@ -592,7 +600,7 @@ and (2) were thus incorporated prior to November 1, 2008. The operator of an \s-1MMC\s0 Site may republish an \s-1MMC\s0 contained in the site under CC-BY-SA on the same site at any time before August 1, 2009, provided the \s-1MMC\s0 is eligible for relicensing. -.SS "\s-1ADDENDUM:\s0 How to use this License for your documents" +.Sh "\s-1ADDENDUM:\s0 How to use this License for your documents" .IX Subsection "ADDENDUM: How to use this License for your documents" To use this License in a document you have written, include a copy of the License in the document and put the following copyright and diff --git a/gcc-4.8/gcc/doc/gfortran.1 b/gcc-4.8/gcc/doc/gfortran.1 index acaf61f9f..eff1ba070 100644 --- a/gcc-4.8/gcc/doc/gfortran.1 +++ b/gcc-4.8/gcc/doc/gfortran.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GFORTRAN 1" -.TH GFORTRAN 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GFORTRAN 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -224,7 +232,7 @@ by type. Explanations are in the following sections. \&\-fno\-automatic \-fno\-protect\-parens \-fno\-underscoring \-fno\-whole\-file \&\-fsecond\-underscore \-fpack\-derived \-frealloc\-lhs \-frecursive \&\-frepack\-arrays \-fshort\-enums \-fstack\-arrays\fR -.SS "Options controlling Fortran dialect" +.Sh "Options controlling Fortran dialect" .IX Subsection "Options controlling Fortran dialect" The following options control the details of the Fortran dialect accepted by the compiler: @@ -406,7 +414,7 @@ that are permitted but obsolescent in later standards. \fB\-std=f2008ts\fR allows the Fortran 2008 standard including the additions of the Technical Specification (\s-1TS\s0) 29113 on Further Interoperability of Fortran with C. -.SS "Enable and customize preprocessing" +.Sh "Enable and customize preprocessing" .IX Subsection "Enable and customize preprocessing" Preprocessor related options. See section \&\fBPreprocessing and conditional compilation\fR for more detailed @@ -594,7 +602,7 @@ by the linemarkers. .IX Item "-Uname" Cancel any previous definition of \fIname\fR, either built in or provided with a \fB\-D\fR option. -.SS "Options to request or suppress errors and warnings" +.Sh "Options to request or suppress errors and warnings" .IX Subsection "Options to request or suppress errors and warnings" Errors are diagnostic messages that report that the \s-1GNU\s0 Fortran compiler cannot compile the relevant piece of source code. The compiler will @@ -825,7 +833,7 @@ target. This option is implied by \fB\-Wall\fR. Turns all warnings into errors. .PP Some of these have no effect when compiling programs written in Fortran. -.SS "Options for debugging your program or \s-1GNU\s0 Fortran" +.Sh "Options for debugging your program or \s-1GNU\s0 Fortran" .IX Subsection "Options for debugging your program or GNU Fortran" \&\s-1GNU\s0 Fortran has various special options that are used for debugging either your program or the \s-1GNU\s0 Fortran compiler. @@ -834,11 +842,12 @@ either your program or the \s-1GNU\s0 Fortran compiler. Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the \&\s-1GNU\s0 Fortran compiler itself. -.IP "\fB\-fdump\-optimized\-tree\fR" 4 -.IX Item "-fdump-optimized-tree" +.IP "\fB\-fdump\-fortran\-optimized\fR" 4 +.IX Item "-fdump-fortran-optimized" Output the parse tree after front-end optimization. Only really useful for debugging the \s-1GNU\s0 Fortran compiler itself. -.Sp +.IP "\fB\-fdump\-parse\-tree\fR" 4 +.IX Item "-fdump-parse-tree" Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the \&\s-1GNU\s0 Fortran compiler itself. This option is deprecated; use @@ -879,7 +888,7 @@ action \fBcore\fR), the Fortran runtime library tries to output a backtrace of the error. \f(CW\*(C`\-fno\-backtrace\*(C'\fR disables the backtrace generation. This option only has influence for compilation of the Fortran main program. -.SS "Options for directory search" +.Sh "Options for directory search" .IX Subsection "Options for directory search" These options affect how \s-1GNU\s0 Fortran searches for files specified by the \f(CW\*(C`INCLUDE\*(C'\fR directive and where it searches @@ -911,7 +920,7 @@ The default is the current directory. .IX Item "-fintrinsic-modules-path dir" This option specifies the location of pre-compiled intrinsic modules, if they are not in the default location expected by the compiler. -.SS "Influencing the linking step" +.Sh "Influencing the linking step" .IX Subsection "Influencing the linking step" These options come into play when the compiler links object files into an executable output file. They are meaningless if the compiler is not doing @@ -922,7 +931,7 @@ On systems that provide \fIlibgfortran\fR as a shared and a static library, this option forces the use of the static version. If no shared version of \fIlibgfortran\fR was built when the compiler was configured, this option has no effect. -.SS "Influencing runtime behavior" +.Sh "Influencing runtime behavior" .IX Subsection "Influencing runtime behavior" These options affect the runtime behavior of programs compiled with \s-1GNU\s0 Fortran. .IP "\fB\-fconvert=\fR\fIconversion\fR" 4 @@ -957,7 +966,7 @@ negative in the \f(CW\*(C`SIGN\*(C'\fR intrinsic. \fB\-fno\-sign\-zero\fR does print the negative sign of zero values (or values rounded to zero for I/O) and regards zero as positive number in the \f(CW\*(C`SIGN\*(C'\fR intrinsic for compatibility with Fortran 77. The default is \fB\-fsign\-zero\fR. -.SS "Options for code generation conventions" +.Sh "Options for code generation conventions" .IX Subsection "Options for code generation conventions" These machine-independent options control the interface conventions used in code generation. diff --git a/gcc-4.8/gcc/doc/gij.1 b/gcc-4.8/gcc/doc/gij.1 index b9f753ea5..df2a7dc00 100644 --- a/gcc-4.8/gcc/doc/gij.1 +++ b/gcc-4.8/gcc/doc/gij.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GIJ 1" -.TH GIJ 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GIJ 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/gpl.7 b/gcc-4.8/gcc/doc/gpl.7 index 30cfa1c71..324dbb93a 100644 --- a/gcc-4.8/gcc/doc/gpl.7 +++ b/gcc-4.8/gcc/doc/gpl.7 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GPL 7" -.TH GPL 7 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GPL 7 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l @@ -133,9 +141,9 @@ gpl \- GNU General Public License .SH "DESCRIPTION" .IX Header "DESCRIPTION" -.SS "\s-1GNU\s0 General Public License" +.Sh "\s-1GNU\s0 General Public License" .IX Subsection "GNU General Public License" -.SS "Version 3, 29 June 2007" +.Sh "Version 3, 29 June 2007" .IX Subsection "Version 3, 29 June 2007" .Vb 1 \& Copyright (c) 2007 Free Software Foundation, Inc. @@ -143,7 +151,7 @@ gpl \- GNU General Public License \& Everyone is permitted to copy and distribute verbatim copies of this \& license document, but changing it is not allowed. .Ve -.SS "Preamble" +.Sh "Preamble" .IX Subsection "Preamble" The \s-1GNU\s0 General Public License is a free, copyleft license for software and other kinds of works. @@ -207,7 +215,7 @@ assures that patents cannot be used to render the program non-free. .PP The precise terms and conditions for copying, distribution and modification follow. -.SS "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" +.Sh "\s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" .IX Subsection "TERMS AND CONDITIONS" .IP "0. Definitions." 4 .IX Item "0. Definitions." @@ -770,9 +778,9 @@ reviewing courts shall apply local law that most closely approximates an absolute waiver of all civil liability in connection with the Program, unless a warranty or assumption of liability accompanies a copy of the Program in return for a fee. -.SS "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" +.Sh "\s-1END\s0 \s-1OF\s0 \s-1TERMS\s0 \s-1AND\s0 \s-1CONDITIONS\s0" .IX Subsection "END OF TERMS AND CONDITIONS" -.SS "How to Apply These Terms to Your New Programs" +.Sh "How to Apply These Terms to Your New Programs" .IX Subsection "How to Apply These Terms to Your New Programs" If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it diff --git a/gcc-4.8/gcc/doc/grmic.1 b/gcc-4.8/gcc/doc/grmic.1 index 8c29a7604..517d51ad8 100644 --- a/gcc-4.8/gcc/doc/grmic.1 +++ b/gcc-4.8/gcc/doc/grmic.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "GRMIC 1" -.TH GRMIC 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH GRMIC 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/invoke.texi b/gcc-4.8/gcc/doc/invoke.texi index cb0d50ec7..a09553ccf 100644 --- a/gcc-4.8/gcc/doc/invoke.texi +++ b/gcc-4.8/gcc/doc/invoke.texi @@ -161,7 +161,7 @@ in the following sections. -pipe -pass-exit-codes @gol -x @var{language} -v -### --help@r{[}=@var{class}@r{[},@dots{}@r{]]} --target-help @gol --version -wrapper @@@var{file} -fplugin=@var{file} -fplugin-arg-@var{name}=@var{arg} @gol --fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{arg} -fdump-go-spec=@var{file}} +-fdump-ada-spec@r{[}-slim@r{]} -fada-spec-parent=@var{unit} -fdump-go-spec=@var{file}} @item C Language Options @xref{C Dialect Options,,Options Controlling C Dialect}. @@ -857,7 +857,12 @@ See RS/6000 and PowerPC Options. -mno-recip-precision @gol -mveclibabi=@var{type} -mfriz -mno-friz @gol -mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol --msave-toc-indirect -mno-save-toc-indirect} +-msave-toc-indirect -mno-save-toc-indirect @gol +-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol +-mcrypto -mno-crypto -mdirect-move -mno-direct-move @gol +-mquad-memory -mno-quad-memory @gol +-mquad-memory-atomic -mno-quad-memory-atomic @gol +-mcompat-align-parm -mno-compat-align-parm} @emph{RX Options} @gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol @@ -881,7 +886,8 @@ See RS/6000 and PowerPC Options. -msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol -m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol -mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd @gol --mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard} +-mwarn-framesize -mwarn-dynamicstack -mstack-size -mstack-guard @gol +-mhotpatch[=@var{halfwords}] -mno-hotpatch} @emph{Score Options} @gccoptlist{-meb -mel @gol @@ -926,11 +932,12 @@ See RS/6000 and PowerPC Options. -mhard-quad-float -msoft-quad-float @gol -mstack-bias -mno-stack-bias @gol -munaligned-doubles -mno-unaligned-doubles @gol +-muser-mode -mno-user-mode @gol -mv8plus -mno-v8plus -mvis -mno-vis @gol -mvis2 -mno-vis2 -mvis3 -mno-vis3 @gol -mcbcond -mno-cbcond @gol -mfmaf -mno-fmaf -mpopc -mno-popc @gol --mfix-at697f} +-mfix-at697f -mfix-ut699} @emph{SPU Options} @gccoptlist{-mwarn-reloc -merror-reloc @gol @@ -1462,11 +1469,18 @@ Define an argument called @var{key} with a value of @var{value} for the plugin called @var{name}. @item -fdump-ada-spec@r{[}-slim@r{]} -For C and C++ source and include files, generate corresponding Ada -specs. @xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, +@opindex fdump-ada-spec +For C and C++ source and include files, generate corresponding Ada specs. +@xref{Generating Ada Bindings for C and C++ headers,,, gnat_ugn, GNAT User's Guide}, which provides detailed documentation on this feature. +@item -fada-spec-parent=@var{unit} +@opindex fada-spec-parent +In conjunction with @option{-fdump-ada-spec@r{[}-slim@r{]}} above, generate +Ada specs as child units of parent @var{unit}. + @item -fdump-go-spec=@var{file} +@opindex fdump-go-spec For input files in any language, generate corresponding Go declarations in @var{file}. This generates Go @code{const}, @code{type}, @code{var}, and @code{func} declarations which may be a @@ -11317,11 +11331,32 @@ option should only be used if you require compatibility with code for big-endian ARM processors generated by versions of the compiler prior to 2.8. This option is now deprecated. -@item -mcpu=@var{name} -@opindex mcpu -This specifies the name of the target ARM processor. GCC uses this name -to determine what kind of instructions it can emit when generating -assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, +@item -march=@var{name} +@opindex march +This specifies the name of the target ARM architecture. GCC uses this +name to determine what kind of instructions it can emit when generating +assembly code. This option can be used in conjunction with or instead +of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, +@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, +@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te}, +@samp{armv6}, @samp{armv6j}, +@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, +@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, @samp{armv7e-m} +@samp{armv8-a}, +@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. + +@option{-march=native} causes the compiler to auto-detect the architecture +of the build computer. At present, this feature is only supported on +Linux, and not all architectures are recognized. If the auto-detect is +unsuccessful the option has no effect. + +@item -mtune=@var{name} +@opindex mtune +This option specifies the name of the target ARM processor for +which GCC should tune the performance of the code. +For some ARM implementations better performance can be obtained by using +this option. +Permissible names are: @samp{arm2}, @samp{arm250}, @samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610}, @samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm}, @samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700}, @@ -11349,27 +11384,6 @@ assembly code. Permissible names are: @samp{arm2}, @samp{arm250}, @samp{fa526}, @samp{fa626}, @samp{fa606te}, @samp{fa626te}, @samp{fmp626}, @samp{fa726te}. - -@option{-mcpu=generic-@var{arch}} is also permissible, and is -equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. -See @option{-mtune} for more information. - -@option{-mcpu=native} causes the compiler to auto-detect the CPU -of the build computer. At present, this feature is only supported on -Linux, and not all architectures are recognized. If the auto-detect is -unsuccessful the option has no effect. - -@item -mtune=@var{name} -@opindex mtune -This option is very similar to the @option{-mcpu=} option, except that -instead of specifying the actual target processor type, and hence -restricting which instructions can be used, it specifies that GCC should -tune the performance of the code as if the target were of the type -specified in this option, but still choosing the instructions it -generates based on the CPU specified by a @option{-mcpu=} option. -For some ARM implementations better performance can be obtained by using -this option. - @option{-mtune=generic-@var{arch}} specifies that GCC should tune the performance for a blend of processors within architecture @var{arch}. The aim is to generate code that run well on the current most popular @@ -11382,21 +11396,23 @@ of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. -@item -march=@var{name} -@opindex march -This specifies the name of the target ARM architecture. GCC uses this -name to determine what kind of instructions it can emit when generating -assembly code. This option can be used in conjunction with or instead -of the @option{-mcpu=} option. Permissible names are: @samp{armv2}, -@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t}, -@samp{armv5}, @samp{armv5t}, @samp{armv5e}, @samp{armv5te}, -@samp{armv6}, @samp{armv6j}, -@samp{armv6t2}, @samp{armv6z}, @samp{armv6zk}, @samp{armv6-m}, -@samp{armv7}, @samp{armv7-a}, @samp{armv7-r}, @samp{armv7-m}, -@samp{armv8-a}, -@samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. +@item -mcpu=@var{name} +@opindex mcpu +This specifies the name of the target ARM processor. GCC uses this name +to derive the name of the target ARM architecture (as if specified +by @option{-march}) and the ARM processor type for which to tune for +performance (as if specified by @option{-mtune}). Where this option +is used in conjunction with @option{-march} or @option{-mtune}, +those options take precedence over the appropriate part of this option. -@option{-march=native} causes the compiler to auto-detect the architecture +Permissible names for this option are the same as those for +@option{-mtune}. + +@option{-mcpu=generic-@var{arch}} is also permissible, and is +equivalent to @option{-march=@var{arch} -mtune=generic-@var{arch}}. +See @option{-mtune} for more information. + +@option{-mcpu=native} causes the compiler to auto-detect the CPU of the build computer. At present, this feature is only supported on Linux, and not all architectures are recognized. If the auto-detect is unsuccessful the option has no effect. @@ -11485,8 +11501,11 @@ before execution begins. @item -mpic-register=@var{reg} @opindex mpic-register -Specify the register to be used for PIC addressing. The default is R10 -unless stack-checking is enabled, when R9 is used. +Specify the register to be used for PIC addressing. +For standard PIC base case, the default will be any suitable register +determined by compiler. For single PIC base case, the default is +@samp{R9} if target is EABI based or stack-checking is enabled, +otherwise the default is @samp{R10}. @item -mpoke-function-name @opindex mpoke-function-name @@ -17313,7 +17332,9 @@ following options: @gccoptlist{-maltivec -mfprnd -mhard-float -mmfcrf -mmultiple @gol -mpopcntb -mpopcntd -mpowerpc64 @gol -mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol --msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx} +-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol +-mcrypto -mdirect-move -mpower8-fusion -mpower8-vector @gol +-mquad-memory -mquad-memory-atomic} The particular options set for any particular CPU varies between compiler versions, depending on what setting seems to produce optimal @@ -17364,6 +17385,38 @@ the AltiVec instruction set. You may also need to set @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI enhancements. +When @option{-maltivec} is used, rather than @option{-maltivec=le} or +@option{-maltivec=be}, the element order for Altivec intrinsics such +as @code{vec_splat}, @code{vec_extract}, and @code{vec_insert} will +match array element order corresponding to the endianness of the +target. That is, element zero identifies the leftmost element in a +vector register when targeting a big-endian platform, and identifies +the rightmost element in a vector register when targeting a +little-endian platform. + +@item -maltivec=be +@opindex maltivec=be +Generate Altivec instructions using big-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as @code{vec_splat}, @code{vec_extract}, and +@code{vec_insert}. By default, these will match array element order +corresponding to the endianness for the target. + +@item -maltivec=le +@opindex maltivec=le +Generate Altivec instructions using little-endian element order, +regardless of whether the target is big- or little-endian. This is +the default when targeting a little-endian platform. This option is +currently ignored when targeting a big-endian platform. + +The element order is used to interpret element numbers in Altivec +intrinsics such as @code{vec_splat}, @code{vec_extract}, and +@code{vec_insert}. By default, these will match array element order +corresponding to the endianness for the target. + @item -mvrsave @itemx -mno-vrsave @opindex mvrsave @@ -17431,6 +17484,55 @@ Generate code that uses (does not use) vector/scalar (VSX) instructions, and also enable the use of built-in functions that allow more direct access to the VSX instruction set. +@item -mcrypto +@itemx -mno-crypto +@opindex mcrypto +@opindex mno-crypto +Enable the use (disable) of the built-in functions that allow direct +access to the cryptographic instructions that were added in version +2.07 of the PowerPC ISA. + +@item -mdirect-move +@itemx -mno-direct-move +@opindex mdirect-move +@opindex mno-direct-move +Generate code that uses (does not use) the instructions to move data +between the general purpose registers and the vector/scalar (VSX) +registers that were added in version 2.07 of the PowerPC ISA. + +@item -mpower8-fusion +@itemx -mno-power8-fusion +@opindex mpower8-fusion +@opindex mno-power8-fusion +Generate code that keeps (does not keeps) some integer operations +adjacent so that the instructions can be fused together on power8 and +later processors. + +@item -mpower8-vector +@itemx -mno-power8-vector +@opindex mpower8-vector +@opindex mno-power8-vector +Generate code that uses (does not use) the vector and scalar +instructions that were added in version 2.07 of the PowerPC ISA. Also +enable the use of built-in functions that allow more direct access to +the vector instructions. + +@item -mquad-memory +@itemx -mno-quad-memory +@opindex mquad-memory +@opindex mno-quad-memory +Generate code that uses (does not use) the non-atomic quad word memory +instructions. The @option{-mquad-memory} option requires use of +64-bit mode. + +@item -mquad-memory-atomic +@itemx -mno-quad-memory-atomic +@opindex mquad-memory-atomic +@opindex mno-quad-memory-atomic +Generate code that uses (does not use) the atomic quad word memory +instructions. The @option{-mquad-memory-atomic} option requires use of +64-bit mode. + @item -mfloat-gprs=@var{yes/single/double/no} @itemx -mfloat-gprs @opindex mfloat-gprs @@ -17850,7 +17952,8 @@ SVR4 ABI)@. @opindex mabi Extend the current ABI with a particular extension, or remove such extension. Valid values are @var{altivec}, @var{no-altivec}, @var{spe}, -@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}@. +@var{no-spe}, @var{ibmlongdouble}, @var{ieeelongdouble}, +@var{elfv1}, @var{elfv2}@. @item -mabi=spe @opindex mabi=spe @@ -17872,6 +17975,20 @@ This is a PowerPC 32-bit SYSV ABI option. Change the current ABI to use IEEE extended-precision long double. This is a PowerPC 32-bit Linux ABI option. +@item -mabi=elfv1 +@opindex mabi=elfv1 +Change the current ABI to use the ELFv1 ABI. +This is the default ABI for big-endian PowerPC 64-bit Linux. +Overriding the default ABI requires special system support and is +likely to fail in spectacular ways. + +@item -mabi=elfv2 +@opindex mabi=elfv2 +Change the current ABI to use the ELFv2 ABI. +This is the default ABI for little-endian PowerPC 64-bit Linux. +Overriding the default ABI requires special system support and is +likely to fail in spectacular ways. + @item -mprototype @itemx -mno-prototype @opindex mprototype @@ -18157,6 +18274,23 @@ stack location in the function prologue if the function calls through a pointer on AIX and 64-bit Linux systems. If the TOC value is not saved in the prologue, it is saved just before the call through the pointer. The @option{-mno-save-toc-indirect} option is the default. + +@item -mcompat-align-parm +@itemx -mno-compat-align-parm +@opindex mcompat-align-parm +Generate (do not generate) code to pass structure parameters with a +maximum alignment of 64 bits, for compatibility with older versions +of GCC. + +Older versions of GCC (prior to 4.9.0) incorrectly did not align a +structure parameter on a 128-bit boundary when that structure contained +a member requiring 128-bit alignment. This is corrected in more +recent versions of GCC. This option may be used to generate code +that is compatible with functions compiled with older versions of +GCC. + +In this version of the compiler, the @option{-mcompat-align-parm} +is the default, except when using the Linux ELFv2 ABI. @end table @node RX Options @@ -18536,6 +18670,21 @@ values have to be exact powers of 2 and @var{stack-size} has to be greater than In order to be efficient the extra code makes the assumption that the stack starts at an address aligned to the value given by @var{stack-size}. The @var{stack-guard} option can only be used in conjunction with @var{stack-size}. + +@item -mhotpatch[=@var{halfwords}] +@itemx -mno-hotpatch +@opindex mhotpatch +If the hotpatch option is enabled, a ``hot-patching'' function +prologue is generated for all functions in the compilation unit. +The funtion label is prepended with the given number of two-byte +Nop instructions (@var{halfwords}, maximum 1000000) or 12 Nop +instructions if no argument is present. Functions with a +hot-patching prologue are never inlined automatically, and a +hot-patching prologue is never generated for functions functions +that are explicitly inline. + +This option can be overridden for individual functions with the +@code{hotpatch} attribute. @end table @node Score Options @@ -19126,8 +19275,9 @@ These @samp{-m} options are supported on the SPARC: @opindex mno-app-regs @opindex mapp-regs Specify @option{-mapp-regs} to generate output using the global registers -2 through 4, which the SPARC SVR4 ABI reserves for applications. This -is the default. +2 through 4, which the SPARC SVR4 ABI reserves for applications. Like the +global register 1, each global register 2 through 4 is then treated as an +allocable register that is clobbered by function calls. This is the default. To be fully SVR4 ABI-compliant at the cost of some performance loss, specify @option{-mno-app-regs}. You should compile libraries and system @@ -19202,6 +19352,14 @@ Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code. +@item -muser-mode +@itemx -mno-user-mode +@opindex muser-mode +@opindex mno-user-mode +Do not generate code that can only run in supervisor mode. This is relevant +only for the @code{casa} instruction emitted for the LEON3 processor. The +default is @option{-mno-user-mode}. + @item -mno-faster-structs @itemx -mfaster-structs @opindex mno-faster-structs @@ -19220,10 +19378,10 @@ the rules of the ABI@. Set the instruction set, register set, and instruction scheduling parameters for machine type @var{cpu_type}. Supported values for @var{cpu_type} are @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{hypersparc}, -@samp{leon}, @samp{sparclite}, @samp{f930}, @samp{f934}, @samp{sparclite86x}, -@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, -@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3}, -and @samp{niagara4}. +@samp{leon}, @samp{leon3}, @samp{sparclite}, @samp{f930}, @samp{f934}, +@samp{sparclite86x}, @samp{sparclet}, @samp{tsc701}, @samp{v9}, +@samp{ultrasparc}, @samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, +@samp{niagara3} and @samp{niagara4}. Native Solaris and GNU/Linux toolchains also support the value @samp{native}, which selects the best architecture option for the host processor. @@ -19242,7 +19400,7 @@ implementations. cypress @item v8 -supersparc, hypersparc, leon +supersparc, hypersparc, leon, leon3 @item sparclite f930, f934, sparclite86x @@ -19304,10 +19462,11 @@ option @option{-mcpu=@var{cpu_type}} does. The same values for @option{-mcpu=@var{cpu_type}} can be used for @option{-mtune=@var{cpu_type}}, but the only useful values are those that select a particular CPU implementation. Those are @samp{cypress}, -@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{f930}, @samp{f934}, -@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, @samp{ultrasparc3}, -@samp{niagara}, @samp{niagara2}, @samp{niagara3} and @samp{niagara4}. With -native Solaris and GNU/Linux toolchains, @samp{native} can also be used. +@samp{supersparc}, @samp{hypersparc}, @samp{leon}, @samp{leon3}, @samp{f930}, +@samp{f934}, @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, +@samp{ultrasparc3}, @samp{niagara}, @samp{niagara2}, @samp{niagara3} and +@samp{niagara4}. With native Solaris and GNU/Linux toolchains, @samp{native} +can also be used. @item -mv8plus @itemx -mno-v8plus @@ -19376,6 +19535,11 @@ later. @opindex mfix-at697f Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor). + +@item -mfix-ut699 +@opindex mfix-ut699 +Enable the documented workarounds for the floating-point errata and the data +cache nullify errata of the UT699 processor. @end table These @samp{-m} options are supported in addition to the above diff --git a/gcc-4.8/gcc/doc/jcf-dump.1 b/gcc-4.8/gcc/doc/jcf-dump.1 index 72a9e4def..2cc5c6172 100644 --- a/gcc-4.8/gcc/doc/jcf-dump.1 +++ b/gcc-4.8/gcc/doc/jcf-dump.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "JCF-DUMP 1" -.TH JCF-DUMP 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH JCF-DUMP 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/jv-convert.1 b/gcc-4.8/gcc/doc/jv-convert.1 index 65f6136f3..66e5cb3d5 100644 --- a/gcc-4.8/gcc/doc/jv-convert.1 +++ b/gcc-4.8/gcc/doc/jv-convert.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "JV-CONVERT 1" -.TH JV-CONVERT 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH JV-CONVERT 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/md.texi b/gcc-4.8/gcc/doc/md.texi index 63ec92f6b..dacb83a70 100644 --- a/gcc-4.8/gcc/doc/md.texi +++ b/gcc-4.8/gcc/doc/md.texi @@ -2055,7 +2055,7 @@ Any constant whose absolute value is no greater than 4-bits. @end table -@item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h} +@item PowerPC and IBM RS6000---@file{config/rs6000/constraints.md} @table @code @item b Address base register @@ -2069,17 +2069,57 @@ Floating point register (containing 32-bit value) @item v Altivec vector register +@item wa +Any VSX register if the -mvsx option was used or NO_REGS. + @item wd -VSX vector register to hold vector double data +VSX vector register to hold vector double data or NO_REGS. @item wf -VSX vector register to hold vector float data +VSX vector register to hold vector float data or NO_REGS. + +@item wg +If @option{-mmfpgpr} was used, a floating point register or NO_REGS. + +@item wl +Floating point register if the LFIWAX instruction is enabled or NO_REGS. + +@item wm +VSX register if direct move instructions are enabled, or NO_REGS. + +@item wn +No register (NO_REGS). + +@item wr +General purpose register if 64-bit instructions are enabled or NO_REGS. @item ws -VSX vector register to hold scalar float data +VSX vector register to hold scalar double values or NO_REGS. -@item wa -Any VSX register +@item wt +VSX vector register to hold 128 bit integer or NO_REGS. + +@item wu +Altivec register to use for float/32-bit int loads/stores or NO_REGS. + +@item wv +Altivec register to use for double loads/stores or NO_REGS. + +@item ww +FP or VSX register to perform float operations under @option{-mvsx} or NO_REGS. + +@item wx +Floating point register if the STFIWX instruction is enabled or NO_REGS. + +@item wy +VSX vector register to hold scalar float values or NO_REGS. + +@item wz +Floating point register if the LFIWZX instruction is enabled or NO_REGS. + +@item wQ +A memory address that will work with the @code{lq} and @code{stq} +instructions. @item h @samp{MQ}, @samp{CTR}, or @samp{LINK} register diff --git a/gcc-4.8/gcc/doc/rebuild-gcj-db.1 b/gcc-4.8/gcc/doc/rebuild-gcj-db.1 index c0fce32e8..899aa6b52 100644 --- a/gcc-4.8/gcc/doc/rebuild-gcj-db.1 +++ b/gcc-4.8/gcc/doc/rebuild-gcj-db.1 @@ -1,7 +1,15 @@ -.\" Automatically generated by Pod::Man 2.25 (Pod::Simple 3.16) +.\" Automatically generated by Pod::Man 2.16 (Pod::Simple 3.05) .\" .\" Standard preamble: .\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. .de Sp \" Vertical space (when we can't use .PP) .if t .sp .5v .if n .sp @@ -45,14 +53,14 @@ .el .ds Aq ' .\" .\" If the F register is turned on, we'll generate index entries on stderr for -.\" titles (.TH), headers (.SH), subsections (.SS), items (.Ip), and index +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index .\" entries marked with X<> in POD. Of course, you'll have to process the .\" output yourself in some meaningful fashion. .ie \nF \{\ -. de IX -. tm Index:\\$1\t\\n%\t"\\$2" +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" .. -. nr % 0 +. nr % 0 . rr F .\} .el \{\ @@ -124,7 +132,7 @@ .\" ======================================================================== .\" .IX Title "REBUILD-GCJ-DB 1" -.TH REBUILD-GCJ-DB 1 "2013-05-31" "gcc-4.8.1" "GNU" +.TH REBUILD-GCJ-DB 1 "2014-05-22" "gcc-4.8.3" "GNU" .\" For nroff, turn off justification. Always turn off hyphenation; it makes .\" way too many mistakes in technical documents. .if n .ad l diff --git a/gcc-4.8/gcc/doc/sourcebuild.texi b/gcc-4.8/gcc/doc/sourcebuild.texi index 90bd0bdf2..9330aae52 100644 --- a/gcc-4.8/gcc/doc/sourcebuild.texi +++ b/gcc-4.8/gcc/doc/sourcebuild.texi @@ -1596,6 +1596,13 @@ MIPS target supports @code{-mpaired-single}. @subsubsection PowerPC-specific attributes @table @code + +@item dfp_hw +PowerPC target supports executing hardware DFP instructions. + +@item p8vector_hw +PowerPC target supports executing VSX instructions (ISA 2.07). + @item powerpc64 Test system supports executing 64-bit instructions. @@ -1605,12 +1612,24 @@ PowerPC target supports AltiVec. @item powerpc_altivec_ok PowerPC target supports @code{-maltivec}. +@item powerpc_eabi_ok +PowerPC target supports @code{-meabi}. + +@item powerpc_elfv2 +PowerPC target supports @code{-mabi=elfv2}. + @item powerpc_fprs PowerPC target supports floating-point registers. @item powerpc_hard_double PowerPC target supports hardware double-precision floating-point. +@item powerpc_htm_ok +PowerPC target supports @code{-mhtm} + +@item powerpc_p8vector_ok +PowerPC target supports @code{-mpower8-vector} + @item powerpc_ppu_ok PowerPC target supports @code{-mcpu=cell}. @@ -1624,9 +1643,6 @@ PowerPC target supports PowerPC SPE. @item powerpc_spu PowerPC target supports PowerPC SPU. -@item spu_auto_overlay -SPU target has toolchain that supports automatic overlay generation. - @item powerpc_vsx_ok PowerPC target supports @code{-mvsx}. @@ -1634,8 +1650,17 @@ PowerPC target supports @code{-mvsx}. Including the options used to compile this particular test, the PowerPC target supports PowerPC 405. +@item ppc_recip_hw +PowerPC target supports executing reciprocal estimate instructions. + +@item spu_auto_overlay +SPU target has toolchain that supports automatic overlay generation. + @item vmx_hw PowerPC target supports executing AltiVec instructions. + +@item vsx_hw +PowerPC target supports executing VSX instructions (ISA 2.06). @end table @subsubsection Other hardware attributes diff --git a/gcc-4.8/gcc/dse.c b/gcc-4.8/gcc/dse.c index 080822292..e853b4118 100644 --- a/gcc-4.8/gcc/dse.c +++ b/gcc-4.8/gcc/dse.c @@ -2518,7 +2518,8 @@ scan_insn (bb_info_t bb_info, rtx insn) /* Cselib clears the table for this case, so we have to essentially do the same. */ if (NONJUMP_INSN_P (insn) - && volatile_insn_p (PATTERN (insn))) + && GET_CODE (PATTERN (insn)) == ASM_OPERANDS + && MEM_VOLATILE_P (PATTERN (insn))) { add_wild_read (bb_info); insn_info->cannot_delete = true; diff --git a/gcc-4.8/gcc/expr.c b/gcc-4.8/gcc/expr.c index 7e909bc0f..92ea1387e 100644 --- a/gcc-4.8/gcc/expr.c +++ b/gcc-4.8/gcc/expr.c @@ -1994,12 +1994,14 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, int ssize) HOST_WIDE_INT bytepos = INTVAL (XEXP (XVECEXP (src, 0, i), 1)); enum machine_mode mode = GET_MODE (tmps[i]); unsigned int bytelen = GET_MODE_SIZE (mode); - unsigned int adj_bytelen = bytelen; + unsigned int adj_bytelen; rtx dest = dst; /* Handle trailing fragments that run over the size of the struct. */ if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize) adj_bytelen = ssize - bytepos; + else + adj_bytelen = bytelen; if (GET_CODE (dst) == CONCAT) { @@ -2040,6 +2042,7 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, int ssize) } } + /* Handle trailing fragments that run over the size of the struct. */ if (ssize >= 0 && bytepos + (HOST_WIDE_INT) bytelen > ssize) { /* store_bit_field always takes its value from the lsb. @@ -2057,16 +2060,22 @@ emit_group_store (rtx orig_dst, rtx src, tree type ATTRIBUTE_UNUSED, int ssize) tmps[i] = expand_shift (RSHIFT_EXPR, mode, tmps[i], shift, tmps[i], 0); } - bytelen = adj_bytelen; + + /* Make sure not to write past the end of the struct. */ + store_bit_field (dest, + adj_bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT, + bytepos * BITS_PER_UNIT, ssize * BITS_PER_UNIT - 1, + VOIDmode, tmps[i]); } /* Optimize the access just a bit. */ - if (MEM_P (dest) - && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest)) + else if (MEM_P (dest) + && (!SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (dest)) || MEM_ALIGN (dest) >= GET_MODE_ALIGNMENT (mode)) && bytepos * BITS_PER_UNIT % GET_MODE_ALIGNMENT (mode) == 0 && bytelen == GET_MODE_SIZE (mode)) emit_move_insn (adjust_address (dest, mode, bytepos), tmps[i]); + else store_bit_field (dest, bytelen * BITS_PER_UNIT, bytepos * BITS_PER_UNIT, 0, 0, mode, tmps[i]); @@ -3602,12 +3611,21 @@ compress_float_constant (rtx x, rtx y) into a new pseudo. This constant may be used in different modes, and if not, combine will put things back together for us. */ trunc_y = force_reg (srcmode, trunc_y); - emit_unop_insn (ic, x, trunc_y, UNKNOWN); + + /* If x is a hard register, perform the extension into a pseudo, + so that e.g. stack realignment code is aware of it. */ + rtx target = x; + if (REG_P (x) && HARD_REGISTER_P (x)) + target = gen_reg_rtx (dstmode); + + emit_unop_insn (ic, target, trunc_y, UNKNOWN); last_insn = get_last_insn (); - if (REG_P (x)) + if (REG_P (target)) set_unique_reg_note (last_insn, REG_EQUAL, y); + if (target != x) + return emit_move_insn (x, target); return last_insn; } @@ -4551,17 +4569,17 @@ get_bit_range (unsigned HOST_WIDE_INT *bitstart, - tree_low_cst (DECL_FIELD_BIT_OFFSET (repr), 1)); /* If the adjustment is larger than bitpos, we would have a negative bit - position for the lower bound and this may wreak havoc later. This can - occur only if we have a non-null offset, so adjust offset and bitpos - to make the lower bound non-negative. */ + position for the lower bound and this may wreak havoc later. Adjust + offset and bitpos to make the lower bound non-negative in that case. */ if (bitoffset > *bitpos) { HOST_WIDE_INT adjust = bitoffset - *bitpos; - gcc_assert ((adjust % BITS_PER_UNIT) == 0); - gcc_assert (*offset != NULL_TREE); *bitpos += adjust; + if (*offset == NULL_TREE) + *offset = size_int (-adjust / BITS_PER_UNIT); + else *offset = size_binop (MINUS_EXPR, *offset, size_int (adjust / BITS_PER_UNIT)); *bitstart = 0; @@ -4668,8 +4686,7 @@ expand_assignment (tree to, tree from, bool nontemporal) expand_insn (icode, 2, ops); } else - store_bit_field (mem, GET_MODE_BITSIZE (mode), - 0, 0, 0, mode, reg); + store_bit_field (mem, GET_MODE_BITSIZE (mode), 0, 0, 0, mode, reg); return; } @@ -4698,6 +4715,15 @@ expand_assignment (tree to, tree from, bool nontemporal) tem = get_inner_reference (to, &bitsize, &bitpos, &offset, &mode1, &unsignedp, &volatilep, true); + /* Make sure bitpos is not negative, it can wreak havoc later. */ + if (bitpos < 0) + { + gcc_assert (offset == NULL_TREE); + offset = size_int (bitpos >> (BITS_PER_UNIT == 8 + ? 3 : exact_log2 (BITS_PER_UNIT))); + bitpos &= BITS_PER_UNIT - 1; + } + if (TREE_CODE (to) == COMPONENT_REF && DECL_BIT_FIELD_TYPE (TREE_OPERAND (to, 1))) get_bit_range (&bitregion_start, &bitregion_end, to, &bitpos, &offset); diff --git a/gcc-4.8/gcc/expr.h b/gcc-4.8/gcc/expr.h index 15fcb471d..98c9daeda 100644 --- a/gcc-4.8/gcc/expr.h +++ b/gcc-4.8/gcc/expr.h @@ -521,8 +521,8 @@ extern rtx expand_divmod (int, enum tree_code, enum machine_mode, rtx, rtx, rtx, int); #endif -extern void locate_and_pad_parm (enum machine_mode, tree, int, int, tree, - struct args_size *, +extern void locate_and_pad_parm (enum machine_mode, tree, int, int, int, + tree, struct args_size *, struct locate_and_pad_arg_data *); /* Return the CODE_LABEL rtx for a LABEL_DECL, creating it if necessary. */ diff --git a/gcc-4.8/gcc/fold-const.c b/gcc-4.8/gcc/fold-const.c index 6dc8934f3..3a60201e2 100644 --- a/gcc-4.8/gcc/fold-const.c +++ b/gcc-4.8/gcc/fold-const.c @@ -461,8 +461,6 @@ negate_expr_p (tree t) case TRUNC_DIV_EXPR: case ROUND_DIV_EXPR: - case FLOOR_DIV_EXPR: - case CEIL_DIV_EXPR: case EXACT_DIV_EXPR: /* In general we can't negate A / B, because if A is INT_MIN and B is 1, we may turn this into INT_MIN / -1 which is undefined @@ -644,8 +642,6 @@ fold_negate_expr (location_t loc, tree t) case TRUNC_DIV_EXPR: case ROUND_DIV_EXPR: - case FLOOR_DIV_EXPR: - case CEIL_DIV_EXPR: case EXACT_DIV_EXPR: /* In general we can't negate A / B, because if A is INT_MIN and B is 1, we may turn this into INT_MIN / -1 which is undefined @@ -2664,10 +2660,11 @@ operand_equal_p (const_tree arg0, const_tree arg1, unsigned int flags) case COMPONENT_REF: /* Handle operand 2 the same as for ARRAY_REF. Operand 0 may be NULL when we're called to compare MEM_EXPRs. */ - if (!OP_SAME_WITH_NULL (0)) + if (!OP_SAME_WITH_NULL (0) + || !OP_SAME (1)) return 0; flags &= ~OEP_CONSTANT_ADDRESS_OF; - return OP_SAME (1) && OP_SAME_WITH_NULL (2); + return OP_SAME_WITH_NULL (2); case BIT_FIELD_REF: if (!OP_SAME (0)) @@ -4920,12 +4917,16 @@ fold_range_test (location_t loc, enum tree_code code, tree type, int in0_p, in1_p, in_p; tree low0, low1, low, high0, high1, high; bool strict_overflow_p = false; - tree lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p); - tree rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p); - tree tem; + tree tem, lhs, rhs; const char * const warnmsg = G_("assuming signed overflow does not occur " "when simplifying range test"); + if (!INTEGRAL_TYPE_P (type)) + return 0; + + lhs = make_range (op0, &in0_p, &low0, &high0, &strict_overflow_p); + rhs = make_range (op1, &in1_p, &low1, &high1, &strict_overflow_p); + /* If this is an OR operation, invert both sides; we will invert again at the end. */ if (or_op) @@ -10927,6 +10928,13 @@ fold_binary_loc (location_t loc, fold_build2_loc (loc, MULT_EXPR, type, build_int_cst (type, 2) , arg1)); + /* ((T) (X /[ex] C)) * C cancels out if the conversion is + sign-changing only. */ + if (TREE_CODE (arg1) == INTEGER_CST + && TREE_CODE (arg0) == EXACT_DIV_EXPR + && operand_equal_p (arg1, TREE_OPERAND (arg0, 1), 0)) + return fold_convert_loc (loc, type, TREE_OPERAND (arg0, 0)); + strict_overflow_p = false; if (TREE_CODE (arg1) == INTEGER_CST && 0 != (tem = extract_muldiv (op0, arg1, code, NULL_TREE, @@ -16587,7 +16595,7 @@ fold_indirect_ref_1 (location_t loc, tree type, tree op0) unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT; tree index = bitsize_int (indexi); - if (offset/part_widthi <= TYPE_VECTOR_SUBPARTS (op00type)) + if (offset / part_widthi < TYPE_VECTOR_SUBPARTS (op00type)) return fold_build3_loc (loc, BIT_FIELD_REF, type, op00, part_width, index); diff --git a/gcc-4.8/gcc/fortran/ChangeLog b/gcc-4.8/gcc/fortran/ChangeLog index c8733a6d7..44c59c77b 100644 --- a/gcc-4.8/gcc/fortran/ChangeLog +++ b/gcc-4.8/gcc/fortran/ChangeLog @@ -1,3 +1,263 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-04-11 Janne Blomqvist + + * intrinsic.texi (RANDOM_SEED): Improve example. + +2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-22 Jakub Jelinek + + PR debug/60603 + * cpp.c (gfc_cpp_init): Restore cb_change_file call to + . + +2014-03-29 Mikael Morin + + PR fortran/60677 + * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Enlarge argument + list buffer. + +2014-03-28 Mikael Morin + Tobias Burnus + + PR fortran/60576 + * trans-expr.c (gfc_conv_derived_to_class): Avoid + generation of out-of-bounds range expr. + +2014-03-28 Thomas Koenig + + PR fortran/60522 + * frontend-passes.c (cfe_code): Do not walk subtrees + for WHERE. + +2014-03-20 Tobias Burnus + + PR fortran/60543 + PR fortran/60283 + * gfortran.h (gfc_unset_implicit_pure): New prototype. + * resolve.c (gfc_unset_implicit_pure): New. + (resolve_structure_cons, resolve_function, + pure_subroutine, resolve_ordinary_assign): Use it. + * decl.c (match_old_style_init, gfc_match_data, + match_pointer_init, variable_decl): Ditto. + * expr.c (gfc_check_pointer_assign): Ditto. + * intrinsic.c (gfc_intrinsic_sub_interface): Ditto. + * io.c (match_vtag, gfc_match_open, gfc_match_close, + match_filepos, gfc_match_inquire, gfc_match_print, + gfc_match_wait, check_io_constraints): Ditto. + * match.c (gfc_match_critical, gfc_match_stopcode, + lock_unlock_statement, sync_statement, gfc_match_allocate, + gfc_match_deallocate): Ditto. + * parse.c (decode_omp_directive): Ditto. + * symbol.c (gfc_add_save): Ditto. + +2014-03-08 Janus Weil + + PR fortran/60450 + * simplify.c (gfc_simplify_shape): Only clear shape if it was really + created successfully. + +2014-03-06 Jakub Jelinek + + Backport from mainline + 2014-02-11 Jakub Jelinek + + PR fortran/52370 + * trans-decl.c (gfc_build_dummy_array_decl): Set TREE_NO_WARNING + on decl if sym->attr.optional. + +2014-03-02 Mikael Morin + + PR fortran/60341 + * frontend-passes.c (optimize_comparison): Guard two union accesses + with the corresponding tag checks. + +2014-02-22 Mikael Morin + + PR fortran/59599 + * trans-intrinsic.c (gfc_conv_intrinsic_ichar): Calculate the + number of arguments. + +2014-02-19 Tobias Burnus + + PR fortran/49397 + * expr.c (gfc_check_pointer_assign): Add check for + F2008Cor2, C729. + * trans-decl.c (gfc_get_symbol_decl): Correctly generate + external decl in a corner case. + +2014-02-19 Janus Weil + + Backports from mainline: + 2014-02-17 Janus Weil + + PR fortran/55907 + * resolve.c (build_default_init_expr): Don't initialize character + variable if -fno-automatic is given. + + 2014-02-18 Janus Weil + + PR fortran/60231 + * resolve.c (check_generic_tbp_ambiguity): Check for presence of dummy + arguments to prevent ICE. + +2014-02-09 Janus Weil + + Backport from mainline + 2013-10-21 Tobias Burnus + + PR fortran/58803 + PR fortran/59395 + * decl.c (match_ppc_decl): Prevent later double free. + +2014-02-08 Mikael Morin + + PR fortran/57033 + * primary.c (gfc_convert_to_structure_constructor): Avoid null pointer + dereference. + +2014-02-07 Paul Thomas + + PR fortran/59906 + * trans-stmt.c (gfc_add_loop_ss_code): In the case of character + SS_REFERENCE, use gfc_conv_string_parameter to ensure that a + pointer to the string is stored. + * trans-expr.c (gfc_conv_expr_reference): Likewise, use + gfc_conv_string_parameter to ensure that a pointer to is passed + to the elemental function. + +2014-02-01 Paul Thomas + + PR fortran/59414 + * trans-stmt.c (gfc_trans_allocate): Before the pointer + assignment to transfer the source _vptr to a class allocate + expression, the final class reference should be exposed. The + tail that includes the _data and array references is stored. + This reduced expression is transferred to 'lhs' and the _vptr + added. Then the tail is restored to the allocate expression. + +2014-01-26 Mikael Morin + + PR fortran/58007 + * module.c + (fp2, find_pointer2): Remove. + (mio_component_ref): Don't forcedfully set the containing derived type + symbol for loading. Remove unused argument. + (mio_ref): Update caller + (skip_list): New argument nest_level. Initialize level with the new + argument. + (read_module): Add forced pointer components association for derived + type symbols. + +2014-01-19 Paul Thomas + + Backport from mainline + 2013-12-01 Paul Thomas + + PR fortran/58410 + * trans-array.c (gfc_alloc_allocatable_for_assignment): Do not + use the array bounds of an unallocated array but set its size + to zero instead. + +2014-01-19 Paul Thomas + + Backport from mainline + 2013-12-01 Paul Thomas + + PR fortran/34547 + * resolve.c (resolve_transfer): EXPR_NULL is always in an + invalid context in a transfer statement. + +2014-01-11 Janus Weil + + Backport from mainline + 2013-12-29 Janus Weil + + PR fortran/59612 + PR fortran/57042 + * dump-parse-tree.c (show_typespec): Check for charlen. + * invoke.texi: Fix documentation of -fdump-fortran-optimized and + -fdump-parse-tree. + +2014-01-04 Janus Weil + + Backport from mainline + 2014-01-02 Janus Weil + + PR fortran/59654 + * resolve.c (resolve_typebound_procedures): No need to create the vtab + here. + +2013-12-31 Janus Weil + + Backport from mainline + 2013-12-30 Janus Weil + + PR fortran/58998 + * resolve.c (resolve_symbol): Check that symbol is not only flavorless + but also untyped. + +2013-12-18 Janus Weil + + Backport from mainline + 2013-12-15 Janus Weil + + PR fortran/59493 + * class.c (gfc_find_intrinsic_vtab): Handle BT_CLASS. + +2013-11-30 Paul Thomas + + Backport from mainline + 2013-11-04 Paul Thomas + + PR fortran/57445 + * trans-expr.c (gfc_conv_class_to_class): Remove spurious + assert. + +2013-11-17 Janus Weil + + Backport from mainline + 2013-11-07 Janus Weil + + PR fortran/58471 + * primary.c (gfc_expr_attr): Check for result symbol. + +2013-11-16 Janus Weil + + Backport from mainline + 2013-09-20 Janus Weil + + PR fortran/58099 + * expr.c (gfc_check_pointer_assign): Remove second call to + 'gfc_compare_interfaces' with swapped arguments. + * interface.c (gfc_compare_interfaces): Symmetrize the call to + 'check_result_characteristics' by calling it with swapped arguments. + +2013-11-16 Paul Thomas + + PR fortran/58771 + * trans-io.c (transfer_expr): If the backend_decl for a derived + type is missing, build it with gfc_typenode_for_spec. + +2013-11-05 Steven G. Kargl + + PR fortran/58989 + * check.c (gfc_check_reshape): ensure that shape is a constant + expression. + +2013-11-02 Janus Weil + + Backport from mainline + 2013-09-23 Janus Weil + + PR fortran/58355 + * decl.c (check_extended_derived_type): Prevent segfault, modify error + message. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/fortran/check.c b/gcc-4.8/gcc/fortran/check.c index 586adee8b..c9520f628 100644 --- a/gcc-4.8/gcc/fortran/check.c +++ b/gcc-4.8/gcc/fortran/check.c @@ -3208,7 +3208,7 @@ gfc_check_reshape (gfc_expr *source, gfc_expr *shape, "than %d elements", &shape->where, GFC_MAX_DIMENSIONS); return FAILURE; } - else if (shape->expr_type == EXPR_ARRAY) + else if (shape->expr_type == EXPR_ARRAY && gfc_is_constant_expr (shape)) { gfc_expr *e; int i, extent; diff --git a/gcc-4.8/gcc/fortran/class.c b/gcc-4.8/gcc/fortran/class.c index d8e7b6ded..55c072b82 100644 --- a/gcc-4.8/gcc/fortran/class.c +++ b/gcc-4.8/gcc/fortran/class.c @@ -2486,7 +2486,7 @@ gfc_find_intrinsic_vtab (gfc_typespec *ts) return NULL; /* Sometimes the typespec is passed from a single call. */ - if (ts->type == BT_DERIVED) + if (ts->type == BT_DERIVED || ts->type == BT_CLASS) return gfc_find_derived_vtab (ts->u.derived); /* Find the top-level namespace. */ diff --git a/gcc-4.8/gcc/fortran/cpp.c b/gcc-4.8/gcc/fortran/cpp.c index 0a176b2ad..36e96ea5c 100644 --- a/gcc-4.8/gcc/fortran/cpp.c +++ b/gcc-4.8/gcc/fortran/cpp.c @@ -569,6 +569,7 @@ gfc_cpp_init (void) if (gfc_option.flag_preprocessed) return; + cpp_change_file (cpp_in, LC_RENAME, _("")); if (!gfc_cpp_option.no_predefined) { /* Make sure all of the builtins about to be declared have diff --git a/gcc-4.8/gcc/fortran/decl.c b/gcc-4.8/gcc/fortran/decl.c index 72c511c8b..90aee19db 100644 --- a/gcc-4.8/gcc/fortran/decl.c +++ b/gcc-4.8/gcc/fortran/decl.c @@ -510,9 +510,7 @@ match_old_style_init (const char *name) free (newdata); return MATCH_ERROR; } - - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (gfc_current_ns->proc_name); /* Mark the variable as having appeared in a data statement. */ if (gfc_add_data (&sym->attr, sym->name, &sym->declared_at) == FAILURE) @@ -571,9 +569,7 @@ gfc_match_data (void) gfc_error ("DATA statement at %C is not allowed in a PURE procedure"); return MATCH_ERROR; } - - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (gfc_current_ns->proc_name); return MATCH_YES; @@ -1737,6 +1733,7 @@ match_pointer_init (gfc_expr **init, int procptr) "a PURE procedure"); return MATCH_ERROR; } + gfc_unset_implicit_pure (gfc_current_ns->proc_name); /* Match NULL() initialization. */ m = gfc_match_null (init); @@ -2045,6 +2042,10 @@ variable_decl (int elem) m = MATCH_ERROR; } + if (current_attr.flavor != FL_PARAMETER + && gfc_state_stack->state != COMP_DERIVED) + gfc_unset_implicit_pure (gfc_current_ns->proc_name); + if (m != MATCH_YES) goto cleanup; } @@ -5069,7 +5070,14 @@ match_ppc_decl (void) if (gfc_add_proc (&c->attr, name, NULL) == FAILURE) return MATCH_ERROR; + if (num == 1) c->tb = tb; + else + { + c->tb = XCNEW (gfc_typebound_proc); + c->tb->where = gfc_current_locus; + *c->tb = *tb; + } /* Set interface. */ if (proc_if != NULL) @@ -7384,6 +7392,7 @@ syntax: /* Check a derived type that is being extended. */ + static gfc_symbol* check_extended_derived_type (char *name) { @@ -7395,14 +7404,15 @@ check_extended_derived_type (char *name) return NULL; } + extended = gfc_find_dt_in_generic (extended); + + /* F08:C428. */ if (!extended) { - gfc_error ("No such symbol in TYPE definition at %C"); + gfc_error ("Symbol '%s' at %C has not been previously defined", name); return NULL; } - extended = gfc_find_dt_in_generic (extended); - if (extended->attr.flavor != FL_DERIVED) { gfc_error ("'%s' in EXTENDS expression at %C is not a " diff --git a/gcc-4.8/gcc/fortran/dump-parse-tree.c b/gcc-4.8/gcc/fortran/dump-parse-tree.c index 14ff00412..77404c8d6 100644 --- a/gcc-4.8/gcc/fortran/dump-parse-tree.c +++ b/gcc-4.8/gcc/fortran/dump-parse-tree.c @@ -110,6 +110,7 @@ show_typespec (gfc_typespec *ts) break; case BT_CHARACTER: + if (ts->u.cl) show_expr (ts->u.cl->length); fprintf(dumpfile, " %d", ts->kind); break; diff --git a/gcc-4.8/gcc/fortran/expr.c b/gcc-4.8/gcc/fortran/expr.c index d16bdb090..0e89a4ce9 100644 --- a/gcc-4.8/gcc/fortran/expr.c +++ b/gcc-4.8/gcc/fortran/expr.c @@ -3555,11 +3555,13 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue) return FAILURE; } - if (!gfc_compare_interfaces (s2, s1, name, 0, 1, - err, sizeof(err), NULL, NULL)) + /* Check F2008Cor2, C729. */ + if (!s2->attr.intrinsic && s2->attr.if_source == IFSRC_UNKNOWN + && !s2->attr.external && !s2->attr.subroutine && !s2->attr.function) { - gfc_error ("Interface mismatch in procedure pointer assignment " - "at %L: %s", &rvalue->where, err); + gfc_error ("Procedure pointer target '%s' at %L must be either an " + "intrinsic, host or use associated, referenced or have " + "the EXTERNAL attribute", s2->name, &rvalue->where); return FAILURE; } @@ -3679,8 +3681,7 @@ gfc_check_pointer_assign (gfc_expr *lvalue, gfc_expr *rvalue) } if (is_implicit_pure && gfc_impure_variable (rvalue->symtree->n.sym)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; - + gfc_unset_implicit_pure (gfc_current_ns->proc_name); if (gfc_has_vector_index (rvalue)) { diff --git a/gcc-4.8/gcc/fortran/frontend-passes.c b/gcc-4.8/gcc/fortran/frontend-passes.c index fdfbce094..27729324c 100644 --- a/gcc-4.8/gcc/fortran/frontend-passes.c +++ b/gcc-4.8/gcc/fortran/frontend-passes.c @@ -623,12 +623,35 @@ cfe_expr_0 (gfc_expr **e, int *walk_subtrees, to insert statements as needed. */ static int -cfe_code (gfc_code **c, int *walk_subtrees ATTRIBUTE_UNUSED, - void *data ATTRIBUTE_UNUSED) +cfe_code (gfc_code **c, int *walk_subtrees, void *data ATTRIBUTE_UNUSED) { current_code = c; inserted_block = NULL; changed_statement = NULL; + + /* Do not do anything inside a WHERE statement; scalar assignments, BLOCKs + and allocation on assigment are prohibited inside WHERE, and finally + masking an expression would lead to wrong-code when replacing + + WHERE (a>0) + b = sum(foo(a) + foo(a)) + END WHERE + + with + + WHERE (a > 0) + tmp = foo(a) + b = sum(tmp + tmp) + END WHERE +*/ + + if ((*c)->op == EXEC_WHERE) + { + *walk_subtrees = 0; + return 0; + } + + return 0; } @@ -1214,7 +1237,9 @@ optimize_comparison (gfc_expr *e, gfc_intrinsic_op op) /* Replace A // B < A // C with B < C, and A // B < C // B with A < C. */ if (op1->ts.type == BT_CHARACTER && op2->ts.type == BT_CHARACTER + && op1->expr_type == EXPR_OP && op1->value.op.op == INTRINSIC_CONCAT + && op2->expr_type == EXPR_OP && op2->value.op.op == INTRINSIC_CONCAT) { gfc_expr *op1_left = op1->value.op.op1; diff --git a/gcc-4.8/gcc/fortran/gfortran.h b/gcc-4.8/gcc/fortran/gfortran.h index 18bbf7954..bd1aeb9ff 100644 --- a/gcc-4.8/gcc/fortran/gfortran.h +++ b/gcc-4.8/gcc/fortran/gfortran.h @@ -2830,6 +2830,7 @@ void gfc_resolve_blocks (gfc_code *, gfc_namespace *); int gfc_impure_variable (gfc_symbol *); int gfc_pure (gfc_symbol *); int gfc_implicit_pure (gfc_symbol *); +void gfc_unset_implicit_pure (gfc_symbol *); int gfc_elemental (gfc_symbol *); gfc_try gfc_resolve_iterator (gfc_iterator *, bool, bool); gfc_try find_forall_index (gfc_expr *, gfc_symbol *, int); diff --git a/gcc-4.8/gcc/fortran/gfortran.info b/gcc-4.8/gcc/fortran/gfortran.info index 676a8d1dd..d7c4d0ca1 100644 --- a/gcc-4.8/gcc/fortran/gfortran.info +++ b/gcc-4.8/gcc/fortran/gfortran.info @@ -1,5 +1,5 @@ -This is doc/gfortran.info, produced by makeinfo version 4.13 from -/d/gcc-4.8.1/gcc-4.8.1/gcc/fortran/gfortran.texi. +This is doc/gfortran.info, produced by makeinfo version 4.12 from +/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/fortran/gfortran.texi. Copyright (C) 1999-2013 Free Software Foundation, Inc. @@ -364,7 +364,7 @@ for them, which work with GNU Fortran. They can be found at Deferred-length character strings of Fortran 2003 supports part of the features of `ISO_VARYING_STRING' and should be considered as -replacement. (Namely, allocatable or pointers of the type +replacement. (Namely, allocatable or pointers of the type `character(len=:)'.)  @@ -544,14 +544,14 @@ accepted by the compiler: `-fbackslash' Change the interpretation of backslashes in string literals from a - single backslash character to "C-style" escape characters. The + single backslash character to "C-style" escape characters. The following combinations are expanded `\a', `\b', `\f', `\n', `\r', `\t', `\v', `\\', and `\0' to the ASCII characters alert, backspace, form feed, newline, carriage return, horizontal tab, vertical tab, backslash, and NUL, respectively. Additionally, `\x'NN, `\u'NNNN and `\U'NNNNNNNN (where each N is a hexadecimal digit) are translated into the Unicode characters corresponding to - the specified code points. All other combinations of a character + the specified code points. All other combinations of a character preceded by \ are unexpanded. `-fmodule-private' @@ -574,13 +574,13 @@ accepted by the compiler: `-ffree-line-length-N' Set column after which characters are ignored in typical free-form - lines in the source file. The default value is 132. N may be + lines in the source file. The default value is 132. N may be `none', meaning that the entire line is meaningful. `-ffree-line-length-0' means the same thing as `-ffree-line-length-none'. `-fmax-identifier-length=N' - Specify the maximum allowed identifier length. Typical values are + Specify the maximum allowed identifier length. Typical values are 31 (Fortran 95) and 63 (Fortran 2003 and Fortran 2008). `-fimplicit-none' @@ -663,13 +663,13 @@ File: gfortran.info, Node: Preprocessing Options, Next: Error and Warning Opti 2.3 Enable and customize preprocessing ====================================== -Preprocessor related options. See section *note Preprocessing and +Preprocessor related options. See section *note Preprocessing and conditional compilation:: for more detailed information on preprocessing in `gfortran'. `-cpp' `-nocpp' - Enable preprocessing. The preprocessor is automatically invoked if + Enable preprocessing. The preprocessor is automatically invoked if the file extension is `.fpp', `.FPP', `.F', `.FOR', `.FTN', `.F90', `.F95', `.F03' or `.F08'. Use this option to manually enable preprocessing of any kind of Fortran file. @@ -677,7 +677,7 @@ preprocessing in `gfortran'. To disable preprocessing of files with any of the above listed extensions, use the negative form: `-nocpp'. - The preprocessor is run in traditional mode. Any restrictions of + The preprocessor is run in traditional mode. Any restrictions of the file-format, especially the limits on line length, apply for preprocessed output as well, so it might be advisable to use the `-ffree-line-length-none' or `-ffixed-line-length-none' options. @@ -685,7 +685,7 @@ preprocessing in `gfortran'. `-dM' Instead of the normal output, generate a list of `'#define'' directives for all the macros defined during the execution of the - preprocessor, including predefined macros. This gives you a way of + preprocessor, including predefined macros. This gives you a way of finding out what is predefined in your version of the preprocessor. Assuming you have no file `foo.f90', the command touch foo.f90; gfortran -cpp -E -dM foo.f90 @@ -714,10 +714,10 @@ preprocessing in `gfortran'. `-fworking-directory' Enable generation of linemarkers in the preprocessor output that will let the compiler know the current working directory at the - time of preprocessing. When this option is enabled, the + time of preprocessing. When this option is enabled, the preprocessor will emit, after the initial linemarker, a second linemarker with the current working directory followed by two - slashes. GCC will use this directory, when it is present in the + slashes. GCC will use this directory, when it is present in the preprocessed input, as the directory emitted as the current working directory in some debugging information formats. This option is implicitly enabled if debugging information is enabled, @@ -729,7 +729,7 @@ preprocessing in `gfortran'. `-idirafter DIR' Search DIR for include files, but do it after all directories specified with `-I' and the standard system directories have been - exhausted. DIR is treated as a system include directory. If dir + exhausted. DIR is treated as a system include directory. If dir begins with `=', then the `=' will be replaced by the sysroot prefix; see `--sysroot' and `-isysroot'. @@ -757,7 +757,7 @@ preprocessing in `gfortran'. Search DIR for header files, after all directories specified by `-I' but before the standard system directories. Mark it as a system directory, so that it gets the same special treatment as is - applied to the standard system directories. If DIR begins with + applied to the standard system directories. If DIR begins with `=', then the `=' will be replaced by the sysroot prefix; see `--sysroot' and `-isysroot'. @@ -780,7 +780,7 @@ preprocessing in `gfortran'. Cancel an assertion with the predicate PREDICATE and answer ANSWER. `-C' - Do not discard comments. All comments are passed through to the + Do not discard comments. All comments are passed through to the output file, except for comments in processed directives, which are deleted along with the directive. @@ -791,11 +791,11 @@ preprocessing in `gfortran'. ordinary source line, since the first token on the line is no longer a `'#''. - Warning: this currently handles C-Style comments only. The + Warning: this currently handles C-Style comments only. The preprocessor does not yet recognize Fortran-style comments. `-CC' - Do not discard comments, including during macro expansion. This is + Do not discard comments, including during macro expansion. This is like `-C', except that comments contained within macros are also passed through to the output file where the macro is expanded. @@ -824,17 +824,17 @@ preprocessing in `gfortran'. If you wish to define a function-like macro on the command line, write its argument list with surrounding parentheses before the - equals sign (if any). Parentheses are meaningful to most shells, - so you will need to quote the option. With sh and csh, + equals sign (if any). Parentheses are meaningful to most shells, + so you will need to quote the option. With sh and csh, `-D'name(args...)=definition'' works. `-D' and `-U' options are processed in the order they are given on - the command line. All -imacros file and -include file options are + the command line. All -imacros file and -include file options are processed after all -D and -U options. `-H' Print the name of each header file used, in addition to other - normal activities. Each name is indented to show how deep in the + normal activities. Each name is indented to show how deep in the `'#include'' stack it is. `-P' @@ -916,7 +916,7 @@ produced by GNU Fortran: `-Wtarget-lifetime', `-Wreal-q-constant' and `-Wunused'. `-Waliasing' - Warn about possible aliasing of dummy arguments. Specifically, it + Warn about possible aliasing of dummy arguments. Specifically, it warns if the same actual argument is associated with a dummy argument with `INTENT(IN)' and a dummy argument with `INTENT(OUT)' in a call with an explicit interface. @@ -933,7 +933,7 @@ produced by GNU Fortran: call bar(a,a) `-Wampersand' - Warn about missing ampersand in continued character constants. The + Warn about missing ampersand in continued character constants. The warning is given with `-Wampersand', `-pedantic', `-std=f95', `-std=f2003' and `-std=f2008'. Note: With no ampersand given in a continued character constant, GNU Fortran assumes continuation at @@ -1018,7 +1018,7 @@ produced by GNU Fortran: By default, tabs are accepted as whitespace, but tabs are not members of the Fortran Character Set. For continuation lines, a tab followed by a digit between 1 and 9 is supported. `-Wno-tabs' - will cause a warning to be issued if a tab is encountered. Note, + will cause a warning to be issued if a tab is encountered. Note, `-Wno-tabs' is active for `-pedantic', `-std=f95', `-std=f2003', `-std=f2008' and `-Wall'. @@ -1034,7 +1034,7 @@ produced by GNU Fortran: implied by `-Wall'. `-Wunused-dummy-argument' - Warn about unused dummy arguments. This option is implied by + Warn about unused dummy arguments. This option is implied by `-Wall'. `-Wunused-parameter' @@ -1104,10 +1104,11 @@ either your program or the GNU Fortran compiler. into internal representation. Only really useful for debugging the GNU Fortran compiler itself. -`-fdump-optimized-tree' +`-fdump-fortran-optimized' Output the parse tree after front-end optimization. Only really useful for debugging the GNU Fortran compiler itself. +`-fdump-parse-tree' Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the GNU Fortran compiler itself. This option is deprecated; use @@ -1146,7 +1147,7 @@ either your program or the GNU Fortran compiler. floating-point exception, and the other POSIX signals that have the action `core'), the Fortran runtime library tries to output a backtrace of the error. `-fno-backtrace' disables the backtrace - generation. This option only has influence for compilation of the + generation. This option only has influence for compilation of the Fortran main program. @@ -1200,12 +1201,12 @@ File: gfortran.info, Node: Link Options, Next: Runtime Options, Prev: Directo ================================ These options come into play when the compiler links object files into -an executable output file. They are meaningless if the compiler is not +an executable output file. They are meaningless if the compiler is not doing a link step. `-static-libgfortran' On systems that provide `libgfortran' as a shared and a static - library, this option forces the use of the static version. If no + library, this option forces the use of the static version. If no shared version of `libgfortran' was built when the compiler was configured, this option has no effect. @@ -1248,7 +1249,7 @@ Fortran. treated as negative in the `SIGN' intrinsic. `-fno-sign-zero' does not print the negative sign of zero values (or values rounded to zero for I/O) and regards zero as positive number in the `SIGN' - intrinsic for compatibility with Fortran 77. The default is + intrinsic for compatibility with Fortran 77. The default is `-fsign-zero'.  @@ -1268,7 +1269,7 @@ the other form by either removing `no-' or adding it. `-fno-automatic' Treat each program unit (except those marked as RECURSIVE) as if the `SAVE' statement were specified for every local variable and - array referenced in it. Does not affect common blocks. (Some + array referenced in it. Does not affect common blocks. (Some Fortran compilers provide this option under the name `-static' or `-save'.) The default, which is `-fautomatic', uses the stack for local variables smaller than the value given by @@ -1420,7 +1421,7 @@ the other form by either removing `no-' or adding it. `array-temps' Warns at run time when for passing an actual argument a - temporary array had to be generated. The information + temporary array had to be generated. The information generated by this warning is sometimes useful in optimization, in order to avoid such temporaries. @@ -1479,7 +1480,7 @@ the other form by either removing `no-' or adding it. print '(10(I0,1X))', i end program test - _Caution: This option can lead to long compile times and + _Caution: This option can lead to long compile times and excessively large object files._ The default value for N is 65535. @@ -1503,7 +1504,7 @@ the other form by either removing `no-' or adding it. arrays, even those of unknown size onto stack memory. If your program uses very large local arrays it is possible that you will have to extend your runtime limits for stack memory on some - operating systems. This flag is enabled by default at optimization + operating systems. This flag is enabled by default at optimization level `-Ofast'. `-fpack-derived' @@ -1549,7 +1550,7 @@ the other form by either removing `no-' or adding it. `-frecursive' Allow indirect recursion by forcing all local arrays to be - allocated on the stack. This flag cannot be used together with + allocated on the stack. This flag cannot be used together with `-fmax-stack-var-size=' or `-fno-automatic'. `-finit-local-zero' @@ -1608,7 +1609,7 @@ the other form by either removing `no-' or adding it. `-frealloc-lhs' An allocatable left-hand side of an intrinsic assignment is automatically (re)allocated if it is either unallocated or has a - different shape. The option is enabled by default except when + different shape. The option is enabled by default except when `-std=f95' is given. See also `-Wrealloc-lhs'. `-faggressive-function-elimination' @@ -1651,7 +1652,7 @@ behavior of programs compiled with GNU Fortran.  File: gfortran.info, Node: Runtime, Next: Fortran 2003 and 2008 status, Prev: Invoking GNU Fortran, Up: Top -3 Runtime: Influencing runtime behavior with environment variables +3 Runtime: Influencing runtime behavior with environment variables ******************************************************************* The behavior of the `gfortran' can be influenced by environment @@ -1906,7 +1907,7 @@ can be found below. See also the wiki page and arrays, including unlimited polymorphism. * Generic interface names, which have the same name as derived types, - are now supported. This allows one to write constructor functions. + are now supported. This allows one to write constructor functions. Note that Fortran does not support static constructor functions. For static variables, only default initialization or structure-constructor initialization are available. @@ -1927,7 +1928,7 @@ can be found below. See also the wiki page * Reallocation on assignment: If an intrinsic assignment is used, an allocatable variable on the left-hand side is automatically allocated (if unallocated) or reallocated (if the shape is - different). Currently, scalar deferred character length left-hand + different). Currently, scalar deferred character length left-hand sides are correctly handled but arrays are not yet fully implemented. @@ -2025,7 +2026,7 @@ downloaded free of charge from `http://www.nag.co.uk/sc22wg5/links.html'. Fortran is developed by the Working Group 5 of Sub-Committee 22 of the Joint Technical Committee 1 of the International Organization for Standardization and the -International Electrotechnical Commission (IEC). This group is known as +International Electrotechnical Commission (IEC). This group is known as WG5 (http://www.nag.co.uk/sc22wg5/). The GNU Fortran compiler supports several of the new features of @@ -2272,9 +2273,9 @@ This section contains a brief overview of data and metadata consistency and durability issues when doing I/O. With respect to durability, GNU Fortran makes no effort to ensure -that data is committed to stable storage. If this is required, the GNU +that data is committed to stable storage. If this is required, the GNU Fortran programmer can use the intrinsic `FNUM' to retrieve the low -level file descriptor corresponding to an open Fortran unit. Then, +level file descriptor corresponding to an open Fortran unit. Then, using e.g. the `ISO_C_BINDING' feature, one can call the underlying system call to flush dirty data to stable storage, such as `fsync' on POSIX, `_commit' on MingW, or `fcntl(fd, F_FULLSYNC, 0)' on Mac OS X. @@ -2307,8 +2308,8 @@ The following example shows how to call fsync: if (ret /= 0) stop "Error calling FSYNC" With respect to consistency, for regular files GNU Fortran uses -buffered I/O in order to improve performance. This buffer is flushed -automatically when full and in some other situations, e.g. when closing +buffered I/O in order to improve performance. This buffer is flushed +automatically when full and in some other situations, e.g. when closing a unit. It can also be explicitly flushed with the `FLUSH' statement. Also, the buffering can be turned off with the `GFORTRAN_UNBUFFERED_ALL' and `GFORTRAN_UNBUFFERED_PRECONNECTED' @@ -2318,7 +2319,7 @@ done in order to allow other processes to see data that GNU Fortran has written, as follows. The Windows platform supports a relaxed metadata consistency model, -where file metadata is written to the directory lazily. This means +where file metadata is written to the directory lazily. This means that, for instance, the `dir' command can show a stale size for a file. One can force a directory metadata update by closing the unit, or by calling `_commit' on the file descriptor. Note, though, that `_commit' @@ -2326,7 +2327,7 @@ will force all dirty data to stable storage, which is often a very slow operation. The Network File System (NFS) implements a relaxed consistency model -called open-to-close consistency. Closing a file forces dirty data and +called open-to-close consistency. Closing a file forces dirty data and metadata to be flushed to the server, and opening a file forces the client to contact the server in order to revalidate cached data. `fsync' will also force a flush of dirty data and metadata to the @@ -3185,7 +3186,7 @@ In order to ensure that exactly the same variable type and kind is used in C and Fortran, the named constants shall be used which are defined in the `ISO_C_BINDING' intrinsic module. That module contains named constants for kind parameters and character named constants for the -escape sequences in C. For a list of the constants, see *note +escape sequences in C. For a list of the constants, see *note ISO_C_BINDING::.  @@ -3263,13 +3264,13 @@ File: gfortran.info, Node: Interoperable Subroutines and Functions, Next: Work --------------------------------------------- Subroutines and functions have to have the `BIND(C)' attribute to be -compatible with C. The dummy argument declaration is relatively +compatible with C. The dummy argument declaration is relatively straightforward. However, one needs to be careful because C uses call-by-value by default while Fortran behaves usually similar to call-by-reference. Furthermore, strings and pointers are handled differently. Note that in Fortran 2003 and 2008 only explicit size and assumed-size arrays are supported but not assumed-shape or -deferred-shape (i.e. allocatable or pointer) arrays. However, those +deferred-shape (i.e. allocatable or pointer) arrays. However, those are allowed since the Technical Specification 29113, see *note Further Interoperability of Fortran with C:: @@ -3504,7 +3505,7 @@ File: gfortran.info, Node: Further Interoperability of Fortran with C, Prev: W The Technical Specification ISO/IEC TS 29113:2012 on further interoperability of Fortran with C extends the interoperability support -of Fortran 2003 and Fortran 2008. Besides removing some restrictions +of Fortran 2003 and Fortran 2008. Besides removing some restrictions and constraints, it adds assumed-type (`TYPE(*)') and assumed-rank (`dimension') variables and allows for interoperability of assumed-shape, assumed-rank and deferred-shape arrays, including @@ -3512,7 +3513,7 @@ allocatables and pointers. Note: Currently, GNU Fortran does not support the array descriptor (dope vector) as specified in the Technical Specification, but uses an -array descriptor with different fields. The Chasm Language +array descriptor with different fields. The Chasm Language Interoperability Tools, `http://chasm-interop.sourceforge.net/', provide an interface to GNU Fortran's array descriptor. @@ -3556,7 +3557,7 @@ are supported by GNU Fortran: Currently unimplemented: * GNU Fortran always uses an array descriptor, which does not match - the one of the Technical Specification. The + the one of the Technical Specification. The `ISO_Fortran_binding.h' header file and the C functions it specifies are not available. @@ -3577,7 +3578,7 @@ allow the user to choose specific implementation details, compiler directives can be used to set attributes of variables and procedures which are not part of the standard. Whether a given attribute is supported and its exact effects depend on both the operating system and -on the processor; see *note C Extensions: (gcc)Top. for details. +on the processor; see *note C Extensions: (gcc)Top. for details. For procedures and procedure pointers, the following attributes can be used to change the calling convention: @@ -3676,9 +3677,9 @@ _Syntax_: `void _gfortran_set_args (int argc, char *argv[])' _Arguments_: - ARGC number of command line argument strings - ARGV the command-line argument strings; argv[0] is - the pathname of the executable itself. + ARGC number of command line argument strings + ARGV the command-line argument strings; argv[0] is + the pathname of the executable itself. _Example_: int main (int argc, char *argv[]) @@ -3707,11 +3708,11 @@ _Syntax_: `void _gfortran_set_options (int num, int options[])' _Arguments_: - NUM number of options passed - ARGV The list of flag values + NUM number of options passed + ARGV The list of flag values _option flag list_: - OPTION[0] Allowed standard; can give run-time errors if + OPTION[0] Allowed standard; can give run-time errors if e.g. an input-output edit descriptor is invalid in a given standard. Possible values are (bitwise or-ed) `GFC_STD_F77' (1), @@ -3722,23 +3723,23 @@ _option flag list_: (256) and GFC_STD_F2008_TS (512). Default: `GFC_STD_F95_OBS | GFC_STD_F95_DEL | GFC_STD_F95 | GFC_STD_F2003 | GFC_STD_F2008 | - GFC_STD_F2008_TS | GFC_STD_F2008_OBS | - GFC_STD_F77 | GFC_STD_GNU | GFC_STD_LEGACY'. - OPTION[1] Standard-warning flag; prints a warning to + GFC_STD_F2008_TS | GFC_STD_F2008_OBS | + GFC_STD_F77 | GFC_STD_GNU | GFC_STD_LEGACY'. + OPTION[1] Standard-warning flag; prints a warning to standard error. Default: `GFC_STD_F95_DEL | - GFC_STD_LEGACY'. + GFC_STD_LEGACY'. OPTION[2] If non zero, enable pedantic checking. Default: off. - OPTION[3] Unused. - OPTION[4] If non zero, enable backtracing on run-time + OPTION[3] Unused. + OPTION[4] If non zero, enable backtracing on run-time errors. Default: off. Note: Installs a signal handler and requires command-line initialization using `_gfortran_set_args'. - OPTION[5] If non zero, supports signed zeros. Default: - enabled. + OPTION[5] If non zero, supports signed zeros. Default: + enabled. OPTION[6] Enables run-time checking. Possible values are (bitwise or-ed): GFC_RTCHECK_BOUNDS (1), - GFC_RTCHECK_ARRAY_TEMPS (2), + GFC_RTCHECK_ARRAY_TEMPS (2), GFC_RTCHECK_RECURSION (4), GFC_RTCHECK_DO (16), GFC_RTCHECK_POINTER (32). Default: disabled. @@ -3762,10 +3763,10 @@ _Syntax_: `void _gfortran_set_convert (int conv)' _Arguments_: - CONV Endian conversion, possible values: - GFC_CONVERT_NATIVE (0, default), - GFC_CONVERT_SWAP (1), GFC_CONVERT_BIG (2), - GFC_CONVERT_LITTLE (3). + CONV Endian conversion, possible values: + GFC_CONVERT_NATIVE (0, default), + GFC_CONVERT_SWAP (1), GFC_CONVERT_BIG (2), + GFC_CONVERT_LITTLE (3). _Example_: int main (int argc, char *argv[]) @@ -3817,8 +3818,8 @@ _Syntax_: `void _gfortran_set_fpe (int val)' _Arguments_: - OPTION[0] IEEE exceptions. Possible values are (bitwise - or-ed) zero (0, default) no trapping, + OPTION[0] IEEE exceptions. Possible values are (bitwise + or-ed) zero (0, default) no trapping, `GFC_FPE_INVALID' (1), `GFC_FPE_DENORMAL' (2), `GFC_FPE_ZERO' (4), `GFC_FPE_OVERFLOW' (8), `GFC_FPE_UNDERFLOW' (16), and @@ -4241,19 +4242,19 @@ _Example_: end program test_abs _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ABS(A)' `REAL(4) A' `REAL(4)' Fortran 77 and - later + later `CABS(A)' `COMPLEX(4) `REAL(4)' Fortran 77 and - A' later + A' later `DABS(A)' `REAL(8) A' `REAL(8)' Fortran 77 and - later + later `IABS(A)' `INTEGER(4) `INTEGER(4)' Fortran 77 and - A' later + A' later `ZABS(A)' `COMPLEX(8) `COMPLEX(8)' GNU extension - A' + A' `CDABS(A)' `COMPLEX(8) `COMPLEX(8)' GNU extension - A' + A'  File: gfortran.info, Node: ACCESS, Next: ACHAR, Prev: ABS, Up: Intrinsic Procedures @@ -4263,7 +4264,7 @@ File: gfortran.info, Node: ACCESS, Next: ACHAR, Prev: ABS, Up: Intrinsic Pro _Description_: `ACCESS(NAME, MODE)' checks whether the file NAME exists, is - readable, writable or executable. Except for the executable check, + readable, writable or executable. Except for the executable check, `ACCESS' can be replaced by Fortran 95's `INQUIRE'. _Standard_: @@ -4280,7 +4281,7 @@ _Arguments_: file name. Tailing blank are ignored unless the character `achar(0)' is present, then all characters up to and excluding `achar(0)' are - used as file name. + used as file name. MODE Scalar `CHARACTER' of default kind with the file access mode, may be any concatenation of `"r"' (readable), `"w"' (writable) and `"x"' @@ -4387,11 +4388,11 @@ _Example_: end program test_acos _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ACOS(X)' `REAL(4) X' `REAL(4)' Fortran 77 and - later + later `DACOS(X)' `REAL(8) X' `REAL(8)' Fortran 77 and - later + later _See also_: Inverse function: *note COS:: @@ -4419,8 +4420,8 @@ _Arguments_: X The type shall be `REAL' or `COMPLEX'. _Return value_: - The return value has the same type and kind as X. If X is complex, - the imaginary part of the result is in radians and lies between 0 + The return value has the same type and kind as X. If X is complex, + the imaginary part of the result is in radians and lies between 0 \leq \Im \acosh(x) \leq \pi. _Example_: @@ -4430,7 +4431,7 @@ _Example_: END PROGRAM _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DACOSH(X)' `REAL(8) X' `REAL(8)' GNU extension _See also_: @@ -4548,10 +4549,10 @@ _Example_: end program test_aimag _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `AIMAG(Z)' `COMPLEX Z' `REAL' GNU extension `DIMAG(Z)' `COMPLEX(8) `REAL(8)' GNU extension - Z' + Z' `IMAG(Z)' `COMPLEX Z' `REAL' GNU extension `IMAGPART(Z)' `COMPLEX Z' `REAL' GNU extension @@ -4599,11 +4600,11 @@ _Example_: end program test_aint _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `AINT(A)' `REAL(4) A' `REAL(4)' Fortran 77 and - later + later `DINT(A)' `REAL(8) A' `REAL(8)' Fortran 77 and - later + later  File: gfortran.info, Node: ALARM, Next: ALL, Prev: AINT, Up: Intrinsic Procedures @@ -4629,7 +4630,7 @@ _Syntax_: `CALL ALARM(SECONDS, HANDLER [, STATUS])' _Arguments_: - SECONDS The type of the argument shall be a scalar + SECONDS The type of the argument shall be a scalar `INTEGER'. It is `INTENT(IN)'. HANDLER Signal handler (`INTEGER FUNCTION' or `SUBROUTINE') or dummy/global `INTEGER' @@ -4673,10 +4674,10 @@ _Syntax_: _Arguments_: MASK The type of the argument shall be `LOGICAL' and - it shall not be scalar. + it shall not be scalar. DIM (Optional) DIM shall be a scalar integer with a value that lies between one and the rank of - MASK. + MASK. _Return value_: `ALL(MASK)' returns a scalar value of type `LOGICAL' where the @@ -4685,11 +4686,11 @@ _Return value_: with the rank of MASK minus 1. The shape is determined from the shape of MASK where the DIM dimension is elided. - (A) + (A) `ALL(MASK)' is true if all elements of MASK are true. It also is true if MASK has zero size; otherwise, it is false. - (B) + (B) If the rank of MASK is one, then `ALL(MASK,DIM)' is equivalent to `ALL(MASK)'. If the rank is greater than one, then `ALL(MASK,DIM)' is determined by applying `ALL' to the array @@ -4775,7 +4776,7 @@ _Syntax_: _Arguments_: I The type shall be either a scalar `INTEGER' type or a scalar `LOGICAL' type. - J The type shall be the same as the type of I. + J The type shall be the same as the type of I. _Return value_: The return type is either a scalar `INTEGER' or a scalar @@ -4839,11 +4840,11 @@ _Example_: end program test_anint _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `AINT(A)' `REAL(4) A' `REAL(4)' Fortran 77 and - later + later `DNINT(A)' `REAL(8) A' `REAL(8)' Fortran 77 and - later + later  File: gfortran.info, Node: ANY, Next: ASIN, Prev: ANINT, Up: Intrinsic Procedures @@ -4866,10 +4867,10 @@ _Syntax_: _Arguments_: MASK The type of the argument shall be `LOGICAL' and - it shall not be scalar. + it shall not be scalar. DIM (Optional) DIM shall be a scalar integer with a value that lies between one and the rank of - MASK. + MASK. _Return value_: `ANY(MASK)' returns a scalar value of type `LOGICAL' where the @@ -4878,12 +4879,12 @@ _Return value_: with the rank of MASK minus 1. The shape is determined from the shape of MASK where the DIM dimension is elided. - (A) + (A) `ANY(MASK)' is true if any element of MASK is true; otherwise, it is false. It also is false if MASK has zero size. - (B) + (B) If the rank of MASK is one, then `ANY(MASK,DIM)' is equivalent to `ANY(MASK)'. If the rank is greater than one, then `ANY(MASK,DIM)' is determined by applying `ANY' to the array @@ -4941,11 +4942,11 @@ _Example_: end program test_asin _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ASIN(X)' `REAL(4) X' `REAL(4)' Fortran 77 and - later + later `DASIN(X)' `REAL(8) X' `REAL(8)' Fortran 77 and - later + later _See also_: Inverse function: *note SIN:: @@ -4973,7 +4974,7 @@ _Arguments_: X The type shall be `REAL' or `COMPLEX'. _Return value_: - The return value is of the same type and kind as X. If X is + The return value is of the same type and kind as X. If X is complex, the imaginary part of the result is in radians and lies between -\pi/2 \leq \Im \asinh(x) \leq \pi/2. @@ -4984,7 +4985,7 @@ _Example_: END PROGRAM _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DASINH(X)' `REAL(8) X' `REAL(8)' GNU extension. _See also_: @@ -5011,39 +5012,39 @@ _Syntax_: _Arguments_: POINTER POINTER shall have the `POINTER' attribute and - it can be of any type. - TARGET (Optional) TARGET shall be a pointer or a - target. It must have the same type, kind type - parameter, and array rank as POINTER. + it can be of any type. + TARGET (Optional) TARGET shall be a pointer or a + target. It must have the same type, kind type + parameter, and array rank as POINTER. The association status of neither POINTER nor TARGET shall be undefined. _Return value_: `ASSOCIATED(POINTER)' returns a scalar value of type `LOGICAL(4)'. There are several cases: - (A) When the optional TARGET is not present then + (A) When the optional TARGET is not present then `ASSOCIATED(POINTER)' is true if POINTER is associated with a target; otherwise, it returns false. - (B) If TARGET is present and a scalar target, the result is true if + (B) If TARGET is present and a scalar target, the result is true if TARGET is not a zero-sized storage sequence and the target associated with POINTER occupies the same storage units. If POINTER is disassociated, the result is false. - (C) If TARGET is present and an array target, the result is true if + (C) If TARGET is present and an array target, the result is true if TARGET and POINTER have the same shape, are not zero-sized arrays, are arrays whose elements are not zero-sized storage sequences, and TARGET and POINTER occupy the same storage units in array element order. As in case(B), the result is false, if POINTER is disassociated. - (D) If TARGET is present and an scalar pointer, the result is true + (D) If TARGET is present and an scalar pointer, the result is true if TARGET is associated with POINTER, the target associated with TARGET are not zero-sized storage sequences and occupy the same storage units. The result is false, if either TARGET or POINTER is disassociated. - (E) If TARGET is present and an array pointer, the result is true if + (E) If TARGET is present and an array pointer, the result is true if target associated with POINTER and the target associated with TARGET have the same shape, are not zero-sized arrays, are arrays whose elements are not zero-sized storage sequences, @@ -5086,12 +5087,12 @@ _Syntax_: _Arguments_: X The type shall be `REAL' or `COMPLEX'; if Y is - present, X shall be REAL. - Y shall - be of the - same type - and kind - as X. + present, X shall be REAL. + Y shall + be of the + same type + and kind + as X. _Return value_: The return value is of the same type and kind as X. If Y is @@ -5106,11 +5107,11 @@ _Example_: end program test_atan _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ATAN(X)' `REAL(4) X' `REAL(4)' Fortran 77 and - later + later `DATAN(X)' `REAL(8) X' `REAL(8)' Fortran 77 and - later + later _See also_: Inverse function: *note TAN:: @@ -5139,9 +5140,9 @@ _Syntax_: _Arguments_: Y The type shall be `REAL'. - X The type and kind type parameter shall be the - same as Y. If Y is zero, then X must be - nonzero. + X The type and kind type parameter shall be the + same as Y. If Y is zero, then X must be + nonzero. _Return value_: The return value has the same type and kind type parameter as Y. It @@ -5160,11 +5161,11 @@ _Example_: end program test_atan2 _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ATAN2(X, `REAL(4) X, `REAL(4)' Fortran 77 and - Y)' Y' later + Y)' Y' later `DATAN2(X, `REAL(8) X, `REAL(8)' Fortran 77 and - Y)' Y' later + Y)' Y' later  File: gfortran.info, Node: ATANH, Next: ATOMIC_DEFINE, Prev: ATAN2, Up: Intrinsic Procedures @@ -5188,7 +5189,7 @@ _Arguments_: X The type shall be `REAL' or `COMPLEX'. _Return value_: - The return value has same type and kind as X. If X is complex, the + The return value has same type and kind as X. If X is complex, the imaginary part of the result is in radians and lies between -\pi/2 \leq \Im \atanh(x) \leq \pi/2. @@ -5199,7 +5200,7 @@ _Example_: END PROGRAM _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DATANH(X)' `REAL(8) X' `REAL(8)' GNU extension _See also_: @@ -5225,11 +5226,11 @@ _Syntax_: `CALL ATOMIC_DEFINE(ATOM, VALUE)' _Arguments_: - ATOM Scalar coarray or coindexed variable of either + ATOM Scalar coarray or coindexed variable of either integer type with `ATOMIC_INT_KIND' kind or logical type with `ATOMIC_LOGICAL_KIND' kind. - VALURE Scalar and of the same type as ATOM. If the + VALURE Scalar and of the same type as ATOM. If the kind is different, the value is converted to the kind of ATOM. @@ -5264,11 +5265,11 @@ _Syntax_: `CALL ATOMIC_REF(VALUE, ATOM)' _Arguments_: - VALURE Scalar and of the same type as ATOM. If the + VALURE Scalar and of the same type as ATOM. If the kind is different, the value is converted to the kind of ATOM. - ATOM Scalar coarray or coindexed variable of either + ATOM Scalar coarray or coindexed variable of either integer type with `ATOMIC_INT_KIND' kind or logical type with `ATOMIC_LOGICAL_KIND' kind. @@ -5297,7 +5298,7 @@ File: gfortran.info, Node: BACKTRACE, Next: BESSEL_J0, Prev: ATOMIC_REF, Up: _Description_: `BACKTRACE' shows a backtrace at an arbitrary place in user code. - Program execution continues normally afterwards. The backtrace + Program execution continues normally afterwards. The backtrace information is printed to the unit corresponding to `ERROR_UNIT' in `ISO_FORTRAN_ENV'. @@ -5338,11 +5339,11 @@ _Syntax_: _Arguments_: X The type shall be `REAL', and it shall be - scalar. + scalar. _Return value_: The return value is of type `REAL' and lies in the range - - 0.4027... \leq Bessel (0,x) \leq 1. It has the same kind as X. + 0.4027... \leq Bessel (0,x) \leq 1. It has the same kind as X. _Example_: program test_besj0 @@ -5351,7 +5352,7 @@ _Example_: end program test_besj0 _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DBESJ0(X)' `REAL(8) X' `REAL(8)' GNU extension  @@ -5376,11 +5377,11 @@ _Syntax_: _Arguments_: X The type shall be `REAL', and it shall be - scalar. + scalar. _Return value_: The return value is of type `REAL' and it lies in the range - - 0.5818... \leq Bessel (0,x) \leq 0.5818 . It has the same kind as + 0.5818... \leq Bessel (0,x) \leq 0.5818 . It has the same kind as X. _Example_: @@ -5390,7 +5391,7 @@ _Example_: end program test_besj1 _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DBESJ1(X)' `REAL(8) X' `REAL(8)' GNU extension  @@ -5422,9 +5423,9 @@ _Syntax_: _Arguments_: N Shall be a scalar or an array of type `INTEGER'. - N1 Shall be a non-negative scalar of type + N1 Shall be a non-negative scalar of type `INTEGER'. - N2 Shall be a non-negative scalar of type + N2 Shall be a non-negative scalar of type `INTEGER'. X Shall be a scalar or an array of type `REAL'; for `BESSEL_JN(N1, N2, X)' it shall be scalar. @@ -5445,9 +5446,9 @@ _Example_: end program test_besjn _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DBESJN(N, `INTEGER N' `REAL(8)' GNU extension - X)' + X)' `REAL(8) X'  @@ -5472,7 +5473,7 @@ _Syntax_: _Arguments_: X The type shall be `REAL', and it shall be - scalar. + scalar. _Return value_: The return value is a scalar of type `REAL'. It has the same kind @@ -5485,7 +5486,7 @@ _Example_: end program test_besy0 _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DBESY0(X)' `REAL(8) X' `REAL(8)' GNU extension  @@ -5510,7 +5511,7 @@ _Syntax_: _Arguments_: X The type shall be `REAL', and it shall be - scalar. + scalar. _Return value_: The return value is a scalar of type `REAL'. It has the same kind @@ -5523,7 +5524,7 @@ _Example_: end program test_besy1 _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DBESY1(X)' `REAL(8) X' `REAL(8)' GNU extension  @@ -5555,9 +5556,9 @@ _Syntax_: _Arguments_: N Shall be a scalar or an array of type `INTEGER' . - N1 Shall be a non-negative scalar of type + N1 Shall be a non-negative scalar of type `INTEGER'. - N2 Shall be a non-negative scalar of type + N2 Shall be a non-negative scalar of type `INTEGER'. X Shall be a scalar or an array of type `REAL'; for `BESSEL_YN(N1, N2, X)' it shall be scalar. @@ -5578,7 +5579,7 @@ _Example_: end program test_besyn _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DBESYN(N,X)' `INTEGER N' `REAL(8)' GNU extension `REAL(8) X' @@ -5793,7 +5794,7 @@ _Syntax_: _Arguments_: C_PTR_1 Scalar of the type `C_PTR' or `C_FUNPTR'. - C_PTR_2 (Optional) Scalar of the same type as C_PTR_1. + C_PTR_2 (Optional) Scalar of the same type as C_PTR_1. _Return value_: The return value is of type `LOGICAL'; it is `.false.' if either @@ -5834,7 +5835,7 @@ _Syntax_: _Arguments_: CPTR scalar of the type `C_PTR'. It is `INTENT(IN)'. - FPTR pointer interoperable with CPTR. It is + FPTR pointer interoperable with CPTR. It is `INTENT(OUT)'. SHAPE (Optional) Rank-one array of type `INTEGER' with `INTENT(IN)'. It shall be present if and @@ -5882,7 +5883,7 @@ _Syntax_: _Arguments_: CPTR scalar of the type `C_FUNPTR'. It is `INTENT(IN)'. - FPTR procedure pointer interoperable with CPTR. It + FPTR procedure pointer interoperable with CPTR. It is `INTENT(OUT)'. _Example_: @@ -5930,8 +5931,8 @@ _Syntax_: `RESULT = C_FUNLOC(x)' _Arguments_: - X Interoperable function or pointer to such - function. + X Interoperable function or pointer to such + function. _Return value_: The return value is of type `C_FUNPTR' and contains the C address @@ -6028,8 +6029,8 @@ _Syntax_: `N = C_SIZEOF(X)' _Arguments_: - X The argument shall be an interoperable data - entity. + X The argument shall be an interoperable data + entity. _Return value_: The return value is of type integer and of the system-dependent @@ -6129,7 +6130,7 @@ _Example_: end program test_char _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `CHAR(I)' `INTEGER I' `CHARACTER(LEN=1)'F77 and later _Note_: @@ -6164,11 +6165,11 @@ _Syntax_: _Arguments_: NAME The type shall be `CHARACTER' of default kind - and shall specify a valid path within the file - system. + and shall specify a valid path within the file + system. STATUS (Optional) `INTEGER' status flag of the default - kind. Returns 0 on success, and a system - specific and nonzero error code otherwise. + kind. Returns 0 on success, and a system + specific and nonzero error code otherwise. _Example_: PROGRAM test_chdir @@ -6210,15 +6211,15 @@ _Arguments_: file name. Trailing blanks are ignored unless the character `achar(0)' is present, then all characters up to and excluding `achar(0)' are - used as the file name. + used as the file name. MODE Scalar `CHARACTER' of default kind giving the - file permission. MODE uses the same syntax as + file permission. MODE uses the same syntax as the `chmod' utility as defined by the POSIX standard. The argument shall either be a string of a nonnegative octal number or a symbolic mode. STATUS (optional) scalar `INTEGER', which is `0' on - success and nonzero otherwise. + success and nonzero otherwise. _Return value_: In either syntax, STATUS is set to `0' on success and nonzero @@ -6309,7 +6310,7 @@ _Syntax_: `RESULT = COMMAND_ARGUMENT_COUNT()' _Arguments_: - None + None _Return value_: The return value is an `INTEGER' of default kind. @@ -6476,10 +6477,10 @@ _Example_: end program test_conjg _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `CONJG(Z)' `COMPLEX Z' `COMPLEX' GNU extension `DCONJG(Z)' `COMPLEX(8) `COMPLEX(8)' GNU extension - Z' + Z'  File: gfortran.info, Node: COS, Next: COSH, Prev: CONJG, Up: Intrinsic Procedures @@ -6503,9 +6504,9 @@ _Arguments_: X The type shall be `REAL' or `COMPLEX'. _Return value_: - The return value is of the same type and kind as X. The real part + The return value is of the same type and kind as X. The real part of the result is in radians. If X is of the type `REAL', the - return value lies in the range -1 \leq \cos (x) \leq 1. + return value lies in the range -1 \leq \cos (x) \leq 1. _Example_: program test_cos @@ -6514,17 +6515,17 @@ _Example_: end program test_cos _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `COS(X)' `REAL(4) X' `REAL(4)' Fortran 77 and - later + later `DCOS(X)' `REAL(8) X' `REAL(8)' Fortran 77 and - later + later `CCOS(X)' `COMPLEX(4) `COMPLEX(4)' Fortran 77 and - X' later + X' later `ZCOS(X)' `COMPLEX(8) `COMPLEX(8)' GNU extension - X' + X' `CDCOS(X)' `COMPLEX(8) `COMPLEX(8)' GNU extension - X' + X' _See also_: Inverse function: *note ACOS:: @@ -6552,7 +6553,7 @@ _Arguments_: X The type shall be `REAL' or `COMPLEX'. _Return value_: - The return value has same type and kind as X. If X is complex, the + The return value has same type and kind as X. If X is complex, the imaginary part of the result is in radians. If X is `REAL', the return value has a lower bound of one, \cosh (x) \geq 1. @@ -6563,11 +6564,11 @@ _Example_: end program test_cosh _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `COSH(X)' `REAL(4) X' `REAL(4)' Fortran 77 and - later + later `DCOSH(X)' `REAL(8) X' `REAL(8)' Fortran 77 and - later + later _See also_: Inverse function: *note ACOSH:: @@ -6644,7 +6645,7 @@ _Description_: execution time. If a time source is available, time will be reported with - microsecond resolution. If no time source is available, TIME is + microsecond resolution. If no time source is available, TIME is set to `-1.0'. Note that TIME may contain a, system dependent, arbitrary offset @@ -6706,7 +6707,7 @@ _Syntax_: `RESULT = CSHIFT(ARRAY, SHIFT [, DIM])' _Arguments_: - ARRAY Shall be an array of any type. + ARRAY Shall be an array of any type. SHIFT The type shall be `INTEGER'. DIM The type shall be `INTEGER'. @@ -6793,7 +6794,7 @@ _Description_: `INTENT(OUT)' and has form ccyymmdd. TIME is `INTENT(OUT)' and has form hhmmss.sss. ZONE is `INTENT(OUT)' and has form (+-)hhmm, representing the difference with respect to Coordinated Universal - Time (UTC). Unavailable time and date parameters return blanks. + Time (UTC). Unavailable time and date parameters return blanks. VALUES is `INTENT(OUT)' and provides the following: @@ -6806,7 +6807,7 @@ _Description_: `VALUE(6)': The minutes of the hour `VALUE(7)': The seconds of the minute `VALUE(8)': The milliseconds of the - second + second _Standard_: Fortran 95 and later @@ -6819,12 +6820,12 @@ _Syntax_: _Arguments_: DATE (Optional) The type shall be `CHARACTER(LEN=8)' - or larger, and of default kind. + or larger, and of default kind. TIME (Optional) The type shall be `CHARACTER(LEN=10)' or larger, and of default kind. ZONE (Optional) The type shall be `CHARACTER(LEN=5)' - or larger, and of default kind. + or larger, and of default kind. VALUES (Optional) The type shall be `INTEGER(8)'. _Return value_: @@ -6985,7 +6986,7 @@ _Syntax_: _Arguments_: X The type shall be `INTEGER' or `REAL' - Y The type shall be the same type and kind as X. + Y The type shall be the same type and kind as X. _Return value_: The return value is of type `INTEGER' or `REAL'. @@ -7001,13 +7002,13 @@ _Example_: end program test_dim _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DIM(X,Y)' `REAL(4) X, `REAL(4)' Fortran 77 and - Y' later + Y' later `IDIM(X,Y)' `INTEGER(4) `INTEGER(4)' Fortran 77 and - X, Y' later + X, Y' later `DDIM(X,Y)' `REAL(8) X, `REAL(8)' Fortran 77 and - Y' later + Y' later  File: gfortran.info, Node: DOT_PRODUCT, Next: DPROD, Prev: DIM, Up: Intrinsic Procedures @@ -7036,7 +7037,7 @@ _Syntax_: _Arguments_: VECTOR_A The type shall be numeric or `LOGICAL', rank 1. - VECTOR_B The type shall be numeric if VECTOR_A is of + VECTOR_B The type shall be numeric if VECTOR_A is of numeric type or `LOGICAL' if VECTOR_A is of type `LOGICAL'. VECTOR_B shall be a rank-one array. @@ -7093,9 +7094,9 @@ _Example_: end program test_dprod _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DPROD(X,Y)' `REAL(4) X, `REAL(4)' Fortran 77 and - Y' later + Y' later  @@ -7155,12 +7156,12 @@ _Syntax_: _Arguments_: I Shall be of type `INTEGER' or a BOZ constant. J Shall be of type `INTEGER' or a BOZ constant. - If both I and J have integer type, then they - shall have the same kind type parameter. I and - J shall not both be BOZ constants. + If both I and J have integer type, then they + shall have the same kind type parameter. I and + J shall not both be BOZ constants. SHIFT Shall be of type `INTEGER'. It shall be - nonnegative. If I is not a BOZ constant, then - SHIFT shall be less than or equal to + nonnegative. If I is not a BOZ constant, then + SHIFT shall be less than or equal to `BIT_SIZE(I)'; otherwise, SHIFT shall be less than or equal to `BIT_SIZE(J)'. @@ -7195,12 +7196,12 @@ _Syntax_: _Arguments_: I Shall be of type `INTEGER' or a BOZ constant. J Shall be of type `INTEGER' or a BOZ constant. - If both I and J have integer type, then they - shall have the same kind type parameter. I and - J shall not both be BOZ constants. + If both I and J have integer type, then they + shall have the same kind type parameter. I and + J shall not both be BOZ constants. SHIFT Shall be of type `INTEGER'. It shall be - nonnegative. If I is not a BOZ constant, then - SHIFT shall be less than or equal to + nonnegative. If I is not a BOZ constant, then + SHIFT shall be less than or equal to `BIT_SIZE(I)'; otherwise, SHIFT shall be less than or equal to `BIT_SIZE(J)'. @@ -7250,7 +7251,7 @@ _Description_: `VALUES(1)': User time in seconds. `VALUES(2)': System time in seconds. `TIME': Run time since start in - seconds. + seconds. _Standard_: GNU extension @@ -7312,9 +7313,9 @@ _Description_: not present then the following are copied in depending on the type of ARRAY. - _Array _Boundary Value_ - Type_ - Numeric 0 of the type and kind of ARRAY. + _Array _Boundary Value_ + Type_ + Numeric 0 of the type and kind of ARRAY. Logical `.FALSE.'. Character(LEN)LEN blanks. @@ -7328,9 +7329,9 @@ _Syntax_: `RESULT = EOSHIFT(ARRAY, SHIFT [, BOUNDARY, DIM])' _Arguments_: - ARRAY May be any type, not scalar. + ARRAY May be any type, not scalar. SHIFT The type shall be `INTEGER'. - BOUNDARY Same type as ARRAY. + BOUNDARY Same type as ARRAY. DIM The type shall be `INTEGER'. _Return value_: @@ -7415,7 +7416,7 @@ _Example_: end program test_erf _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DERF(X)' `REAL(8) X' `REAL(8)' GNU extension  @@ -7441,7 +7442,7 @@ _Arguments_: _Return value_: The return value is of type `REAL' and of the same kind as X. It - lies in the range 0 \leq erfc (x) \leq 2 . + lies in the range 0 \leq erfc (x) \leq 2 . _Example_: program test_erfc @@ -7450,7 +7451,7 @@ _Example_: end program test_erfc _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `DERFC(X)' `REAL(8) X' `REAL(8)' GNU extension  @@ -7596,7 +7597,7 @@ _Arguments_: EXITSTAT (Optional) Shall be an `INTEGER' of the default kind. CMDSTAT (Optional) Shall be an `INTEGER' of the - default kind. + default kind. CMDMSG (Optional) Shall be an `CHARACTER' scalar of the default kind. @@ -7615,9 +7616,9 @@ _Example_: _Note_: Because this intrinsic is implemented in terms of the `system' function call, its behavior with respect to signaling is processor - dependent. In particular, on POSIX-compliant systems, the SIGINT + dependent. In particular, on POSIX-compliant systems, the SIGINT and SIGQUIT signals will be ignored, and the SIGCHLD will be - blocked. As such, if the parent process is terminated, the child + blocked. As such, if the parent process is terminated, the child process might not be terminated alongside. _See also_: @@ -7690,17 +7691,17 @@ _Example_: end program test_exp _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `EXP(X)' `REAL(4) X' `REAL(4)' Fortran 77 and - later + later `DEXP(X)' `REAL(8) X' `REAL(8)' Fortran 77 and - later + later `CEXP(X)' `COMPLEX(4) `COMPLEX(4)' Fortran 77 and - X' later + X' later `ZEXP(X)' `COMPLEX(8) `COMPLEX(8)' GNU extension - X' + X' `CDEXP(X)' `COMPLEX(8) `COMPLEX(8)' GNU extension - X' + X'  File: gfortran.info, Node: EXPONENT, Next: EXTENDS_TYPE_OF, Prev: EXP, Up: Intrinsic Procedures @@ -7755,13 +7756,13 @@ _Syntax_: `RESULT = EXTENDS_TYPE_OF(A, MOLD)' _Arguments_: - A Shall be an object of extensible declared type - or unlimited polymorphic. - MOLD Shall be an object of extensible declared type - or unlimited polymorphic. + A Shall be an object of extensible declared type + or unlimited polymorphic. + MOLD Shall be an object of extensible declared type + or unlimited polymorphic. _Return value_: - The return value is a scalar of type default logical. It is true + The return value is a scalar of type default logical. It is true if and only if the dynamic type of A is an extension type of the dynamic type of MOLD. @@ -7826,7 +7827,7 @@ File: gfortran.info, Node: FGET, Next: FGETC, Prev: FDATE, Up: Intrinsic Pro _Description_: Read a single character in stream mode from stdin by bypassing - normal formatted output. Stream I/O should not be mixed with + normal formatted output. Stream I/O should not be mixed with normal record-oriented (formatted or unformatted) I/O on the same unit; the results are unpredictable. @@ -7851,10 +7852,10 @@ _Syntax_: _Arguments_: C The type shall be `CHARACTER' and of default - kind. + kind. STATUS (Optional) status flag of type `INTEGER'. - Returns 0 on success, -1 on end-of-file, and a - system specific positive error code otherwise. + Returns 0 on success, -1 on end-of-file, and a + system specific positive error code otherwise. _Example_: PROGRAM test_fget @@ -7908,10 +7909,10 @@ _Syntax_: _Arguments_: UNIT The type shall be `INTEGER'. C The type shall be `CHARACTER' and of default - kind. + kind. STATUS (Optional) status flag of type `INTEGER'. - Returns 0 on success, -1 on end-of-file and a - system specific positive error code otherwise. + Returns 0 on success, -1 on end-of-file and a + system specific positive error code otherwise. _Example_: PROGRAM test_fgetc @@ -7977,7 +7978,7 @@ File: gfortran.info, Node: FLUSH, Next: FNUM, Prev: FLOOR, Up: Intrinsic Pro ================================= _Description_: - Flushes Fortran unit(s) currently open for output. Without the + Flushes Fortran unit(s) currently open for output. Without the optional argument, all units are flushed, otherwise just the unit specified. @@ -7999,10 +8000,10 @@ _Note_: The `FLUSH' intrinsic and the Fortran 2003 `FLUSH' statement have identical effect: they flush the runtime library's I/O buffer so - that the data becomes visible to other processes. This does not + that the data becomes visible to other processes. This does not guarantee that the data is committed to disk. - On POSIX systems, you can request that all data is transferred to + On POSIX systems, you can request that all data is transferred to the storage device by calling the `fsync' function, with the POSIX file descriptor of the I/O unit as argument (retrieved with GNU intrinsic `FNUM'). The following example shows how: @@ -8076,7 +8077,7 @@ File: gfortran.info, Node: FPUT, Next: FPUTC, Prev: FNUM, Up: Intrinsic Proc _Description_: Write a single character in stream mode to stdout by bypassing - normal formatted output. Stream I/O should not be mixed with + normal formatted output. Stream I/O should not be mixed with normal record-oriented (formatted or unformatted) I/O on the same unit; the results are unpredictable. @@ -8101,10 +8102,10 @@ _Syntax_: _Arguments_: C The type shall be `CHARACTER' and of default - kind. + kind. STATUS (Optional) status flag of type `INTEGER'. - Returns 0 on success, -1 on end-of-file and a - system specific positive error code otherwise. + Returns 0 on success, -1 on end-of-file and a + system specific positive error code otherwise. _Example_: PROGRAM test_fput @@ -8126,7 +8127,7 @@ File: gfortran.info, Node: FPUTC, Next: FRACTION, Prev: FPUT, Up: Intrinsic _Description_: Write a single character in stream mode by bypassing normal - formatted output. Stream I/O should not be mixed with normal + formatted output. Stream I/O should not be mixed with normal record-oriented (formatted or unformatted) I/O on the same unit; the results are unpredictable. @@ -8152,10 +8153,10 @@ _Syntax_: _Arguments_: UNIT The type shall be `INTEGER'. C The type shall be `CHARACTER' and of default - kind. + kind. STATUS (Optional) status flag of type `INTEGER'. - Returns 0 on success, -1 on end-of-file and a - system specific positive error code otherwise. + Returns 0 on success, -1 on end-of-file and a + system specific positive error code otherwise. _Example_: PROGRAM test_fputc @@ -8217,7 +8218,7 @@ _Description_: Frees memory previously allocated by `MALLOC'. The `FREE' intrinsic is an extension intended to be used with Cray pointers, and is provided in GNU Fortran to allow user to compile legacy - code. For new code using Fortran 95 pointers, the memory + code. For new code using Fortran 95 pointers, the memory de-allocation intrinsic is `DEALLOCATE'. _Standard_: @@ -8231,8 +8232,8 @@ _Syntax_: _Arguments_: PTR The type shall be `INTEGER'. It represents the - location of the memory that should be - de-allocated. + location of the memory that should be + de-allocated. _Return value_: None @@ -8250,16 +8251,16 @@ File: gfortran.info, Node: FSEEK, Next: FSTAT, Prev: FREE, Up: Intrinsic Pro ===================================================== _Description_: - Moves UNIT to the specified OFFSET. If WHENCE is set to 0, the + Moves UNIT to the specified OFFSET. If WHENCE is set to 0, the OFFSET is taken as an absolute value `SEEK_SET', if set to 1, OFFSET is taken to be relative to the current position `SEEK_CUR', and if set to 2 relative to the end of the file `SEEK_END'. On - error, STATUS is set to a nonzero value. If STATUS the seek fails + error, STATUS is set to a nonzero value. If STATUS the seek fails silently. This intrinsic routine is not fully backwards compatible with `g77'. In `g77', the `FSEEK' takes a statement label instead of a - STATUS variable. If FSEEK is used in old code, change + STATUS variable. If FSEEK is used in old code, change CALL FSEEK(UNIT, OFFSET, WHENCE, *label) to INTEGER :: status @@ -8268,7 +8269,7 @@ _Description_: Please note that GNU Fortran provides the Fortran 2003 Stream facility. Programmers should consider the use of new stream IO - feature in new code for future portability. See also *note Fortran + feature in new code for future portability. See also *note Fortran 2003 status::. _Standard_: @@ -8285,7 +8286,7 @@ _Arguments_: OFFSET Shall be a scalar of type `INTEGER'. WHENCE Shall be a scalar of type `INTEGER'. Its value shall be either 0, 1 or 2. - STATUS (Optional) shall be a scalar of type + STATUS (Optional) shall be a scalar of type `INTEGER(4)'. _Example_: @@ -8414,7 +8415,7 @@ _Syntax_: _Arguments_: X Shall be of type `REAL' and neither zero nor a - negative integer. + negative integer. _Return value_: The return value is of type `REAL' of the same kind as X. @@ -8426,7 +8427,7 @@ _Example_: end program test_gamma _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `GAMMA(X)' `REAL(4) X' `REAL(4)' GNU Extension `DGAMMA(X)' `REAL(8) X' `REAL(8)' GNU Extension @@ -8492,15 +8493,15 @@ _Syntax_: _Arguments_: POS Shall be of type `INTEGER' and not wider than - the default integer kind; POS \geq 0 + the default integer kind; POS \geq 0 VALUE Shall be of type `CHARACTER' and of default - kind. + kind. VALUE Shall be of type `CHARACTER'. _Return value_: After `GETARG' returns, the VALUE argument holds the POSth command - line argument. If VALUE can not hold the argument, it is truncated - to fit the length of VALUE. If there are less than POS arguments + line argument. If VALUE can not hold the argument, it is truncated + to fit the length of VALUE. If there are less than POS arguments specified at the command line, VALUE will be filled with blanks. If POS = 0, VALUE is set to the name of the program (on systems that support this feature). @@ -8543,16 +8544,16 @@ _Syntax_: _Arguments_: COMMAND (Optional) shall be of type `CHARACTER' and of - default kind. + default kind. LENGTH (Optional) Shall be of type `INTEGER' and of - default kind. + default kind. STATUS (Optional) Shall be of type `INTEGER' and of - default kind. + default kind. _Return value_: If COMMAND is present, stores the entire command line that was used - to invoke the program in COMMAND. If LENGTH is present, it is - assigned the length of the command line. If STATUS is present, it + to invoke the program in COMMAND. If LENGTH is present, it is + assigned the length of the command line. If STATUS is present, it is assigned 0 upon success of the command, -1 if COMMAND is too short to store the command line, or a positive value in case of an error. @@ -8588,23 +8589,23 @@ _Syntax_: _Arguments_: NUMBER Shall be a scalar of type `INTEGER' and of - default kind, NUMBER \geq 0 + default kind, NUMBER \geq 0 VALUE (Optional) Shall be a scalar of type `CHARACTER' and of default kind. LENGTH (Optional) Shall be a scalar of type `INTEGER' - and of default kind. + and of default kind. STATUS (Optional) Shall be a scalar of type `INTEGER' - and of default kind. + and of default kind. _Return value_: After `GET_COMMAND_ARGUMENT' returns, the VALUE argument holds the - NUMBER-th command line argument. If VALUE can not hold the - argument, it is truncated to fit the length of VALUE. If there are + NUMBER-th command line argument. If VALUE can not hold the + argument, it is truncated to fit the length of VALUE. If there are less than NUMBER arguments specified at the command line, VALUE will be filled with blanks. If NUMBER = 0, VALUE is set to the - name of the program (on systems that support this feature). The + name of the program (on systems that support this feature). The LENGTH argument contains the length of the NUMBER-th command line - argument. If the argument retrieval fails, STATUS is a positive + argument. If the argument retrieval fails, STATUS is a positive number; if VALUE contains a truncated command line argument, STATUS is -1; and otherwise the STATUS is zero. @@ -8650,10 +8651,10 @@ _Syntax_: _Arguments_: C The type shall be `CHARACTER' and of default - kind. + kind. STATUS (Optional) status flag. Returns 0 on success, a system specific and nonzero error code - otherwise. + otherwise. _Example_: PROGRAM test_getcwd @@ -8694,13 +8695,13 @@ _Syntax_: _Arguments_: NAME Shall be of type `CHARACTER' and of default - kind. + kind. VALUE Shall be of type `CHARACTER' and of default - kind. + kind. _Return value_: - Stores the value of NAME in VALUE. If VALUE is not large enough to - hold the data, it is truncated. If NAME is not set, VALUE will be + Stores the value of NAME in VALUE. If VALUE is not large enough to + hold the data, it is truncated. If NAME is not set, VALUE will be filled with blanks. _Example_: @@ -8739,20 +8740,20 @@ _Syntax_: _Arguments_: NAME Shall be a scalar of type `CHARACTER' and of - default kind. + default kind. VALUE (Optional) Shall be a scalar of type `CHARACTER' and of default kind. LENGTH (Optional) Shall be a scalar of type `INTEGER' - and of default kind. + and of default kind. STATUS (Optional) Shall be a scalar of type `INTEGER' - and of default kind. + and of default kind. TRIM_NAME (Optional) Shall be a scalar of type `LOGICAL' - and of default kind. + and of default kind. _Return value_: - Stores the value of NAME in VALUE. If VALUE is not large enough to - hold the data, it is truncated. If NAME is not set, VALUE will be - filled with blanks. Argument LENGTH contains the length needed for + Stores the value of NAME in VALUE. If VALUE is not large enough to + hold the data, it is truncated. If NAME is not set, VALUE will be + filled with blanks. Argument LENGTH contains the length needed for storing the environment variable NAME or zero if it is not present. STATUS is -1 if VALUE is present but too short for the environment variable; it is 1 if the environment variable does not @@ -8816,7 +8817,7 @@ _Syntax_: _Arguments_: C Shall be of type `CHARACTER' and of default - kind. + kind. _Return value_: Stores the current user name in LOGIN. (On systems where POSIX @@ -9032,8 +9033,8 @@ _Syntax_: _Arguments_: X The type shall be `REAL'. - Y The type and kind type parameter shall be the - same as X. + Y The type and kind type parameter shall be the + same as X. _Return value_: The return value has the same type and kind type parameter as X. @@ -9111,8 +9112,8 @@ _Syntax_: _Arguments_: ARRAY Shall be an array of type `INTEGER' DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of ARRAY. + with a value in the range from 1 to n, where n + equals the rank of ARRAY. MASK (Optional) shall be of type `LOGICAL' and either be a scalar or an array of the same shape as ARRAY. @@ -9121,7 +9122,7 @@ _Return value_: The result is of the same type as ARRAY. If DIM is absent, a scalar with the bitwise ALL of all elements in - ARRAY is returned. Otherwise, an array of rank n-1, where n equals + ARRAY is returned. Otherwise, an array of rank n-1, where n equals the rank of ARRAY, and a shape similar to that of ARRAY with dimension DIM dropped is returned. @@ -9203,8 +9204,8 @@ _Syntax_: _Arguments_: ARRAY Shall be an array of type `INTEGER' DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of ARRAY. + with a value in the range from 1 to n, where n + equals the rank of ARRAY. MASK (Optional) shall be of type `LOGICAL' and either be a scalar or an array of the same shape as ARRAY. @@ -9213,7 +9214,7 @@ _Return value_: The result is of the same type as ARRAY. If DIM is absent, a scalar with the bitwise OR of all elements in - ARRAY is returned. Otherwise, an array of rank n-1, where n equals + ARRAY is returned. Otherwise, an array of rank n-1, where n equals the rank of ARRAY, and a shape similar to that of ARRAY with dimension DIM dropped is returned. @@ -9404,15 +9405,15 @@ _Example_: end program test_ichar _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ICHAR(C)' `CHARACTER `INTEGER(4)' Fortran 77 and - C' later + C' later _Note_: No intrinsic exists to convert between a numeric value and a formatted character string representation - for instance, given the `CHARACTER' value `'154'', obtaining an `INTEGER' or `REAL' value - with the value 154, or vice versa. Instead, this functionality is + with the value 154, or vice versa. Instead, this functionality is provided by internal-file I/O, as in the following example: program read_val integer value @@ -9440,7 +9441,7 @@ File: gfortran.info, Node: IDATE, Next: IEOR, Prev: ICHAR, Up: Intrinsic Pro _Description_: `IDATE(VALUES)' Fills VALUES with the numerical values at the - current local time. The day (in the range 1-31), month (in the + current local time. The day (in the range 1-31), month (in the range 1-12), and year appear in elements 1, 2, and 3 of VALUES, respectively. The year has four significant digits. @@ -9455,7 +9456,7 @@ _Syntax_: _Arguments_: VALUES The type shall be `INTEGER, DIMENSION(3)' and - the kind shall be the default integer kind. + the kind shall be the default integer kind. _Return value_: Does not return anything. @@ -9550,13 +9551,13 @@ _Syntax_: `RESULT = IMAGE_INDEX(COARRAY, SUB)' _Arguments_: None. - COARRAY Coarray of any type. - SUB default integer rank-1 array of a size equal to - the corank of COARRAY. + COARRAY Coarray of any type. + SUB default integer rank-1 array of a size equal to + the corank of COARRAY. _Return value_: Scalar default integer with the value of the image index which - corresponds to the cosubscripts. For invalid cosubscripts the + corresponds to the cosubscripts. For invalid cosubscripts the result is zero. _Example_: @@ -9605,9 +9606,9 @@ _Return value_: absent, the return value is of default integer kind. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `INDEX(STRING,`CHARACTER' `INTEGER(4)' Fortran 77 and - SUBSTRING)' later + SUBSTRING)' later _See also_: *note SCAN::, *note VERIFY:: @@ -9641,16 +9642,16 @@ _Return value_: These functions return a `INTEGER' variable or array under the following rules: - (A) + (A) If A is of type `INTEGER', `INT(A) = A' - (B) + (B) If A is of type `REAL' and |A| < 1, `INT(A)' equals `0'. If |A| \geq 1, then `INT(A)' equals the largest integer that does not exceed the range of A and whose sign is the same as the sign of A. - (C) + (C) If A is of type `COMPLEX', rule B is applied to the real part of A. @@ -9663,13 +9664,13 @@ _Example_: end program _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `INT(A)' `REAL(4) A' `INTEGER' Fortran 77 and - later + later `IFIX(A)' `REAL(4) A' `INTEGER' Fortran 77 and - later + later `IDINT(A)' `REAL(8) A' `INTEGER' Fortran 77 and - later + later  @@ -9790,8 +9791,8 @@ _Syntax_: _Arguments_: ARRAY Shall be an array of type `INTEGER' DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of ARRAY. + with a value in the range from 1 to n, where n + equals the rank of ARRAY. MASK (Optional) shall be of type `LOGICAL' and either be a scalar or an array of the same shape as ARRAY. @@ -9800,7 +9801,7 @@ _Return value_: The result is of the same type as ARRAY. If DIM is absent, a scalar with the bitwise XOR of all elements in - ARRAY is returned. Otherwise, an array of rank n-1, where n equals + ARRAY is returned. Otherwise, an array of rank n-1, where n equals the rank of ARRAY, and a shape similar to that of ARRAY with dimension DIM dropped is returned. @@ -9827,7 +9828,7 @@ File: gfortran.info, Node: IRAND, Next: IS_IOSTAT_END, Prev: IPARITY, Up: In _Description_: `IRAND(FLAG)' returns a pseudo-random number from a uniform distribution between 0 and a system-dependent limit (which is in - most cases 2147483647). If FLAG is 0, the next number in the + most cases 2147483647). If FLAG is 0, the next number in the current sequence is returned; if FLAG is 1, the generator is restarted by `CALL SRAND(0)'; if FLAG has any other value, it is used as a new seed with `SRAND'. @@ -9870,7 +9871,7 @@ File: gfortran.info, Node: IS_IOSTAT_END, Next: IS_IOSTAT_EOR, Prev: IRAND, _Description_: `IS_IOSTAT_END' tests whether an variable has the value of the I/O - status "end of file". The function is equivalent to comparing the + status "end of file". The function is equivalent to comparing the variable with the `IOSTAT_END' parameter of the intrinsic module `ISO_FORTRAN_ENV'. @@ -10089,7 +10090,7 @@ File: gfortran.info, Node: ITIME, Next: KILL, Prev: ISNAN, Up: Intrinsic Pro _Description_: `IDATE(VALUES)' Fills VALUES with the numerical values at the - current local time. The hour (in the range 1-24), minute (in the + current local time. The hour (in the range 1-24), minute (in the range 1-60), and seconds (in the range 1-60) appear in elements 1, 2, and 3 of VALUES, respectively. @@ -10104,7 +10105,7 @@ _Syntax_: _Arguments_: VALUES The type shall be `INTEGER, DIMENSION(3)' and - the kind shall be the default integer kind. + the kind shall be the default integer kind. _Return value_: Does not return anything. @@ -10145,7 +10146,7 @@ _Arguments_: VALUE Shall be a scalar `INTEGER', with `INTENT(IN)' STATUS (Optional) status flag of type `INTEGER(4)' or `INTEGER(8)'. Returns 0 on success, or a - system-specific error code otherwise. + system-specific error code otherwise. _See also_: *note ABORT::, *note EXIT:: @@ -10206,7 +10207,7 @@ _Syntax_: `RESULT = LBOUND(ARRAY [, DIM [, KIND]])' _Arguments_: - ARRAY Shall be an array, of any type. + ARRAY Shall be an array, of any type. DIM (Optional) Shall be a scalar `INTEGER'. KIND (Optional) An `INTEGER' initialization expression indicating the kind parameter of @@ -10245,7 +10246,7 @@ _Syntax_: `RESULT = LCOBOUND(COARRAY [, DIM [, KIND]])' _Arguments_: - ARRAY Shall be an coarray, of any type. + ARRAY Shall be an coarray, of any type. DIM (Optional) Shall be a scalar `INTEGER'. KIND (Optional) An `INTEGER' initialization expression indicating the kind parameter of @@ -10328,9 +10329,9 @@ _Return value_: absent, the return value is of default integer kind. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `LEN(STRING)' `CHARACTER' `INTEGER' Fortran 77 and - later + later _See also_: *note LEN_TRIM::, *note ADJUSTL::, *note ADJUSTR:: @@ -10405,9 +10406,9 @@ _Return value_: otherwise, based on the ASCII ordering. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `LGE(STRING_A,`CHARACTER' `LOGICAL' Fortran 77 and - STRING_B)' later + STRING_B)' later _See also_: *note LGT::, *note LLE::, *note LLT:: @@ -10449,9 +10450,9 @@ _Return value_: otherwise, based on the ASCII ordering. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `LGT(STRING_A,`CHARACTER' `LOGICAL' Fortran 77 and - STRING_B)' later + STRING_B)' later _See also_: *note LGE::, *note LLE::, *note LLT:: @@ -10463,7 +10464,7 @@ File: gfortran.info, Node: LINK, Next: LLE, Prev: LGT, Up: Intrinsic Procedu ================================== _Description_: - Makes a (hard) link from file PATH1 to PATH2. A null character + Makes a (hard) link from file PATH1 to PATH2. A null character (`CHAR(0)') can be used to mark the end of the names in PATH1 and PATH2; otherwise, trailing blanks in the file names are ignored. If the STATUS argument is supplied, it contains 0 on success or a @@ -10528,9 +10529,9 @@ _Return value_: otherwise, based on the ASCII ordering. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `LLE(STRING_A,`CHARACTER' `LOGICAL' Fortran 77 and - STRING_B)' later + STRING_B)' later _See also_: *note LGE::, *note LGT::, *note LLT:: @@ -10572,9 +10573,9 @@ _Return value_: otherwise, based on the ASCII ordering. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `LLT(STRING_A,`CHARACTER' `LOGICAL' Fortran 77 and - STRING_B)' later + STRING_B)' later _See also_: *note LGE::, *note LGT::, *note LLE:: @@ -10628,7 +10629,7 @@ _Syntax_: `RESULT = LOC(X)' _Arguments_: - X Variable of any type. + X Variable of any type. _Return value_: The return value is of type `INTEGER', with a `KIND' corresponding @@ -10678,15 +10679,15 @@ _Example_: end program test_log _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ALOG(X)' `REAL(4) X' `REAL(4)' f95, gnu `DLOG(X)' `REAL(8) X' `REAL(8)' f95, gnu `CLOG(X)' `COMPLEX(4) `COMPLEX(4)' f95, gnu - X' + X' `ZLOG(X)' `COMPLEX(8) `COMPLEX(8)' f95, gnu - X' + X' `CDLOG(X)' `COMPLEX(8) `COMPLEX(8)' f95, gnu - X' + X'  File: gfortran.info, Node: LOG10, Next: LOG_GAMMA, Prev: LOG, Up: Intrinsic Procedures @@ -10720,11 +10721,11 @@ _Example_: end program test_log10 _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `ALOG10(X)' `REAL(4) X' `REAL(4)' Fortran 95 and - later + later `DLOG10(X)' `REAL(8) X' `REAL(8)' Fortran 95 and - later + later  File: gfortran.info, Node: LOG_GAMMA, Next: LOGICAL, Prev: LOG10, Up: Intrinsic Procedures @@ -10747,7 +10748,7 @@ _Syntax_: _Arguments_: X Shall be of type `REAL' and neither zero nor a - negative integer. + negative integer. _Return value_: The return value is of type `REAL' of the same kind as X. @@ -10759,7 +10760,7 @@ _Example_: end program test_log_gamma _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `LGAMMA(X)' `REAL(4) X' `REAL(4)' GNU Extension `ALGAMA(X)' `REAL(4) X' `REAL(4)' GNU Extension `DLGAMA(X)' `REAL(8) X' `REAL(8)' GNU Extension @@ -10897,7 +10898,7 @@ _Syntax_: _Arguments_: NAME The type shall be `CHARACTER' of the default - kind, a valid path within the file system. + kind, a valid path within the file system. VALUES The type shall be `INTEGER(4), DIMENSION(13)'. STATUS (Optional) status flag of type `INTEGER(4)'. Returns 0 on success and a system specific @@ -10972,7 +10973,7 @@ _Description_: `MALLOC(SIZE)' allocates SIZE bytes of dynamic memory and returns the address of the allocated memory. The `MALLOC' intrinsic is an extension intended to be used with Cray pointers, and is provided - in GNU Fortran to allow the user to compile legacy code. For new + in GNU Fortran to allow the user to compile legacy code. For new code using Fortran 95 pointers, the memory allocation intrinsic is `ALLOCATE'. @@ -11039,7 +11040,7 @@ _Syntax_: _Arguments_: I Shall be of type `INTEGER'. - KIND Shall be a scalar constant expression of type + KIND Shall be a scalar constant expression of type `INTEGER'. _Return value_: @@ -11071,7 +11072,7 @@ _Syntax_: _Arguments_: I Shall be of type `INTEGER'. - KIND Shall be a scalar constant expression of type + KIND Shall be a scalar constant expression of type `INTEGER'. _Return value_: @@ -11137,26 +11138,26 @@ _Syntax_: _Arguments_: A1 The type shall be `INTEGER' or `REAL'. - A2, A3, An expression of the same type and kind as A1. - ... (As a GNU extension, arguments of different - kinds are permitted.) + A2, A3, An expression of the same type and kind as A1. + ... (As a GNU extension, arguments of different + kinds are permitted.) _Return value_: The return value corresponds to the maximum value among the arguments, and has the same type and kind as the first argument. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `MAX0(A1)' `INTEGER(4) `INTEGER(4)' Fortran 77 and - A1' later + A1' later `AMAX0(A1)' `INTEGER(4) `REAL(MAX(X))'Fortran 77 and - A1' later + A1' later `MAX1(A1)' `REAL A1' `INT(MAX(X))' Fortran 77 and - later + later `AMAX1(A1)' `REAL(4) A1' `REAL(4)' Fortran 77 and - later + later `DMAX1(A1)' `REAL(8) A1' `REAL(8)' Fortran 77 and - later + later _See also_: *note MAXLOC:: *note MAXVAL::, *note MIN:: @@ -11233,7 +11234,7 @@ _Arguments_: rank of ARRAY, inclusive. It may not be an optional dummy argument. MASK Shall be an array of type `LOGICAL', and - conformable with ARRAY. + conformable with ARRAY. _Return value_: If DIM is absent, the result is a rank-one array with a length @@ -11279,7 +11280,7 @@ _Arguments_: rank of ARRAY, inclusive. It may not be an optional dummy argument. MASK Shall be an array of type `LOGICAL', and - conformable with ARRAY. + conformable with ARRAY. _Return value_: If DIM is absent, or if ARRAY has a rank of one, the result is a @@ -11385,7 +11386,7 @@ _Syntax_: `RESULT = MERGE(TSOURCE, FSOURCE, MASK)' _Arguments_: - TSOURCE May be of any type. + TSOURCE May be of any type. FSOURCE Shall be of the same type and type parameters as TSOURCE. MASK Shall be of type `LOGICAL'. @@ -11446,26 +11447,26 @@ _Syntax_: _Arguments_: A1 The type shall be `INTEGER' or `REAL'. - A2, A3, An expression of the same type and kind as A1. - ... (As a GNU extension, arguments of different - kinds are permitted.) + A2, A3, An expression of the same type and kind as A1. + ... (As a GNU extension, arguments of different + kinds are permitted.) _Return value_: The return value corresponds to the maximum value among the arguments, and has the same type and kind as the first argument. _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `MIN0(A1)' `INTEGER(4) `INTEGER(4)' Fortran 77 and - A1' later + A1' later `AMIN0(A1)' `INTEGER(4) `REAL(4)' Fortran 77 and - A1' later + A1' later `MIN1(A1)' `REAL A1' `INTEGER(4)' Fortran 77 and - later + later `AMIN1(A1)' `REAL(4) A1' `REAL(4)' Fortran 77 and - later + later `DMIN1(A1)' `REAL(8) A1' `REAL(8)' Fortran 77 and - later + later _See also_: *note MAX::, *note MINLOC::, *note MINVAL:: @@ -11535,7 +11536,7 @@ _Arguments_: rank of ARRAY, inclusive. It may not be an optional dummy argument. MASK Shall be an array of type `LOGICAL', and - conformable with ARRAY. + conformable with ARRAY. _Return value_: If DIM is absent, the result is a rank-one array with a length @@ -11582,7 +11583,7 @@ _Arguments_: rank of ARRAY, inclusive. It may not be an optional dummy argument. MASK Shall be an array of type `LOGICAL', and - conformable with ARRAY. + conformable with ARRAY. _Return value_: If DIM is absent, or if ARRAY has a rank of one, the result is a @@ -11643,13 +11644,13 @@ _Example_: end program test_mod _Specific names_: - Name Arguments Return type Standard + Name Arguments Return type Standard `MOD(A,P)' `INTEGER `INTEGER' Fortran 95 and - A,P' later + A,P' later `AMOD(A,P)' `REAL(4) `REAL(4)' Fortran 95 and - A,P' later + A,P' later `DMOD(A,P)' `REAL(8) `REAL(8)' Fortran 95 and - A,P' later + A,P' later _See also_: *note MODULO:: @@ -11675,8 +11676,8 @@ _Syntax_: _Arguments_: A Shall be a scalar of type `INTEGER' or `REAL'. - P Shall be a scalar of the same type and kind as - A. It shall not be zero. + P Shall be a scalar of the same type and kind as + A. It shall not be zero. _Return value_: The type and kind of the result are those of the arguments. @@ -11726,9 +11727,9 @@ _Syntax_: _Arguments_: FROM `ALLOCATABLE', `INTENT(INOUT)', may be of any - type and kind. + type and kind. TO `ALLOCATABLE', `INTENT(OUT)', shall be of the - same type, kind and rank as FROM. + same type, kind and rank as FROM. _Return value_: None @@ -11834,7 +11835,7 @@ _Syntax_: `RESULT = NEW_LINE(C)' _Arguments_: - C The argument shall be a scalar or array of the + C The argument shall be a scalar or array of the type `CHARACTER'. _Return value_: @@ -11886,11 +11887,11 @@ _Example_: end program test_nint _Specific names_: - Name Argument Return Type Standard + Name Argument Return Type Standard `NINT(A)' `REAL(4) A' `INTEGER' Fortran 95 and - later + later `IDNINT(A)' `REAL(8) A' `INTEGER' Fortran 95 and - later + later _See also_: *note CEILING::, *note FLOOR:: @@ -11918,8 +11919,8 @@ _Syntax_: _Arguments_: ARRAY Shall be an array of type `REAL' DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of ARRAY. + with a value in the range from 1 to n, where n + equals the rank of ARRAY. _Return value_: The result is of the same type as ARRAY. @@ -11976,7 +11977,7 @@ _Description_: If MOLD is present, a disassociated pointer of the same type is returned, otherwise the type is determined by context. - In Fortran 95, MOLD is optional. Please note that Fortran 2003 + In Fortran 95, MOLD is optional. Please note that Fortran 2003 includes cases where it is required. _Standard_: @@ -12064,7 +12065,7 @@ _Syntax_: _Arguments_: I The type shall be either a scalar `INTEGER' type or a scalar `LOGICAL' type. - J The type shall be the same as the type of J. + J The type shall be the same as the type of J. _Return value_: The return type is either a scalar `INTEGER' or a scalar @@ -12108,9 +12109,9 @@ _Syntax_: `RESULT = PACK(ARRAY, MASK[,VECTOR]' _Arguments_: - ARRAY Shall be an array of any type. + ARRAY Shall be an array of any type. MASK Shall be an array of type `LOGICAL' and of the - same size as ARRAY. Alternatively, it may be a + same size as ARRAY. Alternatively, it may be a `LOGICAL' scalar. VECTOR (Optional) shall be an array of the same type as ARRAY and of rank one. If present, the @@ -12166,8 +12167,8 @@ _Syntax_: _Arguments_: LOGICAL Shall be an array of type `LOGICAL' DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of MASK. + with a value in the range from 1 to n, where n + equals the rank of MASK. _Return value_: The result is of the same type as MASK. @@ -12386,8 +12387,8 @@ _Arguments_: ARRAY Shall be an array of type `INTEGER', `REAL' or `COMPLEX'. DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of ARRAY. + with a value in the range from 1 to n, where n + equals the rank of ARRAY. MASK (Optional) shall be of type `LOGICAL' and either be a scalar or an array of the same shape as ARRAY. @@ -12396,7 +12397,7 @@ _Return value_: The result is of the same type as ARRAY. If DIM is absent, a scalar with the product of all elements in - ARRAY is returned. Otherwise, an array of rank n-1, where n equals + ARRAY is returned. Otherwise, an array of rank n-1, where n equals the rank of ARRAY, and a shape similar to that of ARRAY with dimension DIM dropped is returned. @@ -12473,7 +12474,7 @@ File: gfortran.info, Node: RAND, Next: RANDOM_NUMBER, Prev: RAN, Up: Intrins _Description_: `RAND(FLAG)' returns a pseudo-random number from a uniform - distribution between 0 and 1. If FLAG is 0, the next number in the + distribution between 0 and 1. If FLAG is 0, the next number in the current sequence is returned; if FLAG is 1, the generator is restarted by `CALL SRAND(0)'; if FLAG has any other value, it is used as a new seed with `SRAND'. @@ -12519,7 +12520,7 @@ File: gfortran.info, Node: RANDOM_NUMBER, Next: RANDOM_SEED, Prev: RAND, Up: _Description_: Returns a single pseudorandom number or an array of pseudorandom - numbers from the uniform distribution over the range 0 \leq x < 1. + numbers from the uniform distribution over the range 0 \leq x < 1. The runtime-library implements George Marsaglia's KISS (Keep It Simple Stupid) random number generator (RNG). This RNG combines: @@ -12536,7 +12537,7 @@ _Description_: directives, i.e., its state will be consistent while called from multiple threads. However, the KISS generator does not create random numbers in parallel from multiple sources, but in sequence - from a single source. If an OpenMP-enabled application heavily + from a single source. If an OpenMP-enabled application heavily relies on random numbers, one should consider employing a dedicated parallel random number generator instead. @@ -12573,9 +12574,9 @@ _Description_: used by `RANDOM_NUMBER'. If `RANDOM_SEED' is called without arguments, it is initialized to - a default state. The example below shows how to initialize the + a default state. The example below shows how to initialize the random seed with a varying seed in order to ensure a different - random number sequence for each invocation of the program. Note + random number sequence for each invocation of the program. Note that setting any of the seed values to zero should be avoided as it can result in poor quality random numbers being generated. @@ -12593,23 +12594,24 @@ _Arguments_: default `INTEGER', with `INTENT(OUT)'. It specifies the minimum size of the arrays used with the PUT and GET arguments. - PUT (Optional) Shall be an array of type default + PUT (Optional) Shall be an array of type default `INTEGER' and rank one. It is `INTENT(IN)' and - the size of the array must be larger than or - equal to the number returned by the SIZE - argument. - GET (Optional) Shall be an array of type default + the size of the array must be larger than or + equal to the number returned by the SIZE + argument. + GET (Optional) Shall be an array of type default `INTEGER' and rank one. It is `INTENT(OUT)' and the size of the array must be larger than or equal to the number returned by the SIZE - argument. + argument. _Example_: subroutine init_random_seed() + use iso_fortran_env, only: int64 implicit none integer, allocatable :: seed(:) - integer :: i, n, un, istat, dt(8), pid, t(2), s - integer(8) :: count, tms + integer :: i, n, un, istat, dt(8), pid + integer(int64) :: t call random_seed(size = n) allocate(seed(n)) @@ -12623,34 +12625,37 @@ _Example_: ! Fallback to XOR:ing the current time and pid. The PID is ! useful in case one launches multiple instances of the same ! program in parallel. - call system_clock(count) - if (count /= 0) then - t = transfer(count, t) - else + call system_clock(t) + if (t == 0) then call date_and_time(values=dt) - tms = (dt(1) - 1970) * 365_8 * 24 * 60 * 60 * 1000 & - + dt(2) * 31_8 * 24 * 60 * 60 * 1000 & - + dt(3) * 24 * 60 * 60 * 60 * 1000 & + t = (dt(1) - 1970) * 365_int64 * 24 * 60 * 60 * 1000 & + + dt(2) * 31_int64 * 24 * 60 * 60 * 1000 & + + dt(3) * 24_int64 * 60 * 60 * 1000 & + dt(5) * 60 * 60 * 1000 & + dt(6) * 60 * 1000 + dt(7) * 1000 & + dt(8) - t = transfer(tms, t) end if - s = ieor(t(1), t(2)) - pid = getpid() + 1099279 ! Add a prime - s = ieor(s, pid) - if (n >= 3) then - seed(1) = t(1) + 36269 - seed(2) = t(2) + 72551 - seed(3) = pid - if (n > 3) then - seed(4:) = s + 37 * (/ (i, i = 0, n - 4) /) + pid = getpid() + t = ieor(t, int(pid, kind(t))) + do i = 1, n + seed(i) = lcg(t) + end do end if + call random_seed(put=seed) + contains + ! This simple PRNG might not be good enough for real work, but is + ! sufficient for seeding a better PRNG. + function lcg(s) + integer :: lcg + integer(int64) :: s + if (s == 0) then + s = 104729 else - seed = s + 37 * (/ (i, i = 0, n - 1 ) /) + s = mod(s, 4294967296_int64) end if - end if - call random_seed(put=seed) + s = mod(s * 279470273_int64, 4294967291_int64) + lcg = int(mod(s, int(huge(0), int64)), kind(0)) + end function lcg end subroutine init_random_seed _See also_: @@ -12708,11 +12713,11 @@ _Syntax_: `RESULT = RANGE(A)' _Arguments_: - A can be of any type + A can be of any type _Return value_: The return value is of type `INTEGER' and of the default integer - kind. For arrays, their rank is returned; for scalars zero is + kind. For arrays, their rank is returned; for scalars zero is returned. _Example_: @@ -12755,15 +12760,15 @@ _Return value_: These functions return a `REAL' variable or array under the following rules: - (A) + (A) `REAL(A)' is converted to a default real type if A is an integer or real variable. - (B) + (B) `REAL(A)' is converted to a real type with the kind type parameter of A if A is a complex variable. - (C) + (C) `REAL(A, KIND)' is converted to a real type with kind type parameter KIND if A is a complex, integer, or real variable. @@ -12774,12 +12779,12 @@ _Example_: end program test_real _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `FLOAT(A)' `INTEGER(4)' `REAL(4)' Fortran 77 and - later + later `DFLOAT(A)' `INTEGER(4)' `REAL(8)' GNU extension `SNGL(A)' `INTEGER(8)' `REAL(4)' Fortran 77 and - later + later _See also_: *note DBLE:: @@ -12792,7 +12797,7 @@ File: gfortran.info, Node: RENAME, Next: REPEAT, Prev: REAL, Up: Intrinsic P =============================== _Description_: - Renames a file from file PATH1 to PATH2. A null character + Renames a file from file PATH1 to PATH2. A null character (`CHAR(0)') can be used to mark the end of the names in PATH1 and PATH2; otherwise, trailing blanks in the file names are ignored. If the STATUS argument is supplied, it contains 0 on success or a @@ -12858,7 +12863,7 @@ File: gfortran.info, Node: RESHAPE, Next: RRSPACING, Prev: REPEAT, Up: Intri =============================================== _Description_: - Reshapes SOURCE to correspond to SHAPE. If necessary, the new + Reshapes SOURCE to correspond to SHAPE. If necessary, the new array may be padded with elements from PAD or permuted as defined by ORDER. @@ -12872,13 +12877,13 @@ _Syntax_: `RESULT = RESHAPE(SOURCE, SHAPE[, PAD, ORDER])' _Arguments_: - SOURCE Shall be an array of any type. + SOURCE Shall be an array of any type. SHAPE Shall be of type `INTEGER' and an array of rank one. Its values must be positive or zero. PAD (Optional) shall be an array of the same type as SOURCE. ORDER (Optional) shall be of type `INTEGER' and an - array of the same shape as SHAPE. Its values + array of the same shape as SHAPE. Its values shall be a permutation of the numbers from 1 to n, where n is the size of SHAPE. If ORDER is absent, the natural ordering shall be @@ -12937,7 +12942,7 @@ _Description_: `RSHIFT' returns a value corresponding to I with all of the bits shifted right by SHIFT places. If the absolute value of SHIFT is greater than `BIT_SIZE(I)', the value is undefined. Bits shifted - out from the right end are lost. The fill is arithmetic: the bits + out from the right end are lost. The fill is arithmetic: the bits shifted in from the left end are equal to the leftmost bit, which in two's complement representation is the sign bit. @@ -12984,13 +12989,13 @@ _Syntax_: `RESULT = SAME_TYPE_AS(A, B)' _Arguments_: - A Shall be an object of extensible declared type - or unlimited polymorphic. - B Shall be an object of extensible declared type - or unlimited polymorphic. + A Shall be an object of extensible declared type + or unlimited polymorphic. + B Shall be an object of extensible declared type + or unlimited polymorphic. _Return value_: - The return value is a scalar of type default logical. It is true + The return value is a scalar of type default logical. It is true if and only if the dynamic type of A is the same as the dynamic type of B. @@ -13085,8 +13090,8 @@ File: gfortran.info, Node: SECNDS, Next: SECOND, Prev: SCAN, Up: Intrinsic P _Description_: `SECNDS(X)' gets the time in seconds from the real-time system - clock. X is a reference time, also in seconds. If this is zero, - the time in seconds from midnight is returned. This function is + clock. X is a reference time, also in seconds. If this is zero, + the time in seconds from midnight is returned. This function is non-standard and its use is discouraged. _Standard_: @@ -13162,7 +13167,7 @@ File: gfortran.info, Node: SELECTED_CHAR_KIND, Next: SELECTED_INT_KIND, Prev: _Description_: `SELECTED_CHAR_KIND(NAME)' returns the kind value for the character set named NAME, if a character set with such a name is supported, - or -1 otherwise. Currently, supported character sets include + or -1 otherwise. Currently, supported character sets include "ASCII" and "DEFAULT", which are equivalent, and "ISO_10646" (Universal Character Set, UCS-4) which is commonly known as Unicode. @@ -13177,8 +13182,8 @@ _Syntax_: `RESULT = SELECTED_CHAR_KIND(NAME)' _Arguments_: - NAME Shall be a scalar and of the default character - type. + NAME Shall be a scalar and of the default character + type. _Example_: program character_kind @@ -13210,7 +13215,7 @@ File: gfortran.info, Node: SELECTED_INT_KIND, Next: SELECTED_REAL_KIND, Prev: _Description_: `SELECTED_INT_KIND(R)' return the kind value of the smallest integer type that can represent all values ranging from -10^R - (exclusive) to 10^R (exclusive). If there is no integer kind that + (exclusive) to 10^R (exclusive). If there is no integer kind that accommodates this range, `SELECTED_INT_KIND' returns -1. _Standard_: @@ -13260,11 +13265,11 @@ _Syntax_: `RESULT = SELECTED_REAL_KIND([P, R, RADIX])' _Arguments_: - P (Optional) shall be a scalar and of type + P (Optional) shall be a scalar and of type `INTEGER'. - R (Optional) shall be a scalar and of type + R (Optional) shall be a scalar and of type `INTEGER'. - RADIX (Optional) shall be a scalar and of type + RADIX (Optional) shall be a scalar and of type `INTEGER'. Before Fortran 2008, at least one of the arguments R or P shall be present; since Fortran 2008, they are assumed to be zero if absent. @@ -13274,15 +13279,15 @@ _Return value_: of a real data type with decimal precision of at least `P' digits, a decimal exponent range of at least `R', and with the requested `RADIX'. If the `RADIX' parameter is absent, real kinds with any - radix can be returned. If more than one real data type meet the + radix can be returned. If more than one real data type meet the criteria, the kind of the data type with the smallest decimal - precision is returned. If no real data type matches the criteria, + precision is returned. If no real data type matches the criteria, the result is - -1 if the processor does not support a real data type with a + -1 if the processor does not support a real data type with a precision greater than or equal to `P', but the `R' and `RADIX' requirements can be fulfilled - -2 if the processor does not support a real type with an exponent + -2 if the processor does not support a real type with an exponent range greater than or equal to `R', but `P' and `RADIX' are fulfillable @@ -13366,18 +13371,18 @@ _Syntax_: `RESULT = SHAPE(SOURCE [, KIND])' _Arguments_: - SOURCE Shall be an array or scalar of any type. If - SOURCE is a pointer it must be associated and - allocatable arrays must be allocated. + SOURCE Shall be an array or scalar of any type. If + SOURCE is a pointer it must be associated and + allocatable arrays must be allocated. KIND (Optional) An `INTEGER' initialization expression indicating the kind parameter of the result. _Return value_: An `INTEGER' array of rank one with as many elements as SOURCE has - dimensions. The elements of the resulting array correspond to the - extend of SOURCE along the respective dimensions. If SOURCE is a - scalar, the result is the rank one array of size zero. If KIND is + dimensions. The elements of the resulting array correspond to the + extend of SOURCE along the respective dimensions. If SOURCE is a + scalar, the result is the rank one array of size zero. If KIND is absent, the return value has the default integer kind otherwise the specified kind. @@ -13401,7 +13406,7 @@ _Description_: `SHIFTA' returns a value corresponding to I with all of the bits shifted right by SHIFT places. If the absolute value of SHIFT is greater than `BIT_SIZE(I)', the value is undefined. Bits shifted - out from the right end are lost. The fill is arithmetic: the bits + out from the right end are lost. The fill is arithmetic: the bits shifted in from the left end are equal to the leftmost bit, which in two's complement representation is the sign bit. @@ -13508,7 +13513,7 @@ _Syntax_: _Arguments_: A Shall be of type `INTEGER' or `REAL' - B Shall be of the same type and kind as A + B Shall be of the same type and kind as A _Return value_: The kind of the return value is that of A and B. If B\ge 0 then @@ -13526,13 +13531,13 @@ _Example_: end program test_sign _Specific names_: - Name Arguments Return type Standard + Name Arguments Return type Standard `SIGN(A,B)' `REAL(4) A, `REAL(4)' f77, gnu - B' + B' `ISIGN(A,B)' `INTEGER(4) `INTEGER(4)' f77, gnu - A, B' + A, B' `DSIGN(A,B)' `REAL(8) A, `REAL(8)' f77, gnu - B' + B'  File: gfortran.info, Node: SIGNAL, Next: SIN, Prev: SIGN, Up: Intrinsic Procedures @@ -13613,15 +13618,15 @@ _Example_: end program test_sin _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `SIN(X)' `REAL(4) X' `REAL(4)' f77, gnu `DSIN(X)' `REAL(8) X' `REAL(8)' f95, gnu `CSIN(X)' `COMPLEX(4) `COMPLEX(4)' f95, gnu - X' + X' `ZSIN(X)' `COMPLEX(8) `COMPLEX(8)' f95, gnu - X' + X' `CDSIN(X)' `COMPLEX(8) `COMPLEX(8)' f95, gnu - X' + X' _See also_: *note ASIN:: @@ -13657,11 +13662,11 @@ _Example_: end program test_sinh _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `SINH(X)' `REAL(4) X' `REAL(4)' Fortran 95 and - later + later `DSINH(X)' `REAL(8) X' `REAL(8)' Fortran 95 and - later + later _See also_: *note ASINH:: @@ -13686,9 +13691,9 @@ _Syntax_: `RESULT = SIZE(ARRAY[, DIM [, KIND]])' _Arguments_: - ARRAY Shall be an array of any type. If ARRAY is a - pointer it must be associated and allocatable - arrays must be allocated. + ARRAY Shall be an array of any type. If ARRAY is a + pointer it must be associated and allocatable + arrays must be allocated. DIM (Optional) shall be a scalar of type `INTEGER' and its value shall be in the range from 1 to n, where n equals the rank of ARRAY. @@ -13728,19 +13733,19 @@ _Syntax_: `N = SIZEOF(X)' _Arguments_: - X The argument shall be of any type, rank or - shape. + X The argument shall be of any type, rank or + shape. _Return value_: The return value is of type integer and of the system-dependent - kind C_SIZE_T (from the ISO_C_BINDING module). Its value is the + kind C_SIZE_T (from the ISO_C_BINDING module). Its value is the number of bytes occupied by the argument. If the argument has the `POINTER' attribute, the number of bytes of the storage area pointed to is returned. If the argument is of a derived type with `POINTER' or `ALLOCATABLE' components, the return value does not account for the sizes of the data pointed to by these components. If the argument is polymorphic, the size according to the declared - type is returned. The argument may not be a procedure or procedure + type is returned. The argument may not be a procedure or procedure pointer. _Example_: @@ -13893,17 +13898,17 @@ _Example_: end program test_sqrt _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `SQRT(X)' `REAL(4) X' `REAL(4)' Fortran 95 and - later + later `DSQRT(X)' `REAL(8) X' `REAL(8)' Fortran 95 and - later + later `CSQRT(X)' `COMPLEX(4) `COMPLEX(4)' Fortran 95 and - X' later + X' later `ZSQRT(X)' `COMPLEX(8) `COMPLEX(8)' GNU extension - X' + X' `CDSQRT(X)' `COMPLEX(8) `COMPLEX(8)' GNU extension - X' + X'  File: gfortran.info, Node: SRAND, Next: STAT, Prev: SQRT, Up: Intrinsic Procedures @@ -13937,7 +13942,7 @@ _Example_: _Notes_: The Fortran 2003 standard specifies the intrinsic `RANDOM_SEED' to initialize the pseudo-random numbers generator and `RANDOM_NUMBER' - to generate pseudo-random numbers. Please note that in GNU + to generate pseudo-random numbers. Please note that in GNU Fortran, these two sets of intrinsics (`RAND', `IRAND' and `SRAND' on the one hand, `RANDOM_NUMBER' and `RANDOM_SEED' on the other hand) access two independent pseudo-random number generators. @@ -13953,7 +13958,7 @@ File: gfortran.info, Node: STAT, Next: STORAGE_SIZE, Prev: SRAND, Up: Intrin =============================== _Description_: - This function returns information about a file. No permissions are + This function returns information about a file. No permissions are required on the file itself, but execute (search) permission is required on all of the directories in path that lead to the file. @@ -13992,7 +13997,7 @@ _Syntax_: _Arguments_: NAME The type shall be `CHARACTER', of the default - kind and a valid path within the file system. + kind and a valid path within the file system. VALUES The type shall be `INTEGER(4), DIMENSION(13)'. STATUS (Optional) status flag of type `INTEGER(4)'. Returns 0 on success and a system specific @@ -14044,9 +14049,9 @@ _Syntax_: `RESULT = STORAGE_SIZE(A [, KIND])' _Arguments_: - A Shall be a scalar or array of any type. - KIND (Optional) shall be a scalar integer constant - expression. + A Shall be a scalar or array of any type. + KIND (Optional) shall be a scalar integer constant + expression. _Return Value_: The result is a scalar integer with the kind type parameter @@ -14081,8 +14086,8 @@ _Arguments_: ARRAY Shall be an array of type `INTEGER', `REAL' or `COMPLEX'. DIM (Optional) shall be a scalar of type `INTEGER' - with a value in the range from 1 to n, where n - equals the rank of ARRAY. + with a value in the range from 1 to n, where n + equals the rank of ARRAY. MASK (Optional) shall be of type `LOGICAL' and either be a scalar or an array of the same shape as ARRAY. @@ -14112,7 +14117,7 @@ File: gfortran.info, Node: SYMLNK, Next: SYSTEM, Prev: SUM, Up: Intrinsic Pr ======================================== _Description_: - Makes a symbolic link from file PATH1 to PATH2. A null character + Makes a symbolic link from file PATH1 to PATH2. A null character (`CHAR(0)') can be used to mark the end of the names in PATH1 and PATH2; otherwise, trailing blanks in the file names are ignored. If the STATUS argument is supplied, it contains 0 on success or a @@ -14195,9 +14200,9 @@ _Description_: resolution realtime clock. COUNT_RATE is system dependent and can vary depending on the kind - of the arguments. For KIND=4 arguments, COUNT usually represents + of the arguments. For KIND=4 arguments, COUNT usually represents milliseconds, while for KIND=8 arguments, COUNT typically - represents micro- or nanoseconds. COUNT_MAX usually equals + represents micro- or nanoseconds. COUNT_MAX usually equals `HUGE(COUNT_MAX)'. If there is no clock, COUNT is set to `-HUGE(COUNT)', and @@ -14267,11 +14272,11 @@ _Example_: end program test_tan _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `TAN(X)' `REAL(4) X' `REAL(4)' Fortran 95 and - later + later `DTAN(X)' `REAL(8) X' `REAL(8)' Fortran 95 and - later + later _See also_: *note ATAN:: @@ -14298,9 +14303,9 @@ _Arguments_: X The type shall be `REAL' or `COMPLEX'. _Return value_: - The return value has same type and kind as X. If X is complex, the + The return value has same type and kind as X. If X is complex, the imaginary part of the result is in radians. If X is `REAL', the - return value lies in the range - 1 \leq tanh(x) \leq 1 . + return value lies in the range - 1 \leq tanh(x) \leq 1 . _Example_: program test_tanh @@ -14309,11 +14314,11 @@ _Example_: end program test_tanh _Specific names_: - Name Argument Return type Standard + Name Argument Return type Standard `TANH(X)' `REAL(4) X' `REAL(4)' Fortran 95 and - later + later `DTANH(X)' `REAL(8) X' `REAL(8)' Fortran 95 and - later + later _See also_: *note ATANH:: @@ -14340,16 +14345,16 @@ _Syntax_: _Arguments_: COARRAY Coarray of any type (optional; if DIM present, required). - DIM default integer scalar (optional). If present, - DIM shall be between one and the corank of - COARRAY. + DIM default integer scalar (optional). If present, + DIM shall be between one and the corank of + COARRAY. _Return value_: - Default integer. If COARRAY is not present, it is scalar and its - value is the index of the invoking image. Otherwise, if DIM is not + Default integer. If COARRAY is not present, it is scalar and its + value is the index of the invoking image. Otherwise, if DIM is not present, a rank-1 array with corank elements is returned, containing the cosubscripts for COARRAY specifying the invoking - image. If DIM is present, a scalar is returned, with the value of + image. If DIM is present, a scalar is returned, with the value of the DIM element of `THIS_IMAGE(COARRAY)'. _Example_: @@ -14419,7 +14424,7 @@ _Description_: values over that returned by `time(3)'. On a system with a 32-bit `time(3)', `TIME8' will return a 32-bit value, even though it is converted to a 64-bit `INTEGER(8)' value. That means overflows of - the 32-bit value can still occur. Therefore, the values returned + the 32-bit value can still occur. Therefore, the values returned by this intrinsic might be or become negative or numerically less than previous values during a single run of the compiled program. @@ -14525,8 +14530,8 @@ _Syntax_: `RESULT = TRANSFER(SOURCE, MOLD[, SIZE])' _Arguments_: - SOURCE Shall be a scalar or an array of any type. - MOLD Shall be a scalar or an array of any type. + SOURCE Shall be a scalar or an array of any type. + MOLD Shall be a scalar or an array of any type. SIZE (Optional) shall be a scalar of type `INTEGER'. _Return value_: @@ -14535,7 +14540,7 @@ _Return value_: one-dimensional array of length SIZE. If SIZE is absent but MOLD is an array (of any size or shape), the result is a one- dimensional array of the minimum length needed to contain the - entirety of the bitwise representation of SOURCE. If SIZE is + entirety of the bitwise representation of SOURCE. If SIZE is absent and MOLD is a scalar, the result is a scalar. If the bitwise representation of the result is longer than that of @@ -14562,7 +14567,7 @@ File: gfortran.info, Node: TRANSPOSE, Next: TRIM, Prev: TRANSFER, Up: Intrin =================================================== _Description_: - Transpose an array of rank two. Element (i, j) of the result has + Transpose an array of rank two. Element (i, j) of the result has the value `MATRIX(j, i)', for all i, j. _Standard_: @@ -14623,7 +14628,7 @@ File: gfortran.info, Node: TTYNAM, Next: UBOUND, Prev: TRIM, Up: Intrinsic P ==================================================== _Description_: - Get the name of a terminal device. For more information, see + Get the name of a terminal device. For more information, see `ttyname(3)'. This intrinsic is provided in both subroutine and function forms; @@ -14674,7 +14679,7 @@ _Syntax_: `RESULT = UBOUND(ARRAY [, DIM [, KIND]])' _Arguments_: - ARRAY Shall be an array, of any type. + ARRAY Shall be an array, of any type. DIM (Optional) Shall be a scalar `INTEGER'. KIND (Optional) An `INTEGER' initialization expression indicating the kind parameter of @@ -14714,7 +14719,7 @@ _Syntax_: `RESULT = UCOBOUND(COARRAY [, DIM [, KIND]])' _Arguments_: - ARRAY Shall be an coarray, of any type. + ARRAY Shall be an coarray, of any type. DIM (Optional) Shall be a scalar `INTEGER'. KIND (Optional) An `INTEGER' initialization expression indicating the kind parameter of @@ -14737,8 +14742,8 @@ File: gfortran.info, Node: UMASK, Next: UNLINK, Prev: UCOBOUND, Up: Intrinsi =========================================== _Description_: - Sets the file creation mask to MASK. If called as a function, it - returns the old value. If called as a subroutine and argument OLD + Sets the file creation mask to MASK. If called as a function, it + returns the old value. If called as a subroutine and argument OLD if it is supplied, it is set to the old value. See `umask(2)'. _Standard_: @@ -14808,7 +14813,7 @@ _Syntax_: `RESULT = UNPACK(VECTOR, MASK, FIELD)' _Arguments_: - VECTOR Shall be an array of any type and rank one. It + VECTOR Shall be an array of any type and rank one. It shall have at least as many elements as MASK has `TRUE' values. MASK Shall be an array of type `LOGICAL'. @@ -14906,7 +14911,7 @@ _Syntax_: _Arguments_: I The type shall be either a scalar `INTEGER' type or a scalar `LOGICAL' type. - J The type shall be the same as the type of I. + J The type shall be the same as the type of I. _Return value_: The return type is either a scalar `INTEGER' or a scalar @@ -14953,12 +14958,12 @@ default-integer named constants: `ATOMIC_INT_KIND': Default-kind integer constant to be used as kind parameter when - defining integer variables used in atomic operations. (Fortran + defining integer variables used in atomic operations. (Fortran 2008 or later.) `ATOMIC_LOGICAL_KIND': Default-kind integer constant to be used as kind parameter when - defining logical variables used in atomic operations. (Fortran + defining logical variables used in atomic operations. (Fortran 2008 or later.) `CHARACTER_KINDS': @@ -15002,7 +15007,7 @@ default-integer named constants: `IOSTAT_INQUIRE_INTERNAL_UNIT': Scalar default-integer constant, used by `INQUIRE' for the `IOSTAT=' specifier to denote an that a unit number identifies an - internal unit. (Fortran 2008 or later.) + internal unit. (Fortran 2008 or later.) `NUMERIC_STORAGE_SIZE': The size in bits of the numeric storage unit. @@ -15018,8 +15023,8 @@ default-integer named constants: `REAL32', `REAL64', `REAL128': Kind type parameters to specify a REAL type with a storage size of - 32, 64, and 128 bits. It is negative if a target platform does not - support the particular kind. (Fortran 2008 or later.) + 32, 64, and 128 bits. It is negative if a target platform does not + support the particular kind. (Fortran 2008 or later.) `REAL_KINDS': Default-kind integer constant array of rank one containing the @@ -15029,18 +15034,18 @@ default-integer named constants: `STAT_LOCKED': Scalar default-integer constant used as STAT= return value by `LOCK' to denote that the lock variable is locked by the executing - image. (Fortran 2008 or later.) + image. (Fortran 2008 or later.) `STAT_LOCKED_OTHER_IMAGE': Scalar default-integer constant used as STAT= return value by `UNLOCK' to denote that the lock variable is locked by another - image. (Fortran 2008 or later.) + image. (Fortran 2008 or later.) `STAT_STOPPED_IMAGE': Positive, scalar default-integer constant used as STAT= return value if the argument in the statement requires synchronisation with an image, which has initiated the termination of the - execution. (Fortran 2008 or later.) + execution. (Fortran 2008 or later.) `STAT_UNLOCKED': Scalar default-integer constant used as STAT= return value by @@ -15094,13 +15099,13 @@ Furthermore, if `__float128' is supported in C, the named constants `C_FLOAT128, C_FLOAT128_COMPLEX' are defined. Fortran Named constant C type Extension -Type +Type `INTEGER' `C_INT' `int' `INTEGER' `C_SHORT' `short int' `INTEGER' `C_LONG' `long int' `INTEGER' `C_LONG_LONG' `long long int' `INTEGER' `C_SIGNED_CHAR' `signed char'/`unsigned - char' + char' `INTEGER' `C_SIZE_T' `size_t' `INTEGER' `C_INT8_T' `int8_t' `INTEGER' `C_INT16_T' `int16_t' @@ -15335,7 +15340,7 @@ _Bug hunting/squishing_ instead of isolating them. Going through the bugzilla database at `http://gcc.gnu.org/bugzilla/' to reduce testcases posted there and add more information (for example, for which version does the - testcase work, for which versions does it fail?) is also very + testcase work, for which versions does it fail?) is also very helpful. @@ -15882,7 +15887,7 @@ TERMS AND CONDITIONS by modifying or propagating a covered work, you indicate your acceptance of this License to do so. - 10. Automatic Licensing of Downstream Recipients. + 10. Automatic Licensing of Downstream Recipients. Each time you convey a covered work, the recipient automatically receives a license from the original licensors, to run, modify and @@ -15910,7 +15915,7 @@ TERMS AND CONDITIONS using, selling, offering for sale, or importing the Program or any portion of it. - 11. Patents. + 11. Patents. A "contributor" is a copyright holder who authorizes use under this License of the Program or a work on which the Program is based. @@ -15983,7 +15988,7 @@ TERMS AND CONDITIONS any implied license or other defenses to infringement that may otherwise be available to you under applicable patent law. - 12. No Surrender of Others' Freedom. + 12. No Surrender of Others' Freedom. If conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this @@ -15997,7 +16002,7 @@ TERMS AND CONDITIONS terms and this License would be to refrain entirely from conveying the Program. - 13. Use with the GNU Affero General Public License. + 13. Use with the GNU Affero General Public License. Notwithstanding any other provision of this License, you have permission to link or combine any covered work with a work licensed @@ -16008,7 +16013,7 @@ TERMS AND CONDITIONS General Public License, section 13, concerning interaction through a network will apply to the combination as such. - 14. Revised Versions of this License. + 14. Revised Versions of this License. The Free Software Foundation may publish revised and/or new versions of the GNU General Public License from time to time. @@ -16035,19 +16040,19 @@ TERMS AND CONDITIONS author or copyright holder as a result of your choosing to follow a later version. - 15. Disclaimer of Warranty. + 15. Disclaimer of Warranty. THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY - APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE + APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. - 16. Limitation of Liability. + 16. Limitation of Liability. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES @@ -16060,7 +16065,7 @@ TERMS AND CONDITIONS PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. - 17. Interpretation of Sections 15 and 16. + 17. Interpretation of Sections 15 and 16. If the disclaimer of warranty and limitation of liability provided above cannot be given local legal effect according to their terms, @@ -16533,7 +16538,7 @@ GNU Free Documentation License not permanently reinstated, receipt of a copy of some or all of the same material does not give you any rights to use it. - 10. FUTURE REVISIONS OF THIS LICENSE + 10. FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new, revised versions of the GNU Free Documentation License from time to time. Such new @@ -16554,7 +16559,7 @@ GNU Free Documentation License proxy's public statement of acceptance of a version permanently authorizes you to choose that version for the Document. - 11. RELICENSING + 11. RELICENSING "Massive Multiauthor Collaboration Site" (or "MMC Site") means any World Wide Web server that publishes copyrightable works and also @@ -16601,7 +16606,7 @@ notices just after the title page: Free Documentation License''. If you have Invariant Sections, Front-Cover Texts and Back-Cover -Texts, replace the "with...Texts." line with this: +Texts, replace the "with...Texts." line with this: with the Invariant Sections being LIST THEIR TITLES, with the Front-Cover Texts being LIST, and with the Back-Cover Texts @@ -16733,12 +16738,12 @@ look up both forms. (line 54) * fdump-fortran-optimized: Debugging Options. (line 15) * fdump-fortran-original: Debugging Options. (line 10) -* fdump-parse-tree: Debugging Options. (line 18) +* fdump-parse-tree: Debugging Options. (line 19) * fexternal-blas: Code Gen Options. (line 278) * ff2c: Code Gen Options. (line 25) * ffixed-line-length-N: Fortran Dialect Options. (line 77) -* ffpe-trap=LIST: Debugging Options. (line 24) +* ffpe-trap=LIST: Debugging Options. (line 25) * ffree-form: Fortran Dialect Options. (line 11) * ffree-line-length-N: Fortran Dialect Options. @@ -16763,7 +16768,7 @@ look up both forms. * fmodule-private: Fortran Dialect Options. (line 72) * fno-automatic: Code Gen Options. (line 15) -* fno-backtrace: Debugging Options. (line 51) +* fno-backtrace: Debugging Options. (line 52) * fno-fixed-form: Fortran Dialect Options. (line 11) * fno-protect-parens: Code Gen Options. (line 346) @@ -17039,7 +17044,7 @@ Keyword Index (line 60) * backtrace: BACKTRACE. (line 6) * BACKTRACE: BACKTRACE. (line 6) -* backtrace: Debugging Options. (line 51) +* backtrace: Debugging Options. (line 52) * base 10 logarithm function: LOG10. (line 6) * BESJ0: BESSEL_J0. (line 6) * BESJ1: BESSEL_J1. (line 6) @@ -17925,7 +17930,7 @@ Keyword Index * TIME8: TIME8. (line 6) * TINY: TINY. (line 6) * TR 15581: Fortran 2003 status. (line 93) -* trace: Debugging Options. (line 51) +* trace: Debugging Options. (line 52) * TRAILZ: TRAILZ. (line 6) * TRANSFER: TRANSFER. (line 6) * transforming symbol names: Code Gen Options. (line 54) @@ -18028,358 +18033,358 @@ Keyword Index  Tag Table: -Node: Top1990 -Node: Introduction3377 -Node: About GNU Fortran4126 -Node: GNU Fortran and GCC8115 -Node: Preprocessing and conditional compilation10229 -Node: GNU Fortran and G7711873 -Node: Project Status12446 -Node: Standards14893 -Node: Varying Length Character Strings15906 -Node: Invoking GNU Fortran16657 -Node: Option Summary18380 -Node: Fortran Dialect Options21783 -Node: Preprocessing Options30279 -Node: Error and Warning Options38510 -Node: Debugging Options48571 -Node: Directory Options51554 -Node: Link Options52989 -Node: Runtime Options53613 -Node: Code Gen Options55518 -Node: Environment Variables72500 -Node: Runtime73105 -Node: TMPDIR74207 -Node: GFORTRAN_STDIN_UNIT74876 -Node: GFORTRAN_STDOUT_UNIT75258 -Node: GFORTRAN_STDERR_UNIT75659 -Node: GFORTRAN_UNBUFFERED_ALL76061 -Node: GFORTRAN_UNBUFFERED_PRECONNECTED76592 -Node: GFORTRAN_SHOW_LOCUS77236 -Node: GFORTRAN_OPTIONAL_PLUS77732 -Node: GFORTRAN_DEFAULT_RECL78208 -Node: GFORTRAN_LIST_SEPARATOR78697 -Node: GFORTRAN_CONVERT_UNIT79306 -Node: GFORTRAN_ERROR_BACKTRACE82169 -Node: Fortran 2003 and 2008 status82726 -Node: Fortran 2003 status82986 -Node: Fortran 2008 status87883 -Node: TS 29113 status92668 -Node: Compiler Characteristics93644 -Node: KIND Type Parameters94180 -Node: Internal representation of LOGICAL variables95430 -Node: Thread-safety of the runtime library96787 -Node: Data consistency and durability98214 -Node: Extensions101256 -Node: Extensions implemented in GNU Fortran101861 -Node: Old-style kind specifications103219 -Node: Old-style variable initialization104326 -Node: Extensions to namelist105638 -Node: X format descriptor without count field107635 -Node: Commas in FORMAT specifications108162 -Node: Missing period in FORMAT specifications108679 -Node: I/O item lists109241 -Node: `Q' exponent-letter109628 -Node: BOZ literal constants110228 -Node: Real array indices112807 -Node: Unary operators113106 -Node: Implicitly convert LOGICAL and INTEGER values113520 -Node: Hollerith constants support114480 -Node: Cray pointers116252 -Node: CONVERT specifier121699 -Node: OpenMP123697 -Node: Argument list functions125948 -Node: Extensions not implemented in GNU Fortran127554 -Node: STRUCTURE and RECORD128476 -Node: ENCODE and DECODE statements130912 -Node: Variable FORMAT expressions132272 -Node: Alternate complex function syntax133377 -Node: Mixed-Language Programming133897 -Node: Interoperability with C134437 -Node: Intrinsic Types135775 -Node: Derived Types and struct136290 -Node: Interoperable Global Variables137647 -Node: Interoperable Subroutines and Functions138923 -Node: Working with Pointers142719 -Node: Further Interoperability of Fortran with C147195 -Node: GNU Fortran Compiler Directives150545 -Node: Non-Fortran Main Program152737 -Node: _gfortran_set_args154879 -Node: _gfortran_set_options155814 -Node: _gfortran_set_convert158534 -Node: _gfortran_set_record_marker159398 -Node: _gfortran_set_fpe160206 -Node: _gfortran_set_max_subrecord_length161398 -Node: Intrinsic Procedures162318 -Node: Introduction to Intrinsics177804 -Node: ABORT180156 -Node: ABS180902 -Node: ACCESS182519 -Node: ACHAR184440 -Node: ACOS185641 -Node: ACOSH186878 -Node: ADJUSTL187866 -Node: ADJUSTR188807 -Node: AIMAG189754 -Node: AINT191135 -Node: ALARM192722 -Node: ALL194356 -Node: ALLOCATED196274 -Node: AND197411 -Node: ANINT198708 -Node: ANY200186 -Node: ASIN202116 -Node: ASINH203342 -Node: ASSOCIATED204340 -Node: ATAN207345 -Node: ATAN2208764 -Node: ATANH210536 -Node: ATOMIC_DEFINE211536 -Node: ATOMIC_REF212710 -Node: BACKTRACE214070 -Node: BESSEL_J0214649 -Node: BESSEL_J1215697 -Node: BESSEL_JN216749 -Node: BESSEL_Y0218631 -Node: BESSEL_Y1219631 -Node: BESSEL_YN220631 -Node: BGE222463 -Node: BGT223152 -Node: BIT_SIZE223799 -Node: BLE224620 -Node: BLT225299 -Node: BTEST225934 -Node: C_ASSOCIATED226817 -Node: C_F_POINTER228026 -Node: C_F_PROCPOINTER229450 -Node: C_FUNLOC230951 -Node: C_LOC232320 -Node: C_SIZEOF233597 -Node: CEILING235007 -Node: CHAR236012 -Node: CHDIR237216 -Node: CHMOD238384 -Node: CMPLX240247 -Node: COMMAND_ARGUMENT_COUNT241711 -Node: COMPILER_OPTIONS242634 -Node: COMPILER_VERSION243660 -Node: COMPLEX244624 -Node: CONJG245761 -Node: COS246832 -Node: COSH248278 -Node: COUNT249443 -Node: CPU_TIME251459 -Node: CSHIFT252813 -Node: CTIME254469 -Node: DATE_AND_TIME256122 -Node: DBLE258583 -Node: DCMPLX259376 -Node: DIGITS260570 -Node: DIM261536 -Node: DOT_PRODUCT262794 -Node: DPROD264450 -Node: DREAL265367 -Node: DSHIFTL266033 -Node: DSHIFTR267353 -Node: DTIME268674 -Node: EOSHIFT271477 -Node: EPSILON273550 -Node: ERF274276 -Node: ERFC275050 -Node: ERFC_SCALED275854 -Node: ETIME276546 -Node: EXECUTE_COMMAND_LINE278787 -Node: EXIT281367 -Node: EXP282241 -Node: EXPONENT283514 -Node: EXTENDS_TYPE_OF284274 -Node: FDATE285127 -Node: FGET286609 -Node: FGETC288427 -Node: FLOOR290226 -Node: FLUSH291210 -Node: FNUM293085 -Node: FPUT293807 -Node: FPUTC295432 -Node: FRACTION297203 -Node: FREE298104 -Node: FSEEK298939 -Node: FSTAT301233 -Node: FTELL302313 -Node: GAMMA303291 -Node: GERROR304332 -Node: GETARG305051 -Node: GET_COMMAND306815 -Node: GET_COMMAND_ARGUMENT308179 -Node: GETCWD310215 -Node: GETENV311189 -Node: GET_ENVIRONMENT_VARIABLE312614 -Node: GETGID314767 -Node: GETLOG315304 -Node: GETPID316164 -Node: GETUID316894 -Node: GMTIME317410 -Node: HOSTNM318899 -Node: HUGE319817 -Node: HYPOT320538 -Node: IACHAR321358 -Node: IALL322538 -Node: IAND324015 -Node: IANY324999 -Node: IARGC326485 -Node: IBCLR327506 -Node: IBITS328167 -Node: IBSET329082 -Node: ICHAR329738 -Node: IDATE331910 -Node: IEOR332937 -Node: IERRNO333813 -Node: IMAGE_INDEX334362 -Node: INDEX intrinsic335386 -Node: INT336927 -Node: INT2338629 -Node: INT8339394 -Node: IOR340106 -Node: IPARITY340958 -Node: IRAND342482 -Node: IS_IOSTAT_END343838 -Node: IS_IOSTAT_EOR344935 -Node: ISATTY346062 -Node: ISHFT346845 -Node: ISHFTC347825 -Node: ISNAN349041 -Node: ITIME349789 -Node: KILL350814 -Node: KIND351718 -Node: LBOUND352563 -Node: LCOBOUND353896 -Node: LEADZ355026 -Node: LEN355886 -Node: LEN_TRIM357167 -Node: LGE358149 -Node: LGT359651 -Node: LINK361118 -Node: LLE362153 -Node: LLT363647 -Node: LNBLNK365107 -Node: LOC365883 -Node: LOG366614 -Node: LOG10368017 -Node: LOG_GAMMA368991 -Node: LOGICAL370080 -Node: LONG370888 -Node: LSHIFT371644 -Node: LSTAT372729 -Node: LTIME373923 -Node: MALLOC375334 -Node: MASKL376793 -Node: MASKR377556 -Node: MATMUL378322 -Node: MAX379411 -Node: MAXEXPONENT380910 -Node: MAXLOC381726 -Node: MAXVAL383745 -Node: MCLOCK385378 -Node: MCLOCK8386402 -Node: MERGE387635 -Node: MERGE_BITS388384 -Node: MIN389245 -Node: MINEXPONENT390746 -Node: MINLOC391376 -Node: MINVAL393395 -Node: MOD395047 -Node: MODULO396792 -Node: MOVE_ALLOC398092 -Node: MVBITS399121 -Node: NEAREST400180 -Node: NEW_LINE401276 -Node: NINT402047 -Node: NORM2403450 -Node: NOT404588 -Node: NULL405172 -Node: NUM_IMAGES406077 -Node: OR406893 -Node: PACK408177 -Node: PARITY410169 -Node: PERROR411384 -Node: POPCNT412005 -Node: POPPAR412876 -Node: PRECISION413927 -Node: PRESENT414813 -Node: PRODUCT415919 -Node: RADIX417444 -Node: RAN418256 -Node: RAND418712 -Node: RANDOM_NUMBER420044 -Node: RANDOM_SEED421761 -Node: RANGE425439 -Node: RANK426135 -Node: REAL426916 -Node: RENAME428691 -Node: REPEAT429710 -Node: RESHAPE430436 -Node: RRSPACING431905 -Node: RSHIFT432598 -Node: SAME_TYPE_AS433736 -Node: SCALE434566 -Node: SCAN435346 -Node: SECNDS436896 -Node: SECOND437984 -Node: SELECTED_CHAR_KIND438860 -Node: SELECTED_INT_KIND440451 -Node: SELECTED_REAL_KIND441626 -Node: SET_EXPONENT444292 -Node: SHAPE445288 -Node: SHIFTA446703 -Node: SHIFTL447664 -Node: SHIFTR448499 -Node: SIGN449335 -Node: SIGNAL450619 -Node: SIN452116 -Node: SINH453214 -Node: SIZE454210 -Node: SIZEOF455518 -Node: SLEEP456993 -Node: SPACING457553 -Node: SPREAD458566 -Node: SQRT459711 -Node: SRAND461065 -Node: STAT462233 -Node: STORAGE_SIZE465400 -Node: SUM466279 -Node: SYMLNK467762 -Node: SYSTEM468894 -Node: SYSTEM_CLOCK470145 -Node: TAN472261 -Node: TANH473233 -Node: THIS_IMAGE474390 -Node: TIME475882 -Node: TIME8477007 -Node: TINY478157 -Node: TRAILZ478757 -Node: TRANSFER479574 -Node: TRANSPOSE481608 -Node: TRIM482295 -Node: TTYNAM483152 -Node: UBOUND484067 -Node: UCOBOUND485457 -Node: UMASK486589 -Node: UNLINK487267 -Node: UNPACK488244 -Node: VERIFY489532 -Node: XOR491253 -Node: Intrinsic Modules492625 -Node: ISO_FORTRAN_ENV492868 -Node: ISO_C_BINDING497020 -Node: OpenMP Modules OMP_LIB and OMP_LIB_KINDS501237 -Node: Contributing502523 -Node: Contributors503377 -Node: Projects505044 -Node: Proposed Extensions505848 -Node: Copying507859 -Node: GNU Free Documentation License545423 -Node: Funding570566 -Node: Option Index573091 -Node: Keyword Index588082 +Node: Top2004 +Node: Introduction3391 +Node: About GNU Fortran4140 +Node: GNU Fortran and GCC8129 +Node: Preprocessing and conditional compilation10243 +Node: GNU Fortran and G7711887 +Node: Project Status12460 +Node: Standards14907 +Node: Varying Length Character Strings15920 +Node: Invoking GNU Fortran16671 +Node: Option Summary18394 +Node: Fortran Dialect Options21797 +Node: Preprocessing Options30293 +Node: Error and Warning Options38524 +Node: Debugging Options48585 +Node: Directory Options51591 +Node: Link Options53026 +Node: Runtime Options53650 +Node: Code Gen Options55555 +Node: Environment Variables72537 +Node: Runtime73142 +Node: TMPDIR74244 +Node: GFORTRAN_STDIN_UNIT74913 +Node: GFORTRAN_STDOUT_UNIT75295 +Node: GFORTRAN_STDERR_UNIT75696 +Node: GFORTRAN_UNBUFFERED_ALL76098 +Node: GFORTRAN_UNBUFFERED_PRECONNECTED76629 +Node: GFORTRAN_SHOW_LOCUS77273 +Node: GFORTRAN_OPTIONAL_PLUS77769 +Node: GFORTRAN_DEFAULT_RECL78245 +Node: GFORTRAN_LIST_SEPARATOR78734 +Node: GFORTRAN_CONVERT_UNIT79343 +Node: GFORTRAN_ERROR_BACKTRACE82206 +Node: Fortran 2003 and 2008 status82763 +Node: Fortran 2003 status83023 +Node: Fortran 2008 status87920 +Node: TS 29113 status92705 +Node: Compiler Characteristics93681 +Node: KIND Type Parameters94217 +Node: Internal representation of LOGICAL variables95467 +Node: Thread-safety of the runtime library96824 +Node: Data consistency and durability98251 +Node: Extensions101293 +Node: Extensions implemented in GNU Fortran101898 +Node: Old-style kind specifications103256 +Node: Old-style variable initialization104363 +Node: Extensions to namelist105675 +Node: X format descriptor without count field107672 +Node: Commas in FORMAT specifications108199 +Node: Missing period in FORMAT specifications108716 +Node: I/O item lists109278 +Node: `Q' exponent-letter109665 +Node: BOZ literal constants110265 +Node: Real array indices112844 +Node: Unary operators113143 +Node: Implicitly convert LOGICAL and INTEGER values113557 +Node: Hollerith constants support114517 +Node: Cray pointers116289 +Node: CONVERT specifier121736 +Node: OpenMP123734 +Node: Argument list functions125985 +Node: Extensions not implemented in GNU Fortran127591 +Node: STRUCTURE and RECORD128513 +Node: ENCODE and DECODE statements130949 +Node: Variable FORMAT expressions132309 +Node: Alternate complex function syntax133414 +Node: Mixed-Language Programming133934 +Node: Interoperability with C134474 +Node: Intrinsic Types135812 +Node: Derived Types and struct136327 +Node: Interoperable Global Variables137684 +Node: Interoperable Subroutines and Functions138960 +Node: Working with Pointers142756 +Node: Further Interoperability of Fortran with C147232 +Node: GNU Fortran Compiler Directives150582 +Node: Non-Fortran Main Program152774 +Node: _gfortran_set_args154916 +Node: _gfortran_set_options155851 +Node: _gfortran_set_convert158571 +Node: _gfortran_set_record_marker159435 +Node: _gfortran_set_fpe160243 +Node: _gfortran_set_max_subrecord_length161435 +Node: Intrinsic Procedures162355 +Node: Introduction to Intrinsics177841 +Node: ABORT180193 +Node: ABS180939 +Node: ACCESS182556 +Node: ACHAR184477 +Node: ACOS185678 +Node: ACOSH186915 +Node: ADJUSTL187903 +Node: ADJUSTR188844 +Node: AIMAG189791 +Node: AINT191172 +Node: ALARM192759 +Node: ALL194393 +Node: ALLOCATED196311 +Node: AND197448 +Node: ANINT198745 +Node: ANY200223 +Node: ASIN202153 +Node: ASINH203379 +Node: ASSOCIATED204377 +Node: ATAN207382 +Node: ATAN2208801 +Node: ATANH210573 +Node: ATOMIC_DEFINE211573 +Node: ATOMIC_REF212747 +Node: BACKTRACE214107 +Node: BESSEL_J0214686 +Node: BESSEL_J1215734 +Node: BESSEL_JN216786 +Node: BESSEL_Y0218668 +Node: BESSEL_Y1219668 +Node: BESSEL_YN220668 +Node: BGE222500 +Node: BGT223189 +Node: BIT_SIZE223836 +Node: BLE224657 +Node: BLT225336 +Node: BTEST225971 +Node: C_ASSOCIATED226854 +Node: C_F_POINTER228063 +Node: C_F_PROCPOINTER229487 +Node: C_FUNLOC230988 +Node: C_LOC232357 +Node: C_SIZEOF233634 +Node: CEILING235044 +Node: CHAR236049 +Node: CHDIR237253 +Node: CHMOD238421 +Node: CMPLX240284 +Node: COMMAND_ARGUMENT_COUNT241748 +Node: COMPILER_OPTIONS242671 +Node: COMPILER_VERSION243697 +Node: COMPLEX244661 +Node: CONJG245798 +Node: COS246869 +Node: COSH248315 +Node: COUNT249480 +Node: CPU_TIME251496 +Node: CSHIFT252850 +Node: CTIME254506 +Node: DATE_AND_TIME256159 +Node: DBLE258620 +Node: DCMPLX259413 +Node: DIGITS260607 +Node: DIM261573 +Node: DOT_PRODUCT262831 +Node: DPROD264487 +Node: DREAL265404 +Node: DSHIFTL266070 +Node: DSHIFTR267390 +Node: DTIME268711 +Node: EOSHIFT271514 +Node: EPSILON273587 +Node: ERF274313 +Node: ERFC275087 +Node: ERFC_SCALED275891 +Node: ETIME276583 +Node: EXECUTE_COMMAND_LINE278824 +Node: EXIT281404 +Node: EXP282278 +Node: EXPONENT283551 +Node: EXTENDS_TYPE_OF284311 +Node: FDATE285164 +Node: FGET286646 +Node: FGETC288464 +Node: FLOOR290263 +Node: FLUSH291247 +Node: FNUM293122 +Node: FPUT293844 +Node: FPUTC295469 +Node: FRACTION297240 +Node: FREE298141 +Node: FSEEK298976 +Node: FSTAT301270 +Node: FTELL302350 +Node: GAMMA303328 +Node: GERROR304369 +Node: GETARG305088 +Node: GET_COMMAND306852 +Node: GET_COMMAND_ARGUMENT308216 +Node: GETCWD310252 +Node: GETENV311226 +Node: GET_ENVIRONMENT_VARIABLE312651 +Node: GETGID314804 +Node: GETLOG315341 +Node: GETPID316201 +Node: GETUID316931 +Node: GMTIME317447 +Node: HOSTNM318936 +Node: HUGE319854 +Node: HYPOT320575 +Node: IACHAR321395 +Node: IALL322575 +Node: IAND324052 +Node: IANY325036 +Node: IARGC326522 +Node: IBCLR327543 +Node: IBITS328204 +Node: IBSET329119 +Node: ICHAR329775 +Node: IDATE331947 +Node: IEOR332974 +Node: IERRNO333850 +Node: IMAGE_INDEX334399 +Node: INDEX intrinsic335423 +Node: INT336964 +Node: INT2338666 +Node: INT8339431 +Node: IOR340143 +Node: IPARITY340995 +Node: IRAND342519 +Node: IS_IOSTAT_END343875 +Node: IS_IOSTAT_EOR344972 +Node: ISATTY346099 +Node: ISHFT346882 +Node: ISHFTC347862 +Node: ISNAN349078 +Node: ITIME349826 +Node: KILL350851 +Node: KIND351755 +Node: LBOUND352600 +Node: LCOBOUND353933 +Node: LEADZ355063 +Node: LEN355923 +Node: LEN_TRIM357204 +Node: LGE358186 +Node: LGT359688 +Node: LINK361155 +Node: LLE362190 +Node: LLT363684 +Node: LNBLNK365144 +Node: LOC365920 +Node: LOG366651 +Node: LOG10368054 +Node: LOG_GAMMA369028 +Node: LOGICAL370117 +Node: LONG370925 +Node: LSHIFT371681 +Node: LSTAT372766 +Node: LTIME373960 +Node: MALLOC375371 +Node: MASKL376830 +Node: MASKR377593 +Node: MATMUL378359 +Node: MAX379448 +Node: MAXEXPONENT380947 +Node: MAXLOC381763 +Node: MAXVAL383782 +Node: MCLOCK385415 +Node: MCLOCK8386439 +Node: MERGE387672 +Node: MERGE_BITS388421 +Node: MIN389282 +Node: MINEXPONENT390783 +Node: MINLOC391413 +Node: MINVAL393432 +Node: MOD395084 +Node: MODULO396829 +Node: MOVE_ALLOC398129 +Node: MVBITS399158 +Node: NEAREST400217 +Node: NEW_LINE401313 +Node: NINT402084 +Node: NORM2403487 +Node: NOT404625 +Node: NULL405209 +Node: NUM_IMAGES406114 +Node: OR406930 +Node: PACK408214 +Node: PARITY410206 +Node: PERROR411421 +Node: POPCNT412042 +Node: POPPAR412913 +Node: PRECISION413964 +Node: PRESENT414850 +Node: PRODUCT415956 +Node: RADIX417481 +Node: RAN418293 +Node: RAND418749 +Node: RANDOM_NUMBER420081 +Node: RANDOM_SEED421798 +Node: RANGE425610 +Node: RANK426306 +Node: REAL427087 +Node: RENAME428862 +Node: REPEAT429881 +Node: RESHAPE430607 +Node: RRSPACING432076 +Node: RSHIFT432769 +Node: SAME_TYPE_AS433907 +Node: SCALE434737 +Node: SCAN435517 +Node: SECNDS437067 +Node: SECOND438155 +Node: SELECTED_CHAR_KIND439031 +Node: SELECTED_INT_KIND440622 +Node: SELECTED_REAL_KIND441797 +Node: SET_EXPONENT444463 +Node: SHAPE445459 +Node: SHIFTA446874 +Node: SHIFTL447835 +Node: SHIFTR448670 +Node: SIGN449506 +Node: SIGNAL450790 +Node: SIN452287 +Node: SINH453385 +Node: SIZE454381 +Node: SIZEOF455689 +Node: SLEEP457164 +Node: SPACING457724 +Node: SPREAD458737 +Node: SQRT459882 +Node: SRAND461236 +Node: STAT462404 +Node: STORAGE_SIZE465571 +Node: SUM466450 +Node: SYMLNK467933 +Node: SYSTEM469065 +Node: SYSTEM_CLOCK470316 +Node: TAN472432 +Node: TANH473404 +Node: THIS_IMAGE474561 +Node: TIME476053 +Node: TIME8477178 +Node: TINY478328 +Node: TRAILZ478928 +Node: TRANSFER479745 +Node: TRANSPOSE481779 +Node: TRIM482466 +Node: TTYNAM483323 +Node: UBOUND484238 +Node: UCOBOUND485628 +Node: UMASK486760 +Node: UNLINK487438 +Node: UNPACK488415 +Node: VERIFY489703 +Node: XOR491424 +Node: Intrinsic Modules492796 +Node: ISO_FORTRAN_ENV493039 +Node: ISO_C_BINDING497191 +Node: OpenMP Modules OMP_LIB and OMP_LIB_KINDS501408 +Node: Contributing502694 +Node: Contributors503548 +Node: Projects505215 +Node: Proposed Extensions506019 +Node: Copying508030 +Node: GNU Free Documentation License545594 +Node: Funding570737 +Node: Option Index573262 +Node: Keyword Index588253  End Tag Table diff --git a/gcc-4.8/gcc/fortran/interface.c b/gcc-4.8/gcc/fortran/interface.c index 895eee48c..725cd8a4b 100644 --- a/gcc-4.8/gcc/fortran/interface.c +++ b/gcc-4.8/gcc/fortran/interface.c @@ -1245,7 +1245,8 @@ check_result_characteristics (gfc_symbol *s1, gfc_symbol *s2, return FAILURE; } - if (r1->ts.u.cl->length) + if (s1->ts.u.cl && s1->ts.u.cl->length + && s2->ts.u.cl && s2->ts.u.cl->length) { int compval = gfc_dep_compare_expr (r1->ts.u.cl->length, r2->ts.u.cl->length); @@ -1367,8 +1368,8 @@ gfc_compare_interfaces (gfc_symbol *s1, gfc_symbol *s2, const char *name2, if (s1->attr.function && s2->attr.function) { /* If both are functions, check result characteristics. */ - if (check_result_characteristics (s1, s2, errmsg, err_len) - == FAILURE) + if (check_result_characteristics (s1, s2, errmsg, err_len) == FAILURE + || check_result_characteristics (s2, s1, errmsg, err_len) == FAILURE) return 0; } diff --git a/gcc-4.8/gcc/fortran/intrinsic.c b/gcc-4.8/gcc/fortran/intrinsic.c index c571533ef..7d78419a7 100644 --- a/gcc-4.8/gcc/fortran/intrinsic.c +++ b/gcc-4.8/gcc/fortran/intrinsic.c @@ -4229,13 +4229,16 @@ gfc_intrinsic_sub_interface (gfc_code *c, int error_flag) c->resolved_sym->attr.elemental = isym->elemental; } - if (gfc_pure (NULL) && !isym->pure) + if (!isym->pure && gfc_pure (NULL)) { gfc_error ("Subroutine call to intrinsic '%s' at %L is not PURE", name, &c->loc); return MATCH_ERROR; } + if (!isym->pure) + gfc_unset_implicit_pure (NULL); + c->resolved_sym->attr.noreturn = isym->noreturn; return MATCH_YES; diff --git a/gcc-4.8/gcc/fortran/intrinsic.texi b/gcc-4.8/gcc/fortran/intrinsic.texi index 390750186..91adb400e 100644 --- a/gcc-4.8/gcc/fortran/intrinsic.texi +++ b/gcc-4.8/gcc/fortran/intrinsic.texi @@ -10207,10 +10207,11 @@ the @var{SIZE} argument. @item @emph{Example}: @smallexample subroutine init_random_seed() + use iso_fortran_env, only: int64 implicit none integer, allocatable :: seed(:) - integer :: i, n, un, istat, dt(8), pid, t(2), s - integer(8) :: count, tms + integer :: i, n, un, istat, dt(8), pid + integer(int64) :: t call random_seed(size = n) allocate(seed(n)) @@ -10224,34 +10225,37 @@ subroutine init_random_seed() ! Fallback to XOR:ing the current time and pid. The PID is ! useful in case one launches multiple instances of the same ! program in parallel. - call system_clock(count) - if (count /= 0) then - t = transfer(count, t) - else + call system_clock(t) + if (t == 0) then call date_and_time(values=dt) - tms = (dt(1) - 1970) * 365_8 * 24 * 60 * 60 * 1000 & - + dt(2) * 31_8 * 24 * 60 * 60 * 1000 & - + dt(3) * 24 * 60 * 60 * 60 * 1000 & + t = (dt(1) - 1970) * 365_int64 * 24 * 60 * 60 * 1000 & + + dt(2) * 31_int64 * 24 * 60 * 60 * 1000 & + + dt(3) * 24_int64 * 60 * 60 * 1000 & + dt(5) * 60 * 60 * 1000 & + dt(6) * 60 * 1000 + dt(7) * 1000 & + dt(8) - t = transfer(tms, t) end if - s = ieor(t(1), t(2)) - pid = getpid() + 1099279 ! Add a prime - s = ieor(s, pid) - if (n >= 3) then - seed(1) = t(1) + 36269 - seed(2) = t(2) + 72551 - seed(3) = pid - if (n > 3) then - seed(4:) = s + 37 * (/ (i, i = 0, n - 4) /) + pid = getpid() + t = ieor(t, int(pid, kind(t))) + do i = 1, n + seed(i) = lcg(t) + end do end if + call random_seed(put=seed) +contains + ! This simple PRNG might not be good enough for real work, but is + ! sufficient for seeding a better PRNG. + function lcg(s) + integer :: lcg + integer(int64) :: s + if (s == 0) then + s = 104729 else - seed = s + 37 * (/ (i, i = 0, n - 1 ) /) + s = mod(s, 4294967296_int64) end if - end if - call random_seed(put=seed) + s = mod(s * 279470273_int64, 4294967291_int64) + lcg = int(mod(s, int(huge(0), int64)), kind(0)) + end function lcg end subroutine init_random_seed @end smallexample diff --git a/gcc-4.8/gcc/fortran/invoke.texi b/gcc-4.8/gcc/fortran/invoke.texi index db958f9b3..b0b43d847 100644 --- a/gcc-4.8/gcc/fortran/invoke.texi +++ b/gcc-4.8/gcc/fortran/invoke.texi @@ -982,11 +982,12 @@ Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the GNU Fortran compiler itself. -@item -fdump-optimized-tree +@item -fdump-fortran-optimized @opindex @code{fdump-fortran-optimized} Output the parse tree after front-end optimization. Only really useful for debugging the GNU Fortran compiler itself. +@item -fdump-parse-tree @opindex @code{fdump-parse-tree} Output the internal parse tree after translating the source program into internal representation. Only really useful for debugging the diff --git a/gcc-4.8/gcc/fortran/io.c b/gcc-4.8/gcc/fortran/io.c index 748a4f2fb..1d464742f 100644 --- a/gcc-4.8/gcc/fortran/io.c +++ b/gcc-4.8/gcc/fortran/io.c @@ -1309,7 +1309,8 @@ match_vtag (const io_tag *tag, gfc_expr **v) return MATCH_ERROR; } - if (gfc_pure (NULL) && gfc_impure_variable (result->symtree->n.sym)) + bool impure = gfc_impure_variable (result->symtree->n.sym); + if (impure && gfc_pure (NULL)) { gfc_error ("Variable %s cannot be assigned in PURE procedure at %C", tag->name); @@ -1317,8 +1318,8 @@ match_vtag (const io_tag *tag, gfc_expr **v) return MATCH_ERROR; } - if (gfc_implicit_pure (NULL) && gfc_impure_variable (result->symtree->n.sym)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + if (impure) + gfc_unset_implicit_pure (NULL); *v = result; return MATCH_YES; @@ -1838,8 +1839,7 @@ gfc_match_open (void) goto cleanup; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); warn = (open->err || open->iostat) ? true : false; @@ -2251,8 +2251,7 @@ gfc_match_close (void) goto cleanup; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); warn = (close->iostat || close->err) ? true : false; @@ -2419,8 +2418,7 @@ done: goto cleanup; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); new_st.op = op; new_st.ext.filepos = fp; @@ -3276,9 +3274,8 @@ if (condition) \ "an internal file in a PURE procedure", io_kind_name (k)); - if (gfc_implicit_pure (NULL) && (k == M_READ || k == M_WRITE)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; - + if (k == M_READ || k == M_WRITE) + gfc_unset_implicit_pure (NULL); } if (k != M_READ) @@ -3809,8 +3806,7 @@ gfc_match_print (void) return MATCH_ERROR; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); return MATCH_YES; } @@ -3969,8 +3965,7 @@ gfc_match_inquire (void) return MATCH_ERROR; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); new_st.block = gfc_get_code (); new_st.block->op = EXEC_IOLENGTH; @@ -4023,8 +4018,7 @@ gfc_match_inquire (void) goto cleanup; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); if (inquire->id != NULL && inquire->pending == NULL) { @@ -4212,8 +4206,7 @@ gfc_match_wait (void) goto cleanup; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); new_st.op = EXEC_WAIT; new_st.ext.wait = wait; diff --git a/gcc-4.8/gcc/fortran/match.c b/gcc-4.8/gcc/fortran/match.c index a320248fe..9827b6c48 100644 --- a/gcc-4.8/gcc/fortran/match.c +++ b/gcc-4.8/gcc/fortran/match.c @@ -1753,8 +1753,7 @@ gfc_match_critical (void) return MATCH_ERROR; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); if (gfc_notify_std (GFC_STD_F2008, "CRITICAL statement at %C") == FAILURE) @@ -2683,8 +2682,7 @@ gfc_match_stopcode (gfc_statement st) goto cleanup; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); if (st == ST_STOP && gfc_find_state (COMP_CRITICAL) == SUCCESS) { @@ -2824,8 +2822,7 @@ lock_unlock_statement (gfc_statement st) return MATCH_ERROR; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); if (gfc_option.coarray == GFC_FCOARRAY_NONE) { @@ -3020,8 +3017,7 @@ sync_statement (gfc_statement st) return MATCH_ERROR; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); if (gfc_notify_std (GFC_STD_F2008, "SYNC statement at %C") == FAILURE) @@ -3500,15 +3496,15 @@ gfc_match_allocate (void) if (gfc_check_do_variable (tail->expr->symtree)) goto cleanup; - if (gfc_pure (NULL) && gfc_impure_variable (tail->expr->symtree->n.sym)) + bool impure = gfc_impure_variable (tail->expr->symtree->n.sym); + if (impure && gfc_pure (NULL)) { gfc_error ("Bad allocate-object at %C for a PURE procedure"); goto cleanup; } - if (gfc_implicit_pure (NULL) - && gfc_impure_variable (tail->expr->symtree->n.sym)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + if (impure) + gfc_unset_implicit_pure (NULL); if (tail->expr->ts.deferred) { @@ -3890,14 +3886,15 @@ gfc_match_deallocate (void) sym = tail->expr->symtree->n.sym; - if (gfc_pure (NULL) && gfc_impure_variable (sym)) + bool impure = gfc_impure_variable (sym); + if (impure && gfc_pure (NULL)) { gfc_error ("Illegal allocate-object at %C for a PURE procedure"); goto cleanup; } - if (gfc_implicit_pure (NULL) && gfc_impure_variable (sym)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + if (impure) + gfc_unset_implicit_pure (NULL); if (gfc_is_coarray (tail->expr) && gfc_find_state (COMP_DO_CONCURRENT) == SUCCESS) diff --git a/gcc-4.8/gcc/fortran/module.c b/gcc-4.8/gcc/fortran/module.c index f0f8f971e..7eb205c8d 100644 --- a/gcc-4.8/gcc/fortran/module.c +++ b/gcc-4.8/gcc/fortran/module.c @@ -386,37 +386,6 @@ get_integer (int integer) } -/* Recursive function to find a pointer within a tree by brute force. */ - -static pointer_info * -fp2 (pointer_info *p, const void *target) -{ - pointer_info *q; - - if (p == NULL) - return NULL; - - if (p->u.pointer == target) - return p; - - q = fp2 (p->left, target); - if (q != NULL) - return q; - - return fp2 (p->right, target); -} - - -/* During reading, find a pointer_info node from the pointer value. - This amounts to a brute-force search. */ - -static pointer_info * -find_pointer2 (void *p) -{ - return fp2 (pi_root, p); -} - - /* Resolve any fixups using a known pointer. */ static void @@ -2522,45 +2491,13 @@ mio_pointer_ref (void *gp) the namespace and is not loaded again. */ static void -mio_component_ref (gfc_component **cp, gfc_symbol *sym) +mio_component_ref (gfc_component **cp) { - char name[GFC_MAX_SYMBOL_LEN + 1]; - gfc_component *q; pointer_info *p; p = mio_pointer_ref (cp); if (p->type == P_UNKNOWN) p->type = P_COMPONENT; - - if (iomode == IO_OUTPUT) - mio_pool_string (&(*cp)->name); - else - { - mio_internal_string (name); - - if (sym && sym->attr.is_class) - sym = sym->components->ts.u.derived; - - /* It can happen that a component reference can be read before the - associated derived type symbol has been loaded. Return now and - wait for a later iteration of load_needed. */ - if (sym == NULL) - return; - - if (sym->components != NULL && p->u.pointer == NULL) - { - /* Symbol already loaded, so search by name. */ - q = gfc_find_component (sym, name, true, true); - - if (q) - associate_integer_pointer (p, q); - } - - /* Make sure this symbol will eventually be loaded. */ - p = find_pointer2 (sym); - if (p->u.rsym.state == UNUSED) - p->u.rsym.state = NEEDED; - } } @@ -2917,7 +2854,7 @@ mio_ref (gfc_ref **rp) case REF_COMPONENT: mio_symbol_ref (&r->u.c.sym); - mio_component_ref (&r->u.c.component, r->u.c.sym); + mio_component_ref (&r->u.c.component); break; case REF_SUBSTRING: @@ -3772,7 +3709,9 @@ mio_full_f2k_derived (gfc_symbol *sym) /* Unlike most other routines, the address of the symbol node is already - fixed on input and the name/module has already been filled in. */ + fixed on input and the name/module has already been filled in. + If you update the symbol format here, don't forget to update read_module + as well (look for "seek to the symbol's component list"). */ static void mio_symbol (gfc_symbol *sym) @@ -3782,6 +3721,7 @@ mio_symbol (gfc_symbol *sym) mio_lparen (); mio_symbol_attribute (&sym->attr); + mio_typespec (&sym->ts); if (sym->ts.type == BT_CLASS) sym->attr.class_ok = 1; @@ -3812,7 +3752,6 @@ mio_symbol (gfc_symbol *sym) /* Note that components are always saved, even if they are supposed to be private. Component access is checked during searching. */ - mio_component_list (&sym->components, sym->attr.vtype); if (sym->components != NULL) @@ -3914,14 +3853,17 @@ find_symbol (gfc_symtree *st, const char *name, } -/* Skip a list between balanced left and right parens. */ +/* Skip a list between balanced left and right parens. + By setting NEST_LEVEL one assumes that a number of NEST_LEVEL opening parens + have been already parsed by hand, and the remaining of the content is to be + skipped here. The default value is 0 (balanced parens). */ static void -skip_list (void) +skip_list (int nest_level = 0) { int level; - level = 0; + level = nest_level; do { switch (parse_atom ()) @@ -4555,7 +4497,6 @@ read_module (void) info->u.rsym.ns = atom_int; get_module_locus (&info->u.rsym.where); - skip_list (); /* See if the symbol has already been loaded by a previous module. If so, we reference the existing symbol and prevent it from @@ -4566,10 +4507,56 @@ read_module (void) if (sym == NULL || (sym->attr.flavor == FL_VARIABLE && info->u.rsym.ns !=1)) + { + skip_list (); continue; + } info->u.rsym.state = USED; info->u.rsym.sym = sym; + /* The current symbol has already been loaded, so we can avoid loading + it again. However, if it is a derived type, some of its components + can be used in expressions in the module. To avoid the module loading + failing, we need to associate the module's component pointer indexes + with the existing symbol's component pointers. */ + if (sym->attr.flavor == FL_DERIVED) + { + gfc_component *c; + + /* First seek to the symbol's component list. */ + mio_lparen (); /* symbol opening. */ + skip_list (); /* skip symbol attribute. */ + skip_list (); /* typespec. */ + require_atom (ATOM_INTEGER); /* namespace ref. */ + require_atom (ATOM_INTEGER); /* common ref. */ + skip_list (); /* formal args. */ + /* no value. */ + skip_list (); /* array_spec. */ + require_atom (ATOM_INTEGER); /* result. */ + /* not a cray pointer. */ + + mio_lparen (); /* component list opening. */ + for (c = sym->components; c; c = c->next) + { + pointer_info *p; + const char *comp_name; + int n; + + mio_lparen (); /* component opening. */ + mio_integer (&n); + p = get_integer (n); + if (p->u.pointer == NULL) + associate_integer_pointer (p, c); + mio_pool_string (&comp_name); + gcc_assert (comp_name == c->name); + skip_list (1); /* component end. */ + } + mio_rparen (); /* component list closing. */ + + skip_list (1); /* symbol end. */ + } + else + skip_list (); /* Some symbols do not have a namespace (eg. formal arguments), so the automatic "unique symtree" mechanism must be suppressed diff --git a/gcc-4.8/gcc/fortran/parse.c b/gcc-4.8/gcc/fortran/parse.c index 33d325d8d..f748fe326 100644 --- a/gcc-4.8/gcc/fortran/parse.c +++ b/gcc-4.8/gcc/fortran/parse.c @@ -550,8 +550,7 @@ decode_omp_directive (void) return ST_NONE; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); old_locus = gfc_current_locus; diff --git a/gcc-4.8/gcc/fortran/primary.c b/gcc-4.8/gcc/fortran/primary.c index d14922416..f44bf575e 100644 --- a/gcc-4.8/gcc/fortran/primary.c +++ b/gcc-4.8/gcc/fortran/primary.c @@ -2252,7 +2252,7 @@ gfc_expr_attr (gfc_expr *e) case EXPR_FUNCTION: gfc_clear_attr (&attr); - if (e->value.function.esym != NULL) + if (e->value.function.esym && e->value.function.esym->result) { gfc_symbol *sym = e->value.function.esym->result; attr = sym->attr; @@ -2540,6 +2540,7 @@ gfc_convert_to_structure_constructor (gfc_expr *e, gfc_symbol *sym, gfc_expr **c if (parent && !comp) break; + if (actual) actual = actual->next; } diff --git a/gcc-4.8/gcc/fortran/resolve.c b/gcc-4.8/gcc/fortran/resolve.c index 486a22c2d..755ea90bd 100644 --- a/gcc-4.8/gcc/fortran/resolve.c +++ b/gcc-4.8/gcc/fortran/resolve.c @@ -1,5 +1,5 @@ /* Perform type resolution on the various structures. - Copyright (C) 2001-2013 Free Software Foundation, Inc. + Copyright (C) 2001-2014 Free Software Foundation, Inc. Contributed by Andy Vaught This file is part of GCC. @@ -1259,9 +1259,10 @@ resolve_structure_cons (gfc_expr *expr, int init) } /* F2003, C1272 (3). */ - if (gfc_pure (NULL) && cons->expr->expr_type == EXPR_VARIABLE + bool impure = cons->expr->expr_type == EXPR_VARIABLE && (gfc_impure_variable (cons->expr->symtree->n.sym) - || gfc_is_coindexed (cons->expr))) + || gfc_is_coindexed (cons->expr)); + if (impure && gfc_pure (NULL)) { t = FAILURE; gfc_error ("Invalid expression in the structure constructor for " @@ -1269,12 +1270,8 @@ resolve_structure_cons (gfc_expr *expr, int init) comp->name, &cons->expr->where); } - if (gfc_implicit_pure (NULL) - && cons->expr->expr_type == EXPR_VARIABLE - && (gfc_impure_variable (cons->expr->symtree->n.sym) - || gfc_is_coindexed (cons->expr))) - gfc_current_ns->proc_name->attr.implicit_pure = 0; - + if (impure) + gfc_unset_implicit_pure (NULL); } return t; @@ -3295,8 +3292,7 @@ resolve_function (gfc_expr *expr) t = FAILURE; } - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); } /* Functions without the RECURSIVE attribution are not allowed to @@ -3361,8 +3357,7 @@ pure_subroutine (gfc_code *c, gfc_symbol *sym) gfc_error ("Subroutine call to '%s' at %L is not PURE", sym->name, &c->loc); - if (gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); } @@ -8705,10 +8700,11 @@ resolve_transfer (gfc_code *code) && exp->value.op.op == INTRINSIC_PARENTHESES) exp = exp->value.op.op1; - if (exp && exp->expr_type == EXPR_NULL && exp->ts.type == BT_UNKNOWN) + if (exp && exp->expr_type == EXPR_NULL + && code->ext.dt) { - gfc_error ("NULL intrinsic at %L in data transfer statement requires " - "MOLD=", &exp->where); + gfc_error ("Invalid context for NULL () intrinsic at %L", + &exp->where); return; } @@ -9612,7 +9608,7 @@ resolve_ordinary_assign (gfc_code *code, gfc_namespace *ns) if (lhs->expr_type == EXPR_VARIABLE && lhs->symtree->n.sym != gfc_current_ns->proc_name && lhs->symtree->n.sym->ns != gfc_current_ns) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); if (lhs->ts.type == BT_DERIVED && lhs->expr_type == EXPR_VARIABLE @@ -9620,11 +9616,11 @@ resolve_ordinary_assign (gfc_code *code, gfc_namespace *ns) && rhs->expr_type == EXPR_VARIABLE && (gfc_impure_variable (rhs->symtree->n.sym) || gfc_is_coindexed (rhs))) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); /* Fortran 2008, C1283. */ if (gfc_is_coindexed (lhs)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + gfc_unset_implicit_pure (NULL); } /* F03:7.4.1.2. */ @@ -11057,7 +11053,7 @@ build_default_init_expr (gfc_symbol *sym) init_expr = NULL; } if (!init_expr && gfc_option.flag_init_character == GFC_INIT_CHARACTER_ON - && sym->ts.u.cl->length) + && sym->ts.u.cl->length && gfc_option.flag_max_stack_var_size != 0) { gfc_actual_arglist *arg; init_expr = gfc_get_expr (); @@ -11877,6 +11873,7 @@ check_generic_tbp_ambiguity (gfc_tbp_generic* t1, gfc_tbp_generic* t2, { gfc_symbol *sym1, *sym2; const char *pass1, *pass2; + gfc_formal_arglist *dummy_args; gcc_assert (t1->specific && t2->specific); gcc_assert (!t1->specific->is_generic); @@ -11899,19 +11896,33 @@ check_generic_tbp_ambiguity (gfc_tbp_generic* t1, gfc_tbp_generic* t2, return FAILURE; } - /* Compare the interfaces. */ + /* Determine PASS arguments. */ if (t1->specific->nopass) pass1 = NULL; else if (t1->specific->pass_arg) pass1 = t1->specific->pass_arg; else - pass1 = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym)->sym->name; + { + dummy_args = gfc_sym_get_dummy_args (t1->specific->u.specific->n.sym); + if (dummy_args) + pass1 = dummy_args->sym->name; + else + pass1 = NULL; + } if (t2->specific->nopass) pass2 = NULL; else if (t2->specific->pass_arg) pass2 = t2->specific->pass_arg; else - pass2 = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym)->sym->name; + { + dummy_args = gfc_sym_get_dummy_args (t2->specific->u.specific->n.sym); + if (dummy_args) + pass2 = dummy_args->sym->name; + else + pass2 = NULL; + } + + /* Compare the interfaces. */ if (gfc_compare_interfaces (sym1, sym2, sym2->name, !t1->is_operator, 0, NULL, 0, pass1, pass2)) { @@ -12425,9 +12436,6 @@ resolve_typebound_procedures (gfc_symbol* derived) resolve_bindings_derived = derived; resolve_bindings_result = SUCCESS; - /* Make sure the vtab has been generated. */ - gfc_find_derived_vtab (derived); - if (derived->f2k_derived->tb_sym_root) gfc_traverse_symtree (derived->f2k_derived->tb_sym_root, &resolve_typebound_procedure); @@ -13256,7 +13264,8 @@ resolve_symbol (gfc_symbol *sym) if (sym->attr.flavor == FL_UNKNOWN || (sym->attr.flavor == FL_PROCEDURE && !sym->attr.intrinsic && !sym->attr.generic && !sym->attr.external - && sym->attr.if_source == IFSRC_UNKNOWN)) + && sym->attr.if_source == IFSRC_UNKNOWN + && sym->ts.type == BT_UNKNOWN)) { /* If we find that a flavorless symbol is an interface in one of the @@ -14376,6 +14385,33 @@ gfc_implicit_pure (gfc_symbol *sym) } +void +gfc_unset_implicit_pure (gfc_symbol *sym) +{ + gfc_namespace *ns; + + if (sym == NULL) + { + /* Check if the current procedure is implicit_pure. Walk up + the procedure list until we find a procedure. */ + for (ns = gfc_current_ns; ns; ns = ns->parent) + { + sym = ns->proc_name; + if (sym == NULL) + return; + + if (sym->attr.flavor == FL_PROCEDURE) + break; + } + } + + if (sym->attr.flavor == FL_PROCEDURE) + sym->attr.implicit_pure = 0; + else + sym->attr.pure = 0; +} + + /* Test whether the current procedure is elemental or not. */ int diff --git a/gcc-4.8/gcc/fortran/simplify.c b/gcc-4.8/gcc/fortran/simplify.c index b03096b65..7c21f226d 100644 --- a/gcc-4.8/gcc/fortran/simplify.c +++ b/gcc-4.8/gcc/fortran/simplify.c @@ -5528,7 +5528,7 @@ gfc_simplify_shape (gfc_expr *source, gfc_expr *kind) if (e == &gfc_bad_expr || range_check (e, "SHAPE") == &gfc_bad_expr) { gfc_free_expr (result); - if (t) + if (t == SUCCESS) gfc_clear_shape (shape, source->rank); return &gfc_bad_expr; } @@ -5536,7 +5536,7 @@ gfc_simplify_shape (gfc_expr *source, gfc_expr *kind) gfc_constructor_append_expr (&result->value.constructor, e, NULL); } - if (t) + if (t == SUCCESS) gfc_clear_shape (shape, source->rank); return result; diff --git a/gcc-4.8/gcc/fortran/symbol.c b/gcc-4.8/gcc/fortran/symbol.c index ef4076df3..1b3702f82 100644 --- a/gcc-4.8/gcc/fortran/symbol.c +++ b/gcc-4.8/gcc/fortran/symbol.c @@ -1110,8 +1110,8 @@ gfc_add_save (symbol_attribute *attr, save_state s, const char *name, return FAILURE; } - if (s == SAVE_EXPLICIT && gfc_implicit_pure (NULL)) - gfc_current_ns->proc_name->attr.implicit_pure = 0; + if (s == SAVE_EXPLICIT) + gfc_unset_implicit_pure (NULL); if (s == SAVE_EXPLICIT && attr->save == SAVE_EXPLICIT) { diff --git a/gcc-4.8/gcc/fortran/trans-array.c b/gcc-4.8/gcc/fortran/trans-array.c index b34f6fb19..8da24a257 100644 --- a/gcc-4.8/gcc/fortran/trans-array.c +++ b/gcc-4.8/gcc/fortran/trans-array.c @@ -1,5 +1,5 @@ /* Array translation routines - Copyright (C) 2002-2013 Free Software Foundation, Inc. + Copyright (C) 2002-2014 Free Software Foundation, Inc. Contributed by Paul Brook and Steven Bosscher @@ -2487,6 +2487,11 @@ gfc_add_loop_ss_code (gfc_loopinfo * loop, gfc_ss * ss, bool subscript, a reference to the value. */ gfc_conv_expr (&se, expr); } + + /* Ensure that a pointer to the string is stored. */ + if (expr->ts.type == BT_CHARACTER) + gfc_conv_string_parameter (&se); + gfc_add_block_to_block (&outer_loop->pre, &se.pre); gfc_add_block_to_block (&outer_loop->post, &se.post); if (gfc_is_class_scalar_expr (expr)) @@ -7940,6 +7945,7 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, tree size1; tree size2; tree array1; + tree cond_null; tree cond; tree tmp; tree tmp2; @@ -8015,9 +8021,9 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, jump_label2 = gfc_build_label_decl (NULL_TREE); /* Allocate if data is NULL. */ - cond = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, + cond_null = fold_build2_loc (input_location, EQ_EXPR, boolean_type_node, array1, build_int_cst (TREE_TYPE (array1), 0)); - tmp = build3_v (COND_EXPR, cond, + tmp = build3_v (COND_EXPR, cond_null, build1_v (GOTO_EXPR, jump_label1), build_empty_stmt (input_location)); gfc_add_expr_to_block (&fblock, tmp); @@ -8069,13 +8075,25 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, tmp = build1_v (LABEL_EXPR, jump_label1); gfc_add_expr_to_block (&fblock, tmp); - size1 = gfc_conv_descriptor_size (desc, expr1->rank); + /* If the lhs has not been allocated, its bounds will not have been + initialized and so its size is set to zero. */ + size1 = gfc_create_var (gfc_array_index_type, NULL); + gfc_init_block (&alloc_block); + gfc_add_modify (&alloc_block, size1, gfc_index_zero_node); + gfc_init_block (&realloc_block); + gfc_add_modify (&realloc_block, size1, + gfc_conv_descriptor_size (desc, expr1->rank)); + tmp = build3_v (COND_EXPR, cond_null, + gfc_finish_block (&alloc_block), + gfc_finish_block (&realloc_block)); + gfc_add_expr_to_block (&fblock, tmp); - /* Get the rhs size. Fix both sizes. */ + /* Get the rhs size and fix it. */ if (expr2) desc2 = rss->info->data.array.descriptor; else desc2 = NULL_TREE; + size2 = gfc_index_one_node; for (n = 0; n < expr2->rank; n++) { @@ -8089,8 +8107,6 @@ gfc_alloc_allocatable_for_assignment (gfc_loopinfo *loop, gfc_array_index_type, tmp, size2); } - - size1 = gfc_evaluate_now (size1, &fblock); size2 = gfc_evaluate_now (size2, &fblock); cond = fold_build2_loc (input_location, NE_EXPR, boolean_type_node, diff --git a/gcc-4.8/gcc/fortran/trans-decl.c b/gcc-4.8/gcc/fortran/trans-decl.c index 7806bbbd8..7d2356187 100644 --- a/gcc-4.8/gcc/fortran/trans-decl.c +++ b/gcc-4.8/gcc/fortran/trans-decl.c @@ -1013,6 +1013,10 @@ gfc_build_dummy_array_decl (gfc_symbol * sym, tree dummy) TREE_STATIC (decl) = 0; DECL_EXTERNAL (decl) = 0; + /* Avoid uninitialized warnings for optional dummy arguments. */ + if (sym->attr.optional) + TREE_NO_WARNING (decl) = 1; + /* We should never get deferred shape arrays here. We used to because of frontend bugs. */ gcc_assert (sym->as->type != AS_DEFERRED); @@ -1358,9 +1362,10 @@ gfc_get_symbol_decl (gfc_symbol * sym) if (sym->attr.flavor == FL_PROCEDURE) { - /* Catch function declarations. Only used for actual parameters, + /* Catch functions. Only used for actual parameters, procedure pointers and procptr initialization targets. */ - if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic) + if (sym->attr.external || sym->attr.use_assoc || sym->attr.intrinsic + || sym->attr.if_source != IFSRC_DECL) { decl = gfc_get_extern_function_decl (sym); gfc_set_decl_location (decl, &sym->declared_at); diff --git a/gcc-4.8/gcc/fortran/trans-expr.c b/gcc-4.8/gcc/fortran/trans-expr.c index 2c3ff1fc3..07d51ba10 100644 --- a/gcc-4.8/gcc/fortran/trans-expr.c +++ b/gcc-4.8/gcc/fortran/trans-expr.c @@ -355,7 +355,11 @@ gfc_conv_derived_to_class (gfc_se *parmse, gfc_expr *e, gfc_conv_expr_descriptor (parmse, e); if (e->rank != class_ts.u.derived->components->as->rank) - class_array_data_assign (&block, ctree, parmse->expr, true); + { + gcc_assert (class_ts.u.derived->components->as->type + == AS_ASSUMED_RANK); + class_array_data_assign (&block, ctree, parmse->expr, false); + } else { if (gfc_expr_attr (e).codimension) @@ -670,7 +674,6 @@ gfc_conv_class_to_class (gfc_se *parmse, gfc_expr *e, gfc_typespec class_ts, gfc_add_modify (&parmse->post, vptr, fold_convert (TREE_TYPE (vptr), ctree)); - gcc_assert (!optional || (optional && !copyback)); if (optional) { tree tmp2; @@ -6343,7 +6346,13 @@ gfc_conv_expr_reference (gfc_se * se, gfc_expr * expr) /* Returns a reference to the scalar evaluated outside the loop for this case. */ gfc_conv_expr (se, expr); + + if (expr->ts.type == BT_CHARACTER + && expr->expr_type != EXPR_FUNCTION) + gfc_conv_string_parameter (se); + else se->expr = gfc_build_addr_expr (NULL_TREE, se->expr); + return; } diff --git a/gcc-4.8/gcc/fortran/trans-intrinsic.c b/gcc-4.8/gcc/fortran/trans-intrinsic.c index ddd9eaea5..273c86ff4 100644 --- a/gcc-4.8/gcc/fortran/trans-intrinsic.c +++ b/gcc-4.8/gcc/fortran/trans-intrinsic.c @@ -4684,9 +4684,11 @@ gfc_conv_intrinsic_index_scan_verify (gfc_se * se, gfc_expr * expr, static void gfc_conv_intrinsic_ichar (gfc_se * se, gfc_expr * expr) { - tree args[2], type, pchartype; + tree args[3], type, pchartype; + int nargs; - gfc_conv_intrinsic_function_args (se, expr, args, 2); + nargs = gfc_intrinsic_argument_list_length (expr); + gfc_conv_intrinsic_function_args (se, expr, args, nargs); gcc_assert (POINTER_TYPE_P (TREE_TYPE (args[1]))); pchartype = gfc_get_pchar_type (expr->value.function.actual->expr->ts.kind); args[1] = fold_build1_loc (input_location, NOP_EXPR, pchartype, args[1]); diff --git a/gcc-4.8/gcc/fortran/trans-io.c b/gcc-4.8/gcc/fortran/trans-io.c index 9394810f0..afb0354d7 100644 --- a/gcc-4.8/gcc/fortran/trans-io.c +++ b/gcc-4.8/gcc/fortran/trans-io.c @@ -2158,6 +2158,12 @@ transfer_expr (gfc_se * se, gfc_typespec * ts, tree addr_expr, gfc_code * code) expr = build_fold_indirect_ref_loc (input_location, expr); + /* Make sure that the derived type has been built. An external + function, if only referenced in an io statement requires this + check (see PR58771). */ + if (ts->u.derived->backend_decl == NULL_TREE) + tmp = gfc_typenode_for_spec (ts); + for (c = ts->u.derived->components; c; c = c->next) { field = c->backend_decl; diff --git a/gcc-4.8/gcc/fortran/trans-stmt.c b/gcc-4.8/gcc/fortran/trans-stmt.c index 430b10e37..1d8588d60 100644 --- a/gcc-4.8/gcc/fortran/trans-stmt.c +++ b/gcc-4.8/gcc/fortran/trans-stmt.c @@ -5104,10 +5104,49 @@ gfc_trans_allocate (gfc_code * code) { gfc_expr *lhs, *rhs; gfc_se lse; + gfc_ref *ref, *class_ref, *tail; + + /* Find the last class reference. */ + class_ref = NULL; + for (ref = e->ref; ref; ref = ref->next) + { + if (ref->type == REF_COMPONENT + && ref->u.c.component->ts.type == BT_CLASS) + class_ref = ref; + + if (ref->next == NULL) + break; + } + + /* Remove and store all subsequent references after the + CLASS reference. */ + if (class_ref) + { + tail = class_ref->next; + class_ref->next = NULL; + } + else + { + tail = e->ref; + e->ref = NULL; + } lhs = gfc_expr_to_initialize (e); gfc_add_vptr_component (lhs); + /* Remove the _vptr component and restore the original tail + references. */ + if (class_ref) + { + gfc_free_ref_list (class_ref->next); + class_ref->next = tail; + } + else + { + gfc_free_ref_list (e->ref); + e->ref = tail; + } + if (class_expr != NULL_TREE) { /* Polymorphic SOURCE: VPTR must be determined at run time. */ diff --git a/gcc-4.8/gcc/function.c b/gcc-4.8/gcc/function.c index e673f21a5..a67167ab6 100644 --- a/gcc-4.8/gcc/function.c +++ b/gcc-4.8/gcc/function.c @@ -2507,6 +2507,7 @@ assign_parm_find_entry_rtl (struct assign_parm_data_all *all, } locate_and_pad_parm (data->promoted_mode, data->passed_type, in_regs, + all->reg_parm_stack_space, entry_parm ? data->partial : 0, current_function_decl, &all->stack_args_size, &data->locate); @@ -3485,11 +3486,7 @@ assign_parms (tree fndecl) /* Adjust function incoming argument size for alignment and minimum length. */ -#ifdef REG_PARM_STACK_SPACE - crtl->args.size = MAX (crtl->args.size, - REG_PARM_STACK_SPACE (fndecl)); -#endif - + crtl->args.size = MAX (crtl->args.size, all.reg_parm_stack_space); crtl->args.size = CEIL_ROUND (crtl->args.size, PARM_BOUNDARY / BITS_PER_UNIT); @@ -3693,6 +3690,9 @@ gimplify_parameters (void) IN_REGS is nonzero if the argument will be passed in registers. It will never be set if REG_PARM_STACK_SPACE is not defined. + REG_PARM_STACK_SPACE is the number of bytes of stack space reserved + for arguments which are passed in registers. + FNDECL is the function in which the argument was defined. There are two types of rounding that are done. The first, controlled by @@ -3713,19 +3713,16 @@ gimplify_parameters (void) void locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs, - int partial, tree fndecl ATTRIBUTE_UNUSED, + int reg_parm_stack_space, int partial, + tree fndecl ATTRIBUTE_UNUSED, struct args_size *initial_offset_ptr, struct locate_and_pad_arg_data *locate) { tree sizetree; enum direction where_pad; unsigned int boundary, round_boundary; - int reg_parm_stack_space = 0; int part_size_in_regs; -#ifdef REG_PARM_STACK_SPACE - reg_parm_stack_space = REG_PARM_STACK_SPACE (fndecl); - /* If we have found a stack parm before we reach the end of the area reserved for registers, skip that area. */ if (! in_regs) @@ -3743,7 +3740,6 @@ locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs, initial_offset_ptr->constant = reg_parm_stack_space; } } -#endif /* REG_PARM_STACK_SPACE */ part_size_in_regs = (reg_parm_stack_space == 0 ? partial : 0); @@ -3806,11 +3802,7 @@ locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs, locate->slot_offset.constant += part_size_in_regs; - if (!in_regs -#ifdef REG_PARM_STACK_SPACE - || REG_PARM_STACK_SPACE (fndecl) > 0 -#endif - ) + if (!in_regs || reg_parm_stack_space > 0) pad_to_arg_alignment (&locate->slot_offset, boundary, &locate->alignment_pad); @@ -3830,11 +3822,7 @@ locate_and_pad_parm (enum machine_mode passed_mode, tree type, int in_regs, pad_below (&locate->offset, passed_mode, sizetree); #else /* !ARGS_GROW_DOWNWARD */ - if (!in_regs -#ifdef REG_PARM_STACK_SPACE - || REG_PARM_STACK_SPACE (fndecl) > 0 -#endif - ) + if (!in_regs || reg_parm_stack_space > 0) pad_to_arg_alignment (initial_offset_ptr, boundary, &locate->alignment_pad); locate->slot_offset = *initial_offset_ptr; @@ -5093,6 +5081,7 @@ expand_function_end (void) amount. BLKmode results are handled using the group load/store machinery. */ if (TYPE_MODE (TREE_TYPE (decl_result)) != BLKmode + && REG_P (real_decl_rtl) && targetm.calls.return_in_msb (TREE_TYPE (decl_result))) { emit_move_insn (gen_rtx_REG (GET_MODE (decl_rtl), @@ -5509,9 +5498,12 @@ move_insn_for_shrink_wrap (basic_block bb, rtx insn, except for any part that overlaps SRC (next loop). */ bb_uses = &DF_LR_BB_INFO (bb)->use; bb_defs = &DF_LR_BB_INFO (bb)->def; + if (df_live) + { for (i = dregno; i < end_dregno; i++) { - if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i)) + if (REGNO_REG_SET_P (bb_uses, i) || REGNO_REG_SET_P (bb_defs, i) + || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i)) next_block = NULL; CLEAR_REGNO_REG_SET (live_out, i); CLEAR_REGNO_REG_SET (live_in, i); @@ -5521,11 +5513,31 @@ move_insn_for_shrink_wrap (basic_block bb, rtx insn, Either way, SRC is now live on entry. */ for (i = sregno; i < end_sregno; i++) { - if (REGNO_REG_SET_P (bb_defs, i)) + if (REGNO_REG_SET_P (bb_defs, i) + || REGNO_REG_SET_P (&DF_LIVE_BB_INFO (bb)->gen, i)) next_block = NULL; SET_REGNO_REG_SET (live_out, i); SET_REGNO_REG_SET (live_in, i); } + } + else + { + /* DF_LR_BB_INFO (bb)->def does not comprise the DF_REF_PARTIAL and + DF_REF_CONDITIONAL defs. So if DF_LIVE doesn't exist, i.e. + at -O1, just give up searching NEXT_BLOCK. */ + next_block = NULL; + for (i = dregno; i < end_dregno; i++) + { + CLEAR_REGNO_REG_SET (live_out, i); + CLEAR_REGNO_REG_SET (live_in, i); + } + + for (i = sregno; i < end_sregno; i++) + { + SET_REGNO_REG_SET (live_out, i); + SET_REGNO_REG_SET (live_in, i); + } + } /* If we don't need to add the move to BB, look for a single successor block. */ diff --git a/gcc-4.8/gcc/gcc.c b/gcc-4.8/gcc/gcc.c index e16f72ec5..ac5032a98 100644 --- a/gcc-4.8/gcc/gcc.c +++ b/gcc-4.8/gcc/gcc.c @@ -5441,7 +5441,7 @@ eval_spec_function (const char *func, const char *args) const char *save_suffix_subst; int save_growing_size; - void *save_growing_value; + void *save_growing_value = NULL; sf = lookup_spec_function (func); if (sf == NULL) diff --git a/gcc-4.8/gcc/gengtype-lex.c b/gcc-4.8/gcc/gengtype-lex.c index 36da3a32d..7ad0b2500 100644 --- a/gcc-4.8/gcc/gengtype-lex.c +++ b/gcc-4.8/gcc/gengtype-lex.c @@ -1173,7 +1173,7 @@ int yy_flex_debug = 0; #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; -#line 1 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 1 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* -*- indented-text -*- */ /* Process source files and output type information. Copyright (C) 2002-2013 Free Software Foundation, Inc. @@ -1194,7 +1194,7 @@ You should have received a copy of the GNU General Public License along with GCC; see the file COPYING3. If not see . */ #define YY_NO_INPUT 1 -#line 24 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 24 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" #ifdef GENERATOR_FILE #include "bconfig.h" #else @@ -1313,7 +1313,7 @@ static int input (void ); /* This used to be an fputs(), but since the string might contain NUL's, * we now use fwrite(). */ -#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0) +#define ECHO fwrite( yytext, yyleng, 1, yyout ) #endif /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL, @@ -1324,7 +1324,7 @@ static int input (void ); if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \ { \ int c = '*'; \ - unsigned n; \ + int n; \ for ( n = 0; n < max_size && \ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \ buf[n] = (char) c; \ @@ -1409,7 +1409,7 @@ YY_DECL register char *yy_cp, *yy_bp; register int yy_act; -#line 65 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 65 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* Do this on entry to yylex(): */ *yylval = 0; @@ -1506,7 +1506,7 @@ case 1: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 76 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 76 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); return TYPEDEF; @@ -1518,7 +1518,7 @@ case 2: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 80 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 80 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); return STRUCT; @@ -1530,7 +1530,7 @@ case 3: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 84 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 84 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); return UNION; @@ -1542,7 +1542,7 @@ case 4: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 88 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 88 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); return STRUCT; @@ -1554,7 +1554,7 @@ case 5: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 92 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 92 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); return EXTERN; @@ -1566,7 +1566,7 @@ case 6: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 96 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 96 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); return STATIC; @@ -1577,25 +1577,25 @@ YY_RULE_SETUP case 7: YY_RULE_SETUP -#line 104 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 104 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct_comment); } YY_BREAK case 8: /* rule 8 can match eol */ YY_RULE_SETUP -#line 105 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 105 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 9: /* rule 9 can match eol */ YY_RULE_SETUP -#line 107 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 107 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { update_lineno (yytext, yyleng); } YY_BREAK case 10: /* rule 10 can match eol */ YY_RULE_SETUP -#line 108 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 108 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 11: @@ -1604,7 +1604,7 @@ case 11: (yy_c_buf_p) = yy_cp = yy_bp + 5; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 110 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 110 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* don't care */ YY_BREAK case 12: @@ -1612,14 +1612,14 @@ case 12: *yy_cp = (yy_hold_char); /* undo effects of setting up yytext */ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ -#line 112 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 112 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 13: /* rule 13 can match eol */ -#line 113 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 113 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 14: /* rule 14 can match eol */ YY_RULE_SETUP -#line 113 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 113 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext, yyleng, yyleng + 1); return IGNORABLE_CXX_KEYWORD; @@ -1631,7 +1631,7 @@ case 15: (yy_c_buf_p) = yy_cp = yy_bp + 3; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 117 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 117 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return GTY_TOKEN; } YY_BREAK case 16: @@ -1640,7 +1640,7 @@ case 16: (yy_c_buf_p) = yy_cp = yy_bp + 5; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 118 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 118 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return UNION; } YY_BREAK case 17: @@ -1649,7 +1649,7 @@ case 17: (yy_c_buf_p) = yy_cp = yy_bp + 6; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 119 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 119 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return STRUCT; } YY_BREAK case 18: @@ -1658,7 +1658,7 @@ case 18: (yy_c_buf_p) = yy_cp = yy_bp + 5; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 120 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 120 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return STRUCT; } YY_BREAK case 19: @@ -1667,7 +1667,7 @@ case 19: (yy_c_buf_p) = yy_cp = yy_bp + 7; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 121 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 121 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return TYPEDEF; } YY_BREAK case 20: @@ -1676,7 +1676,7 @@ case 20: (yy_c_buf_p) = yy_cp = yy_bp + 4; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 122 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 122 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return ENUM; } YY_BREAK case 21: @@ -1685,7 +1685,7 @@ case 21: (yy_c_buf_p) = yy_cp = yy_bp + 9; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 123 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 123 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return PTR_ALIAS; } YY_BREAK case 22: @@ -1694,7 +1694,7 @@ case 22: (yy_c_buf_p) = yy_cp = yy_bp + 10; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 124 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 124 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return NESTED_PTR; } YY_BREAK case 23: @@ -1703,12 +1703,12 @@ case 23: (yy_c_buf_p) = yy_cp = yy_bp + 4; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 125 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 125 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return USER_GTY; } YY_BREAK case 24: YY_RULE_SETUP -#line 126 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 126 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return NUM; } YY_BREAK case 25: @@ -1717,7 +1717,7 @@ case 25: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 127 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 127 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1); return PARAM_IS; @@ -1728,11 +1728,11 @@ case 26: *yy_cp = (yy_hold_char); /* undo effects of setting up yytext */ (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ -#line 133 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 133 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 27: /* rule 27 can match eol */ YY_RULE_SETUP -#line 133 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 133 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { size_t len; @@ -1750,7 +1750,7 @@ case 28: (yy_c_buf_p) = yy_cp -= 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 144 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 144 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext, yyleng, yyleng+1); return ID; @@ -1759,7 +1759,7 @@ YY_RULE_SETUP case 29: /* rule 29 can match eol */ YY_RULE_SETUP -#line 149 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 149 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1); return STRING; @@ -1769,7 +1769,7 @@ YY_RULE_SETUP case 30: /* rule 30 can match eol */ YY_RULE_SETUP -#line 154 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 154 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng-1); return ARRAY; @@ -1778,7 +1778,7 @@ YY_RULE_SETUP case 31: /* rule 31 can match eol */ YY_RULE_SETUP -#line 158 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 158 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { *yylval = XDUPVAR (const char, yytext+1, yyleng-2, yyleng); return CHAR; @@ -1786,24 +1786,24 @@ YY_RULE_SETUP YY_BREAK case 32: YY_RULE_SETUP -#line 163 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 163 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return ELLIPSIS; } YY_BREAK case 33: YY_RULE_SETUP -#line 164 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 164 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { return yytext[0]; } YY_BREAK /* ignore pp-directives */ case 34: /* rule 34 can match eol */ YY_RULE_SETUP -#line 167 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 167 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" {lexer_line.line++;} YY_BREAK case 35: YY_RULE_SETUP -#line 169 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 169 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { error_at_line (&lexer_line, "unexpected character `%s'", yytext); } @@ -1811,36 +1811,36 @@ YY_RULE_SETUP case 36: YY_RULE_SETUP -#line 174 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 174 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_comment); } YY_BREAK case 37: /* rule 37 can match eol */ YY_RULE_SETUP -#line 175 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 175 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 38: /* rule 38 can match eol */ YY_RULE_SETUP -#line 176 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 176 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 39: -#line 178 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 178 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 40: /* rule 40 can match eol */ -#line 179 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 179 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 41: /* rule 41 can match eol */ YY_RULE_SETUP -#line 179 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 179 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 42: /* rule 42 can match eol */ YY_RULE_SETUP -#line 180 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 180 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { update_lineno (yytext, yyleng); } YY_BREAK case 43: @@ -1849,21 +1849,21 @@ case 43: (yy_c_buf_p) = yy_cp = yy_bp + 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 181 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 181 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 44: /* rule 44 can match eol */ YY_RULE_SETUP -#line 184 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 184 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { lexer_line.line++; } YY_BREAK case 45: -#line 186 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 186 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 46: YY_RULE_SETUP -#line 186 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 186 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 47: @@ -1872,25 +1872,25 @@ case 47: (yy_c_buf_p) = yy_cp = yy_bp + 1; YY_DO_BEFORE_ACTION; /* set up yytext again */ YY_RULE_SETUP -#line 187 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 187 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 48: YY_RULE_SETUP -#line 190 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 190 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(INITIAL); } YY_BREAK case 49: YY_RULE_SETUP -#line 191 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 191 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { BEGIN(in_struct); } YY_BREAK case 50: -#line 194 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 194 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" case 51: YY_RULE_SETUP -#line 194 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 194 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" { error_at_line (&lexer_line, "unterminated comment or string; unexpected EOF"); @@ -1899,12 +1899,12 @@ YY_RULE_SETUP case 52: /* rule 52 can match eol */ YY_RULE_SETUP -#line 199 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 199 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" /* do nothing */ YY_BREAK case 53: YY_RULE_SETUP -#line 201 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 201 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" YY_FATAL_ERROR( "flex scanner jammed" ); YY_BREAK #line 1910 "gengtype-lex.c" @@ -2238,7 +2238,7 @@ static int yy_get_next_buffer (void) yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; yy_is_jam = (yy_current_state == 557); - return yy_is_jam ? 0 : yy_current_state; + return yy_is_jam ? 0 : yy_current_state; } #ifndef YY_NO_INPUT @@ -2871,7 +2871,7 @@ void yyfree (void * ptr ) #define YYTABLES_NAME "yytables" -#line 201 "/d/gcc-4.8.1/gcc-4.8.1/gcc/gengtype-lex.l" +#line 201 "/space/rguenther/gcc-4.8.3/gcc-4.8.3/gcc/gengtype-lex.l" diff --git a/gcc-4.8/gcc/gimple-fold.c b/gcc-4.8/gcc/gimple-fold.c index b9211a9ad..5d08169b8 100644 --- a/gcc-4.8/gcc/gimple-fold.c +++ b/gcc-4.8/gcc/gimple-fold.c @@ -178,7 +178,7 @@ canonicalize_constructor_val (tree cval, tree from_decl) /* Make sure we create a cgraph node for functions we'll reference. They can be non-existent if the reference comes from an entry of an external vtable for example. */ - cgraph_get_create_node (base); + cgraph_get_create_real_symbol_node (base); } /* Fixup types in global initializers. */ if (TREE_TYPE (TREE_TYPE (cval)) != TREE_TYPE (TREE_OPERAND (cval, 0))) @@ -866,6 +866,7 @@ gimple_fold_builtin (gimple stmt) break; case BUILT_IN_STRCPY: case BUILT_IN_STRNCPY: + case BUILT_IN_STRCAT: arg_idx = 1; type = 0; break; @@ -941,6 +942,13 @@ gimple_fold_builtin (gimple stmt) val[1]); break; + case BUILT_IN_STRCAT: + if (val[1] && is_gimple_val (val[1]) && nargs == 2) + result = fold_builtin_strcat (loc, gimple_call_arg (stmt, 0), + gimple_call_arg (stmt, 1), + val[1]); + break; + case BUILT_IN_FPUTS: if (nargs == 2) result = fold_builtin_fputs (loc, gimple_call_arg (stmt, 0), diff --git a/gcc-4.8/gcc/gimple-low.c b/gcc-4.8/gcc/gimple-low.c index b06d194da..9ac0d60e5 100644 --- a/gcc-4.8/gcc/gimple-low.c +++ b/gcc-4.8/gcc/gimple-low.c @@ -238,6 +238,7 @@ gimple_check_call_args (gimple stmt, tree fndecl) break; arg = gimple_call_arg (stmt, i); if (p == error_mark_node + || DECL_ARG_TYPE (p) == error_mark_node || arg == error_mark_node || (!types_compatible_p (DECL_ARG_TYPE (p), TREE_TYPE (arg)) && !fold_convertible_p (DECL_ARG_TYPE (p), arg))) diff --git a/gcc-4.8/gcc/gimple-ssa-strength-reduction.c b/gcc-4.8/gcc/gimple-ssa-strength-reduction.c index 5cda3873e..a1d1a11f0 100644 --- a/gcc-4.8/gcc/gimple-ssa-strength-reduction.c +++ b/gcc-4.8/gcc/gimple-ssa-strength-reduction.c @@ -735,16 +735,19 @@ create_mul_imm_cand (gimple gs, tree base_in, tree stride_in, bool speed) X = Y * c ============================ X = (B + i') * (S * c) */ - base = base_cand->base_expr; - index = base_cand->index; temp = tree_to_double_int (base_cand->stride) * tree_to_double_int (stride_in); + if (double_int_fits_to_tree_p (TREE_TYPE (stride_in), temp)) + { + base = base_cand->base_expr; + index = base_cand->index; stride = double_int_to_tree (TREE_TYPE (stride_in), temp); ctype = base_cand->cand_type; if (has_single_use (base_in)) savings = (base_cand->dead_savings + stmt_cost (base_cand->cand_stmt, speed)); } + } else if (base_cand->kind == CAND_ADD && operand_equal_p (base_cand->stride, integer_one_node, 0)) { diff --git a/gcc-4.8/gcc/gimple.c b/gcc-4.8/gcc/gimple.c index 97a37e32d..9b5de4a25 100644 --- a/gcc-4.8/gcc/gimple.c +++ b/gcc-4.8/gcc/gimple.c @@ -3841,42 +3841,46 @@ get_base_loadstore (tree op) /* For the statement STMT call the callbacks VISIT_LOAD, VISIT_STORE and VISIT_ADDR if non-NULL on loads, store and address-taken operands - passing the STMT, the base of the operand and DATA to it. The base - will be either a decl, an indirect reference (including TARGET_MEM_REF) - or the argument of an address expression. + passing the STMT, the base of the operand, the operand itself containing + the base and DATA to it. The base will be either a decl, an indirect + reference (including TARGET_MEM_REF) or the argument of an address + expression. Returns the results of these callbacks or'ed. */ bool walk_stmt_load_store_addr_ops (gimple stmt, void *data, - bool (*visit_load)(gimple, tree, void *), - bool (*visit_store)(gimple, tree, void *), - bool (*visit_addr)(gimple, tree, void *)) + walk_stmt_load_store_addr_fn visit_load, + walk_stmt_load_store_addr_fn visit_store, + walk_stmt_load_store_addr_fn visit_addr) { bool ret = false; unsigned i; if (gimple_assign_single_p (stmt)) { - tree lhs, rhs; + tree lhs, rhs, arg; if (visit_store) { - lhs = get_base_loadstore (gimple_assign_lhs (stmt)); + arg = gimple_assign_lhs (stmt); + lhs = get_base_loadstore (arg); if (lhs) - ret |= visit_store (stmt, lhs, data); + ret |= visit_store (stmt, lhs, arg, data); } - rhs = gimple_assign_rhs1 (stmt); + arg = gimple_assign_rhs1 (stmt); + rhs = arg; while (handled_component_p (rhs)) rhs = TREE_OPERAND (rhs, 0); if (visit_addr) { if (TREE_CODE (rhs) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), arg, data); else if (TREE_CODE (rhs) == TARGET_MEM_REF && TREE_CODE (TMR_BASE (rhs)) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (rhs), 0), arg, + data); else if (TREE_CODE (rhs) == OBJ_TYPE_REF && TREE_CODE (OBJ_TYPE_REF_OBJECT (rhs)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (rhs), - 0), data); + 0), arg, data); else if (TREE_CODE (rhs) == CONSTRUCTOR) { unsigned int ix; @@ -3884,23 +3888,23 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (rhs), ix, val) if (TREE_CODE (val) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (val, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (val, 0), arg, data); else if (TREE_CODE (val) == OBJ_TYPE_REF && TREE_CODE (OBJ_TYPE_REF_OBJECT (val)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (OBJ_TYPE_REF_OBJECT (val), - 0), data); + 0), arg, data); } lhs = gimple_assign_lhs (stmt); if (TREE_CODE (lhs) == TARGET_MEM_REF && TREE_CODE (TMR_BASE (lhs)) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (TMR_BASE (lhs), 0), lhs, data); } if (visit_load) { rhs = get_base_loadstore (rhs); if (rhs) - ret |= visit_load (stmt, rhs, data); + ret |= visit_load (stmt, rhs, arg, data); } } else if (visit_addr @@ -3913,17 +3917,17 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, if (op == NULL_TREE) ; else if (TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); /* COND_EXPR and VCOND_EXPR rhs1 argument is a comparison tree with two operands. */ else if (i == 1 && COMPARISON_CLASS_P (op)) { if (TREE_CODE (TREE_OPERAND (op, 0)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 0), - 0), data); + 0), op, data); if (TREE_CODE (TREE_OPERAND (op, 1)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (TREE_OPERAND (op, 1), - 0), data); + 0), op, data); } } } @@ -3931,38 +3935,39 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { if (visit_store) { - tree lhs = gimple_call_lhs (stmt); - if (lhs) + tree arg = gimple_call_lhs (stmt); + if (arg) { - lhs = get_base_loadstore (lhs); + tree lhs = get_base_loadstore (arg); if (lhs) - ret |= visit_store (stmt, lhs, data); + ret |= visit_store (stmt, lhs, arg, data); } } if (visit_load || visit_addr) for (i = 0; i < gimple_call_num_args (stmt); ++i) { - tree rhs = gimple_call_arg (stmt, i); + tree arg = gimple_call_arg (stmt, i); if (visit_addr - && TREE_CODE (rhs) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (rhs, 0), data); + && TREE_CODE (arg) == ADDR_EXPR) + ret |= visit_addr (stmt, TREE_OPERAND (arg, 0), arg, data); else if (visit_load) { - rhs = get_base_loadstore (rhs); + tree rhs = get_base_loadstore (arg); if (rhs) - ret |= visit_load (stmt, rhs, data); + ret |= visit_load (stmt, rhs, arg, data); } } if (visit_addr && gimple_call_chain (stmt) && TREE_CODE (gimple_call_chain (stmt)) == ADDR_EXPR) ret |= visit_addr (stmt, TREE_OPERAND (gimple_call_chain (stmt), 0), - data); + gimple_call_chain (stmt), data); if (visit_addr && gimple_call_return_slot_opt_p (stmt) && gimple_call_lhs (stmt) != NULL_TREE && TREE_ADDRESSABLE (TREE_TYPE (gimple_call_lhs (stmt)))) - ret |= visit_addr (stmt, gimple_call_lhs (stmt), data); + ret |= visit_addr (stmt, gimple_call_lhs (stmt), + gimple_call_lhs (stmt), data); } else if (gimple_code (stmt) == GIMPLE_ASM) { @@ -3978,7 +3983,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, tree link = gimple_asm_output_op (stmt, i); tree op = get_base_loadstore (TREE_VALUE (link)); if (op && visit_store) - ret |= visit_store (stmt, op, data); + ret |= visit_store (stmt, op, TREE_VALUE (link), data); if (visit_addr) { constraint = TREE_STRING_POINTER @@ -3987,7 +3992,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, parse_output_constraint (&constraint, i, 0, 0, &allows_mem, &allows_reg, &is_inout); if (op && !allows_reg && allows_mem) - ret |= visit_addr (stmt, op, data); + ret |= visit_addr (stmt, op, TREE_VALUE (link), data); } } if (visit_load || visit_addr) @@ -3997,14 +4002,14 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, tree op = TREE_VALUE (link); if (visit_addr && TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); else if (visit_load || visit_addr) { op = get_base_loadstore (op); if (op) { if (visit_load) - ret |= visit_load (stmt, op, data); + ret |= visit_load (stmt, op, TREE_VALUE (link), data); if (visit_addr) { constraint = TREE_STRING_POINTER @@ -4013,7 +4018,8 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, 0, oconstraints, &allows_mem, &allows_reg); if (!allows_reg && allows_mem) - ret |= visit_addr (stmt, op, data); + ret |= visit_addr (stmt, op, TREE_VALUE (link), + data); } } } @@ -4026,12 +4032,12 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { if (visit_addr && TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); else if (visit_load) { - op = get_base_loadstore (op); - if (op) - ret |= visit_load (stmt, op, data); + tree base = get_base_loadstore (op); + if (base) + ret |= visit_load (stmt, base, op, data); } } } @@ -4042,7 +4048,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { tree op = PHI_ARG_DEF (stmt, i); if (TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); } } else if (visit_addr @@ -4050,7 +4056,7 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, { tree op = gimple_goto_dest (stmt); if (TREE_CODE (op) == ADDR_EXPR) - ret |= visit_addr (stmt, TREE_OPERAND (op, 0), data); + ret |= visit_addr (stmt, TREE_OPERAND (op, 0), op, data); } return ret; @@ -4061,8 +4067,8 @@ walk_stmt_load_store_addr_ops (gimple stmt, void *data, bool walk_stmt_load_store_ops (gimple stmt, void *data, - bool (*visit_load)(gimple, tree, void *), - bool (*visit_store)(gimple, tree, void *)) + walk_stmt_load_store_addr_fn visit_load, + walk_stmt_load_store_addr_fn visit_store) { return walk_stmt_load_store_addr_ops (stmt, data, visit_load, visit_store, NULL); @@ -4071,8 +4077,7 @@ walk_stmt_load_store_ops (gimple stmt, void *data, /* Helper for gimple_ior_addresses_taken_1. */ static bool -gimple_ior_addresses_taken_1 (gimple stmt ATTRIBUTE_UNUSED, - tree addr, void *data) +gimple_ior_addresses_taken_1 (gimple, tree addr, tree, void *data) { bitmap addresses_taken = (bitmap)data; addr = get_base_address (addr); diff --git a/gcc-4.8/gcc/gimple.h b/gcc-4.8/gcc/gimple.h index 1bbd7d76a..4985446cc 100644 --- a/gcc-4.8/gcc/gimple.h +++ b/gcc-4.8/gcc/gimple.h @@ -176,6 +176,9 @@ struct GTY((chain_next ("%h.next"))) gimple_statement_base { /* Nonzero if this statement contains volatile operands. */ unsigned has_volatile_ops : 1; + /* Padding to get subcode to 16 bit alignment. */ + unsigned pad : 1; + /* The SUBCODE field can be used for tuple-specific flags for tuples that do not require subcodes. Note that SUBCODE should be at least as wide as tree codes, as several tuples store tree codes @@ -888,13 +891,14 @@ extern tree gimple_signed_type (tree); extern alias_set_type gimple_get_alias_set (tree); extern void count_uses_and_derefs (tree, gimple, unsigned *, unsigned *, unsigned *); +typedef bool (*walk_stmt_load_store_addr_fn) (gimple, tree, tree, void *); extern bool walk_stmt_load_store_addr_ops (gimple, void *, - bool (*)(gimple, tree, void *), - bool (*)(gimple, tree, void *), - bool (*)(gimple, tree, void *)); + walk_stmt_load_store_addr_fn, + walk_stmt_load_store_addr_fn, + walk_stmt_load_store_addr_fn); extern bool walk_stmt_load_store_ops (gimple, void *, - bool (*)(gimple, tree, void *), - bool (*)(gimple, tree, void *)); + walk_stmt_load_store_addr_fn, + walk_stmt_load_store_addr_fn); extern bool gimple_ior_addresses_taken (bitmap, gimple); extern bool gimple_call_builtin_p (gimple, enum built_in_class); extern bool gimple_call_builtin_p (gimple, enum built_in_function); diff --git a/gcc-4.8/gcc/gimplify.c b/gcc-4.8/gcc/gimplify.c index 9416963c4..f69739527 100644 --- a/gcc-4.8/gcc/gimplify.c +++ b/gcc-4.8/gcc/gimplify.c @@ -2060,6 +2060,9 @@ gimplify_conversion (tree *expr_p) /* Nonlocal VLAs seen in the current function. */ static struct pointer_set_t *nonlocal_vlas; +/* The VAR_DECLs created for nonlocal VLAs for debug info purposes. */ +static tree nonlocal_vla_vars; + /* Gimplify a VAR_DECL or PARM_DECL. Return GS_OK if we expanded a DECL_VALUE_EXPR, and it's worth re-examining things. */ @@ -2106,14 +2109,13 @@ gimplify_var_or_parm_decl (tree *expr_p) ctx = ctx->outer_context; if (!ctx && !pointer_set_insert (nonlocal_vlas, decl)) { - tree copy = copy_node (decl), block; + tree copy = copy_node (decl); lang_hooks.dup_lang_specific_decl (copy); SET_DECL_RTL (copy, 0); TREE_USED (copy) = 1; - block = DECL_INITIAL (current_function_decl); - DECL_CHAIN (copy) = BLOCK_VARS (block); - BLOCK_VARS (block) = copy; + DECL_CHAIN (copy) = nonlocal_vla_vars; + nonlocal_vla_vars = copy; SET_DECL_VALUE_EXPR (copy, unshare_expr (value_expr)); DECL_HAS_VALUE_EXPR_P (copy) = 1; } @@ -4378,7 +4380,7 @@ gimple_fold_indirect_ref (tree t) unsigned HOST_WIDE_INT indexi = offset * BITS_PER_UNIT; tree index = bitsize_int (indexi); if (offset / part_widthi - <= TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype))) + < TYPE_VECTOR_SUBPARTS (TREE_TYPE (addrtype))) return fold_build3 (BIT_FIELD_REF, type, TREE_OPERAND (addr, 0), part_width, index); } @@ -6140,7 +6142,7 @@ omp_is_private (struct gimplify_omp_ctx *ctx, tree decl) region's REDUCTION clause. */ static bool -omp_check_private (struct gimplify_omp_ctx *ctx, tree decl) +omp_check_private (struct gimplify_omp_ctx *ctx, tree decl, bool copyprivate) { splay_tree_node n; @@ -6149,8 +6151,11 @@ omp_check_private (struct gimplify_omp_ctx *ctx, tree decl) ctx = ctx->outer_context; if (ctx == NULL) return !(is_global_var (decl) - /* References might be private, but might be shared too. */ - || lang_hooks.decls.omp_privatize_by_reference (decl)); + /* References might be private, but might be shared too, + when checking for copyprivate, assume they might be + private, otherwise assume they might be shared. */ + || (!copyprivate + && lang_hooks.decls.omp_privatize_by_reference (decl))); n = splay_tree_lookup (ctx->variables, (splay_tree_key) decl); if (n != NULL) @@ -6276,12 +6281,36 @@ gimplify_scan_omp_clauses (tree *list_p, gimple_seq *pre_p, remove = true; break; } + if (OMP_CLAUSE_CODE (c) == OMP_CLAUSE_COPYPRIVATE + && !remove + && !omp_check_private (ctx, decl, true)) + { + remove = true; + if (is_global_var (decl)) + { + if (DECL_THREAD_LOCAL_P (decl)) + remove = false; + else if (DECL_HAS_VALUE_EXPR_P (decl)) + { + tree value = get_base_address (DECL_VALUE_EXPR (decl)); + + if (value + && DECL_P (value) + && DECL_THREAD_LOCAL_P (value)) + remove = false; + } + } + if (remove) + error_at (OMP_CLAUSE_LOCATION (c), + "copyprivate variable %qE is not threadprivate" + " or private in outer context", DECL_NAME (decl)); + } do_notice: if (outer_ctx) omp_notice_variable (outer_ctx, decl, true); if (check_non_private && region_type == ORT_WORKSHARE - && omp_check_private (ctx, decl)) + && omp_check_private (ctx, decl, false)) { error ("%s variable %qE is private in outer context", check_non_private, DECL_NAME (decl)); @@ -8270,6 +8299,21 @@ gimplify_body (tree fndecl, bool do_parms) if (nonlocal_vlas) { + if (nonlocal_vla_vars) + { + /* tree-nested.c may later on call declare_vars (..., true); + which relies on BLOCK_VARS chain to be the tail of the + gimple_bind_vars chain. Ensure we don't violate that + assumption. */ + if (gimple_bind_block (outer_bind) + == DECL_INITIAL (current_function_decl)) + declare_vars (nonlocal_vla_vars, outer_bind, true); + else + BLOCK_VARS (DECL_INITIAL (current_function_decl)) + = chainon (BLOCK_VARS (DECL_INITIAL (current_function_decl)), + nonlocal_vla_vars); + nonlocal_vla_vars = NULL_TREE; + } pointer_set_destroy (nonlocal_vlas); nonlocal_vlas = NULL; } @@ -8597,6 +8641,8 @@ gimple_regimplify_operands (gimple stmt, gimple_stmt_iterator *gsi_p) gsi_insert_after (gsi_p, post_stmt, GSI_NEW_STMT); pop_gimplify_context (NULL); + + update_stmt (stmt); } /* Expand EXPR to list of gimple statements STMTS. GIMPLE_TEST_F specifies diff --git a/gcc-4.8/gcc/go/ChangeLog b/gcc-4.8/gcc/go/ChangeLog index 6c1504db5..e5860d7ff 100644 --- a/gcc-4.8/gcc/go/ChangeLog +++ b/gcc-4.8/gcc/go/ChangeLog @@ -1,3 +1,26 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2013-12-11 Ian Lance Taylor + + * go-lang.c (go_langhook_post_options): Disable sibling calls by + default. + +2013-10-16 Ian Lance Taylor + + Bring in from mainline: + + 2013-10-11 Chris Manghane + * go-gcc.cc (Gcc_backend::function_code_expression): New + function. + + 2013-10-10 Chris Manghane + * go-gcc.cc (Backend::error_function): New function. + (Backend::function): New function. + (Backend::make_function): New function. + (function_to_tree): New function. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/go/go-gcc.cc b/gcc-4.8/gcc/go/go-gcc.cc index fcfd41b34..81e9ad186 100644 --- a/gcc-4.8/gcc/go/go-gcc.cc +++ b/gcc-4.8/gcc/go/go-gcc.cc @@ -232,6 +232,9 @@ class Gcc_backend : public Backend Bexpression* convert_expression(Btype* type, Bexpression* expr, Location); + Bexpression* + function_code_expression(Bfunction*, Location); + // Statements. Bstatement* @@ -334,6 +337,17 @@ class Gcc_backend : public Backend Bexpression* label_address(Blabel*, Location); + // Functions. + + Bfunction* + error_function() + { return this->make_function(error_mark_node); } + + Bfunction* + function(Btype* fntype, const std::string& name, const std::string& asm_name, + bool is_visible, bool is_declaration, bool is_inlinable, + bool disable_split_stack, bool in_unique_section, Location); + private: // Make a Bexpression from a tree. Bexpression* @@ -350,6 +364,10 @@ class Gcc_backend : public Backend make_type(tree t) { return new Btype(t); } + Bfunction* + make_function(tree t) + { return new Bfunction(t); } + Btype* fill_in_struct(Btype*, const std::vector&); @@ -966,6 +984,19 @@ Gcc_backend::convert_expression(Btype* type, Bexpression* expr, Location) return tree_to_expr(ret); } +// Get the address of a function. + +Bexpression* +Gcc_backend::function_code_expression(Bfunction* bfunc, Location location) +{ + tree func = bfunc->get_tree(); + if (func == error_mark_node) + return this->error_expression(); + + tree ret = build_fold_addr_expr_loc(location.gcc_location(), func); + return this->make_expression(ret); +} + // An expression as a statement. Bstatement* @@ -1724,6 +1755,56 @@ Gcc_backend::label_address(Blabel* label, Location location) return this->make_expression(ret); } +// Declare or define a new function. + +Bfunction* +Gcc_backend::function(Btype* fntype, const std::string& name, + const std::string& asm_name, bool is_visible, + bool is_declaration, bool is_inlinable, + bool disable_split_stack, bool in_unique_section, + Location location) +{ + tree functype = fntype->get_tree(); + if (functype != error_mark_node) + { + gcc_assert(FUNCTION_POINTER_TYPE_P(functype)); + functype = TREE_TYPE(functype); + } + tree id = get_identifier_from_string(name); + if (functype == error_mark_node || id == error_mark_node) + return this->error_function(); + + tree decl = build_decl(location.gcc_location(), FUNCTION_DECL, id, functype); + if (!asm_name.empty()) + SET_DECL_ASSEMBLER_NAME(decl, get_identifier_from_string(asm_name)); + if (is_visible) + TREE_PUBLIC(decl) = 1; + if (is_declaration) + DECL_EXTERNAL(decl) = 1; + else + { + tree restype = TREE_TYPE(functype); + tree resdecl = + build_decl(location.gcc_location(), RESULT_DECL, NULL_TREE, restype); + DECL_ARTIFICIAL(resdecl) = 1; + DECL_IGNORED_P(resdecl) = 1; + DECL_CONTEXT(resdecl) = decl; + DECL_RESULT(decl) = resdecl; + } + if (!is_inlinable) + DECL_UNINLINABLE(decl) = 1; + if (disable_split_stack) + { + tree attr = get_identifier("__no_split_stack__"); + DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE); + } + if (in_unique_section) + resolve_unique_section(decl, 0, 1); + + go_preserve_from_gc(decl); + return new Bfunction(decl); +} + // The single backend. static Gcc_backend gcc_backend; @@ -1799,3 +1880,9 @@ var_to_tree(Bvariable* bv) { return bv->get_tree(); } + +tree +function_to_tree(Bfunction* bf) +{ + return bf->get_tree(); +} diff --git a/gcc-4.8/gcc/go/go-lang.c b/gcc-4.8/gcc/go/go-lang.c index 659cd8ef7..7e92deb92 100644 --- a/gcc-4.8/gcc/go/go-lang.c +++ b/gcc-4.8/gcc/go/go-lang.c @@ -269,6 +269,10 @@ go_langhook_post_options (const char **pfilename ATTRIBUTE_UNUSED) if (flag_excess_precision_cmdline == EXCESS_PRECISION_DEFAULT) flag_excess_precision_cmdline = EXCESS_PRECISION_STANDARD; + /* Tail call optimizations can confuse uses of runtime.Callers. */ + if (!global_options_set.x_flag_optimize_sibling_calls) + global_options.x_flag_optimize_sibling_calls = 0; + /* Returning false means that the backend should be used. */ return false; } diff --git a/gcc-4.8/gcc/go/gofrontend/backend.h b/gcc-4.8/gcc/go/gofrontend/backend.h index fa3e3cc68..ca997f08a 100644 --- a/gcc-4.8/gcc/go/gofrontend/backend.h +++ b/gcc-4.8/gcc/go/gofrontend/backend.h @@ -23,7 +23,7 @@ class Bexpression; // The backend representation of a statement. class Bstatement; -// The backend representation of a function definition. +// The backend representation of a function definition or declaration. class Bfunction; // The backend representation of a block. @@ -266,6 +266,11 @@ class Backend virtual Bexpression* convert_expression(Btype* type, Bexpression* expr, Location) = 0; + // Create an expression for the address of a function. This is used to + // get the address of the code for a function. + virtual Bexpression* + function_code_expression(Bfunction*, Location) = 0; + // Statements. // Create an error statement. This is used for cases which should @@ -498,6 +503,32 @@ class Backend // recover. virtual Bexpression* label_address(Blabel*, Location) = 0; + + // Functions. + + // Create an error function. This is used for cases which should + // not occur in a correct program, in order to keep the compilation + // going without crashing. + virtual Bfunction* + error_function() = 0; + + // Declare or define a function of FNTYPE. + // NAME is the Go name of the function. ASM_NAME, if not the empty string, is + // the name that should be used in the symbol table; this will be non-empty if + // a magic extern comment is used. + // IS_VISIBLE is true if this function should be visible outside of the + // current compilation unit. IS_DECLARATION is true if this is a function + // declaration rather than a definition; the function definition will be in + // another compilation unit. + // IS_INLINABLE is true if the function can be inlined. + // DISABLE_SPLIT_STACK is true if this function may not split the stack; this + // is used for the implementation of recover. + // IN_UNIQUE_SECTION is true if this function should be put into a unique + // location if possible; this is used for field tracking. + virtual Bfunction* + function(Btype* fntype, const std::string& name, const std::string& asm_name, + bool is_visible, bool is_declaration, bool is_inlinable, + bool disable_split_stack, bool in_unique_section, Location) = 0; }; // The backend interface has to define this function. @@ -517,5 +548,6 @@ extern tree expr_to_tree(Bexpression*); extern tree stat_to_tree(Bstatement*); extern tree block_to_tree(Bblock*); extern tree var_to_tree(Bvariable*); +extern tree function_to_tree(Bfunction*); #endif // !defined(GO_BACKEND_H) diff --git a/gcc-4.8/gcc/go/gofrontend/expressions.cc b/gcc-4.8/gcc/go/gofrontend/expressions.cc index d5e3a6762..3e54084ff 100644 --- a/gcc-4.8/gcc/go/gofrontend/expressions.cc +++ b/gcc-4.8/gcc/go/gofrontend/expressions.cc @@ -1219,7 +1219,7 @@ Func_expression::do_type() // Get the tree for the code of a function expression. -tree +Bexpression* Func_expression::get_code_pointer(Gogo* gogo, Named_object* no, Location loc) { Function_type* fntype; @@ -1237,25 +1237,18 @@ Func_expression::get_code_pointer(Gogo* gogo, Named_object* no, Location loc) error_at(loc, "invalid use of special builtin function %qs; must be called", no->message_name().c_str()); - return error_mark_node; + return gogo->backend()->error_expression(); } - tree id = no->get_id(gogo); - if (id == error_mark_node) - return error_mark_node; - - tree fndecl; + Bfunction* fndecl; if (no->is_function()) - fndecl = no->func_value()->get_or_make_decl(gogo, no, id); + fndecl = no->func_value()->get_or_make_decl(gogo, no); else if (no->is_function_declaration()) - fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no, id); + fndecl = no->func_declaration_value()->get_or_make_decl(gogo, no); else go_unreachable(); - if (fndecl == error_mark_node) - return error_mark_node; - - return build_fold_addr_expr_loc(loc.gcc_location(), fndecl); + return gogo->backend()->function_code_expression(fndecl, loc); } // Get the tree for a function expression. This is used when we take @@ -1492,8 +1485,10 @@ class Func_code_reference_expression : public Expression tree Func_code_reference_expression::do_get_tree(Translate_context* context) { - return Func_expression::get_code_pointer(context->gogo(), this->function_, + Bexpression* ret = + Func_expression::get_code_pointer(context->gogo(), this->function_, this->location()); + return expr_to_tree(ret); } // Make a reference to the code of a function. @@ -3055,8 +3050,7 @@ class Type_conversion_expression : public Expression do_lower(Gogo*, Named_object*, Statement_inserter*, int); bool - do_is_constant() const - { return this->expr_->is_constant(); } + do_is_constant() const; bool do_numeric_constant_value(Numeric_constant*) const; @@ -3198,6 +3192,27 @@ Type_conversion_expression::do_lower(Gogo*, Named_object*, return this; } +// Return whether a type conversion is a constant. + +bool +Type_conversion_expression::do_is_constant() const +{ + if (!this->expr_->is_constant()) + return false; + + // A conversion to a type that may not be used as a constant is not + // a constant. For example, []byte(nil). + Type* type = this->type_; + if (type->integer_type() == NULL + && type->float_type() == NULL + && type->complex_type() == NULL + && !type->is_boolean_type() + && !type->is_string_type()) + return false; + + return true; +} + // Return the constant numeric value if there is one. bool @@ -5586,6 +5601,15 @@ Binary_expression::do_determine_type(const Type_context* context) subcontext.type = NULL; } + if (this->op_ == OPERATOR_ANDAND || this->op_ == OPERATOR_OROR) + { + // For a logical operation, the context does not determine the + // types of the operands. The operands must be some boolean + // type but if the context has a boolean type they do not + // inherit it. See http://golang.org/issue/3924. + subcontext.type = NULL; + } + // Set the context for the left hand operand. if (is_shift_op) { @@ -5967,6 +5991,43 @@ Binary_expression::do_get_tree(Translate_context* context) right); } + // For complex division Go wants slightly different results than the + // GCC library provides, so we have our own runtime routine. + if (this->op_ == OPERATOR_DIV && this->left_->type()->complex_type() != NULL) + { + const char *name; + tree *pdecl; + Type* ctype; + static tree complex64_div_decl; + static tree complex128_div_decl; + switch (this->left_->type()->complex_type()->bits()) + { + case 64: + name = "__go_complex64_div"; + pdecl = &complex64_div_decl; + ctype = Type::lookup_complex_type("complex64"); + break; + case 128: + name = "__go_complex128_div"; + pdecl = &complex128_div_decl; + ctype = Type::lookup_complex_type("complex128"); + break; + default: + go_unreachable(); + } + Btype* cbtype = ctype->get_backend(gogo); + tree ctype_tree = type_to_tree(cbtype); + return Gogo::call_builtin(pdecl, + this->location(), + name, + 2, + ctype_tree, + ctype_tree, + fold_convert_loc(gccloc, ctype_tree, left), + type, + fold_convert_loc(gccloc, ctype_tree, right)); + } + tree compute_type = excess_precision_type(type); if (compute_type != NULL_TREE) { @@ -7191,6 +7252,15 @@ Builtin_call_expression::do_lower(Gogo* gogo, Named_object* function, if (this->code_ == BUILTIN_OFFSETOF) { Expression* arg = this->one_arg(); + + if (arg->bound_method_expression() != NULL + || arg->interface_field_reference_expression() != NULL) + { + this->report_error(_("invalid use of method value as argument " + "of Offsetof")); + return this; + } + Field_reference_expression* farg = arg->field_reference_expression(); while (farg != NULL) { @@ -7200,7 +7270,8 @@ Builtin_call_expression::do_lower(Gogo* gogo, Named_object* function, // it must not be reached through pointer indirections. if (farg->expr()->deref() != farg->expr()) { - this->report_error(_("argument of Offsetof implies indirection of an embedded field")); + this->report_error(_("argument of Offsetof implies " + "indirection of an embedded field")); return this; } // Go up until we reach the original base. @@ -7476,7 +7547,7 @@ Builtin_call_expression::check_int_value(Expression* e, bool is_length) switch (nc.to_unsigned_long(&v)) { case Numeric_constant::NC_UL_VALID: - return true; + break; case Numeric_constant::NC_UL_NOTINT: error_at(e->location(), "non-integer %s argument to make", is_length ? "len" : "cap"); @@ -7488,8 +7559,23 @@ Builtin_call_expression::check_int_value(Expression* e, bool is_length) case Numeric_constant::NC_UL_BIG: // We don't want to give a compile-time error for a 64-bit // value on a 32-bit target. - return true; + break; } + + mpz_t val; + if (!nc.to_int(&val)) + go_unreachable(); + int bits = mpz_sizeinbase(val, 2); + mpz_clear(val); + Type* int_type = Type::lookup_integer_type("int"); + if (bits >= int_type->integer_type()->bits()) + { + error_at(e->location(), "%s argument too large for make", + is_length ? "len" : "cap"); + return false; + } + + return true; } if (e->type()->integer_type() != NULL) @@ -7595,6 +7681,8 @@ Find_call_expression::expression(Expression** pexpr) bool Builtin_call_expression::do_is_constant() const { + if (this->is_error_expression()) + return true; switch (this->code_) { case BUILTIN_LEN: @@ -9744,14 +9832,8 @@ Call_expression::do_get_tree(Translate_context* context) } tree fntype_tree = type_to_tree(fntype->get_backend(gogo)); - if (fntype_tree == error_mark_node) - return error_mark_node; - go_assert(POINTER_TYPE_P(fntype_tree)); - if (TREE_TYPE(fntype_tree) == error_mark_node) - return error_mark_node; - go_assert(TREE_CODE(TREE_TYPE(fntype_tree)) == RECORD_TYPE); - tree fnfield_type = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(fntype_tree))); - if (fnfield_type == error_mark_node) + tree fnfield_type = type_to_tree(fntype->get_backend_fntype(gogo)); + if (fntype_tree == error_mark_node || fnfield_type == error_mark_node) return error_mark_node; go_assert(FUNCTION_POINTER_TYPE_P(fnfield_type)); tree rettype = TREE_TYPE(TREE_TYPE(fnfield_type)); @@ -9763,7 +9845,7 @@ Call_expression::do_get_tree(Translate_context* context) if (func != NULL) { Named_object* no = func->named_object(); - fn = Func_expression::get_code_pointer(gogo, no, location); + fn = expr_to_tree(Func_expression::get_code_pointer(gogo, no, location)); if (!has_closure) closure_tree = NULL_TREE; else @@ -10817,11 +10899,20 @@ String_index_expression::do_determine_type(const Type_context*) void String_index_expression::do_check_types(Gogo*) { - if (this->start_->type()->integer_type() == NULL) + Numeric_constant nc; + unsigned long v; + if (this->start_->type()->integer_type() == NULL + && !this->start_->type()->is_error() + && (!this->start_->numeric_constant_value(&nc) + || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT)) this->report_error(_("index must be integer")); if (this->end_ != NULL && this->end_->type()->integer_type() == NULL - && !this->end_->is_nil_expression()) + && !this->end_->type()->is_error() + && !this->end_->is_nil_expression() + && !this->end_->is_error_expression() + && (!this->end_->numeric_constant_value(&nc) + || nc.to_unsigned_long(&v) == Numeric_constant::NC_UL_NOTINT)) this->report_error(_("slice end must be integer")); std::string sval; diff --git a/gcc-4.8/gcc/go/gofrontend/expressions.h b/gcc-4.8/gcc/go/gofrontend/expressions.h index bc7a25f76..35bfcfe8e 100644 --- a/gcc-4.8/gcc/go/gofrontend/expressions.h +++ b/gcc-4.8/gcc/go/gofrontend/expressions.h @@ -1514,8 +1514,8 @@ class Func_expression : public Expression closure() { return this->closure_; } - // Return a tree for the code for a function. - static tree + // Return a backend expression for the code of a function. + static Bexpression* get_code_pointer(Gogo*, Named_object* function, Location loc); protected: diff --git a/gcc-4.8/gcc/go/gofrontend/gogo-tree.cc b/gcc-4.8/gcc/go/gofrontend/gogo-tree.cc index a95f29015..ef6c842c0 100644 --- a/gcc-4.8/gcc/go/gofrontend/gogo-tree.cc +++ b/gcc-4.8/gcc/go/gofrontend/gogo-tree.cc @@ -985,74 +985,6 @@ Gogo::write_globals() delete[] vec; } -// Get a tree for the identifier for a named object. - -tree -Named_object::get_id(Gogo* gogo) -{ - go_assert(!this->is_variable() && !this->is_result_variable()); - std::string decl_name; - if (this->is_function_declaration() - && !this->func_declaration_value()->asm_name().empty()) - decl_name = this->func_declaration_value()->asm_name(); - else if (this->is_type() - && Linemap::is_predeclared_location(this->type_value()->location())) - { - // We don't need the package name for builtin types. - decl_name = Gogo::unpack_hidden_name(this->name_); - } - else - { - std::string package_name; - if (this->package_ == NULL) - package_name = gogo->package_name(); - else - package_name = this->package_->package_name(); - - // Note that this will be misleading if this is an unexported - // method generated for an embedded imported type. In that case - // the unexported method should have the package name of the - // package from which it is imported, but we are going to give - // it our package name. Fixing this would require knowing the - // package name, but we only know the package path. It might be - // better to use package paths here anyhow. This doesn't affect - // the assembler code, because we always set that name in - // Function::get_or_make_decl anyhow. FIXME. - - decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_); - - Function_type* fntype; - if (this->is_function()) - fntype = this->func_value()->type(); - else if (this->is_function_declaration()) - fntype = this->func_declaration_value()->type(); - else - fntype = NULL; - if (fntype != NULL && fntype->is_method()) - { - decl_name.push_back('.'); - decl_name.append(fntype->receiver()->type()->mangled_name(gogo)); - } - } - if (this->is_type()) - { - unsigned int index; - const Named_object* in_function = this->type_value()->in_function(&index); - if (in_function != NULL) - { - decl_name += '$' + Gogo::unpack_hidden_name(in_function->name()); - if (index > 0) - { - char buf[30]; - snprintf(buf, sizeof buf, "%u", index); - decl_name += '$'; - decl_name += buf; - } - } - } - return get_identifier_from_string(decl_name); -} - // Get a tree for a named object. tree @@ -1067,11 +999,6 @@ Named_object::get_tree(Gogo* gogo, Named_object* function) return error_mark_node; } - tree name; - if (this->classification_ == NAMED_OBJECT_TYPE) - name = NULL_TREE; - else - name = this->get_id(gogo); tree decl; switch (this->classification_) { @@ -1099,6 +1026,7 @@ Named_object::get_tree(Gogo* gogo, Named_object* function) decl = error_mark_node; else if (INTEGRAL_TYPE_P(TREE_TYPE(expr_tree))) { + tree name = get_identifier_from_string(this->get_id(gogo)); decl = build_decl(named_constant->location().gcc_location(), CONST_DECL, name, TREE_TYPE(expr_tree)); DECL_INITIAL(decl) = expr_tree; @@ -1161,7 +1089,7 @@ Named_object::get_tree(Gogo* gogo, Named_object* function) case NAMED_OBJECT_FUNC: { Function* func = this->u_.func_value; - decl = func->get_or_make_decl(gogo, this, name); + decl = function_to_tree(func->get_or_make_decl(gogo, this)); if (decl != error_mark_node) { if (func->block() != NULL) @@ -1286,123 +1214,12 @@ Variable::get_init_block(Gogo* gogo, Named_object* function, tree var_decl) return block_tree; } -// Get a tree for a function decl. +// Get the backend representation. -tree -Function::get_or_make_decl(Gogo* gogo, Named_object* no, tree id) +Bfunction* +Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no) { - if (this->fndecl_ == NULL_TREE) - { - tree functype = type_to_tree(this->type_->get_backend(gogo)); - - if (functype != error_mark_node) - { - // The type of a function comes back as a pointer to a - // struct whose first field is the function, but we want the - // real function type for a function declaration. - go_assert(POINTER_TYPE_P(functype) - && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE); - functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype))); - go_assert(FUNCTION_POINTER_TYPE_P(functype)); - functype = TREE_TYPE(functype); - } - - if (functype == error_mark_node) - this->fndecl_ = error_mark_node; - else - { - tree decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, - id, functype); - - this->fndecl_ = decl; - - if (no->package() != NULL) - ; - else if (this->enclosing_ != NULL || Gogo::is_thunk(no)) - ; - else if (Gogo::unpack_hidden_name(no->name()) == "init" - && !this->type_->is_method()) - ; - else if (Gogo::unpack_hidden_name(no->name()) == "main" - && gogo->is_main_package()) - TREE_PUBLIC(decl) = 1; - // Methods have to be public even if they are hidden because - // they can be pulled into type descriptors when using - // anonymous fields. - else if (!Gogo::is_hidden_name(no->name()) - || this->type_->is_method()) - { - TREE_PUBLIC(decl) = 1; - std::string pkgpath = gogo->pkgpath_symbol(); - if (this->type_->is_method() - && Gogo::is_hidden_name(no->name()) - && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath()) - { - // This is a method we created for an unexported - // method of an imported embedded type. We need to - // use the pkgpath of the imported package to avoid - // a possible name collision. See bug478 for a test - // case. - pkgpath = Gogo::hidden_name_pkgpath(no->name()); - pkgpath = Gogo::pkgpath_for_symbol(pkgpath); - } - - std::string asm_name = pkgpath; - asm_name.append(1, '.'); - asm_name.append(Gogo::unpack_hidden_name(no->name())); - if (this->type_->is_method()) - { - asm_name.append(1, '.'); - Type* rtype = this->type_->receiver()->type(); - asm_name.append(rtype->mangled_name(gogo)); - } - SET_DECL_ASSEMBLER_NAME(decl, - get_identifier_from_string(asm_name)); - } - - // Why do we have to do this in the frontend? - tree restype = TREE_TYPE(functype); - tree resdecl = - build_decl(this->location().gcc_location(), RESULT_DECL, NULL_TREE, - restype); - DECL_ARTIFICIAL(resdecl) = 1; - DECL_IGNORED_P(resdecl) = 1; - DECL_CONTEXT(resdecl) = decl; - DECL_RESULT(decl) = resdecl; - - // If a function calls the predeclared recover function, we - // can't inline it, because recover behaves differently in a - // function passed directly to defer. If this is a recover - // thunk that we built to test whether a function can be - // recovered, we can't inline it, because that will mess up - // our return address comparison. - if (this->calls_recover_ || this->is_recover_thunk_) - DECL_UNINLINABLE(decl) = 1; - - // If this is a thunk created to call a function which calls - // the predeclared recover function, we need to disable - // stack splitting for the thunk. - if (this->is_recover_thunk_) - { - tree attr = get_identifier("__no_split_stack__"); - DECL_ATTRIBUTES(decl) = tree_cons(attr, NULL_TREE, NULL_TREE); - } - - if (this->in_unique_section_) - resolve_unique_section (decl, 0, 1); - - go_preserve_from_gc(decl); - } - } - return this->fndecl_; -} - -// Get a tree for a function declaration. - -tree -Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no, tree id) -{ - if (this->fndecl_ == NULL_TREE) + if (this->fndecl_ == NULL) { // Let Go code use an asm declaration to pick up a builtin // function. @@ -1412,38 +1229,15 @@ Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no, tree id) builtin_functions.find(this->asm_name_); if (p != builtin_functions.end()) { - this->fndecl_ = p->second; + this->fndecl_ = tree_to_function(p->second); return this->fndecl_; } } - tree functype = type_to_tree(this->fntype_->get_backend(gogo)); - - if (functype != error_mark_node) - { - // The type of a function comes back as a pointer to a - // struct whose first field is the function, but we want the - // real function type for a function declaration. - go_assert(POINTER_TYPE_P(functype) - && TREE_CODE(TREE_TYPE(functype)) == RECORD_TYPE); - functype = TREE_TYPE(TYPE_FIELDS(TREE_TYPE(functype))); - go_assert(FUNCTION_POINTER_TYPE_P(functype)); - functype = TREE_TYPE(functype); - } - - tree decl; - if (functype == error_mark_node) - decl = error_mark_node; - else - { - decl = build_decl(this->location().gcc_location(), FUNCTION_DECL, id, - functype); - TREE_PUBLIC(decl) = 1; - DECL_EXTERNAL(decl) = 1; - + std::string asm_name; if (this->asm_name_.empty()) { - std::string asm_name = (no->package() == NULL + asm_name = (no->package() == NULL ? gogo->pkgpath_symbol() : no->package()->pkgpath_symbol()); asm_name.append(1, '.'); @@ -1454,16 +1248,27 @@ Function_declaration::get_or_make_decl(Gogo* gogo, Named_object* no, tree id) Type* rtype = this->fntype_->receiver()->type(); asm_name.append(rtype->mangled_name(gogo)); } - SET_DECL_ASSEMBLER_NAME(decl, - get_identifier_from_string(asm_name)); } + + Btype* functype = this->fntype_->get_backend_fntype(gogo); + this->fndecl_ = + gogo->backend()->function(functype, no->get_id(gogo), asm_name, + true, true, true, false, false, + this->location()); } - this->fndecl_ = decl; - go_preserve_from_gc(decl); - } + return this->fndecl_; } +// Return the function's decl after it has been built. + +tree +Function::get_decl() const +{ + go_assert(this->fndecl_ != NULL); + return function_to_tree(this->fndecl_); +} + // We always pass the receiver to a method as a pointer. If the // receiver is actually declared as a non-pointer type, then we copy // the value into a local variable, so that it has the right type. In @@ -1558,7 +1363,7 @@ Function::copy_parm_to_heap(Gogo* gogo, Named_object* no, tree var_decl) void Function::build_tree(Gogo* gogo, Named_object* named_function) { - tree fndecl = this->fndecl_; + tree fndecl = this->get_decl(); go_assert(fndecl != NULL_TREE); tree params = NULL_TREE; @@ -1796,7 +1601,7 @@ Function::build_defer_wrapper(Gogo* gogo, Named_object* named_function, set = NULL_TREE; else set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node, - DECL_RESULT(this->fndecl_), retval); + DECL_RESULT(this->get_decl()), retval); tree ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR, void_type_node, set); append_to_statement_list(ret_stmt, &stmt_list); @@ -1851,7 +1656,7 @@ Function::build_defer_wrapper(Gogo* gogo, Named_object* named_function, retval = this->return_value(gogo, named_function, end_loc, &stmt_list); set = fold_build2_loc(end_loc.gcc_location(), MODIFY_EXPR, void_type_node, - DECL_RESULT(this->fndecl_), retval); + DECL_RESULT(this->get_decl()), retval); ret_stmt = fold_build1_loc(end_loc.gcc_location(), RETURN_EXPR, void_type_node, set); @@ -1869,7 +1674,7 @@ Function::build_defer_wrapper(Gogo* gogo, Named_object* named_function, *fini = stmt_list; } -// Return the value to assign to DECL_RESULT(this->fndecl_). This may +// Return the value to assign to DECL_RESULT(this->get_decl()). This may // also add statements to STMT_LIST, which need to be executed before // the assignment. This is used for a return statement with no // explicit values. @@ -1902,7 +1707,7 @@ Function::return_value(Gogo* gogo, Named_object* named_function, } else { - tree rettype = TREE_TYPE(DECL_RESULT(this->fndecl_)); + tree rettype = TREE_TYPE(DECL_RESULT(this->get_decl())); retval = create_tmp_var(rettype, "RESULT"); tree field = TYPE_FIELDS(rettype); int index = 0; @@ -2323,18 +2128,14 @@ Gogo::interface_method_table_for_type(const Interface_type* interface, go_assert(m != NULL); Named_object* no = m->named_object(); - - tree fnid = no->get_id(this); - - tree fndecl; + Bfunction* bf; if (no->is_function()) - fndecl = no->func_value()->get_or_make_decl(this, no, fnid); + bf = no->func_value()->get_or_make_decl(this, no); else if (no->is_function_declaration()) - fndecl = no->func_declaration_value()->get_or_make_decl(this, no, - fnid); + bf = no->func_declaration_value()->get_or_make_decl(this, no); else go_unreachable(); - fndecl = build_fold_addr_expr(fndecl); + tree fndecl = build_fold_addr_expr(function_to_tree(bf)); elt = pointers->quick_push(empty); elt->index = size_int(i); @@ -2353,10 +2154,11 @@ Gogo::interface_method_table_for_type(const Interface_type* interface, TREE_CONSTANT(decl) = 1; DECL_INITIAL(decl) = constructor; - // If the interface type has hidden methods, then this is the only - // definition of the table. Otherwise it is a comdat table which - // may be defined in multiple packages. - if (has_hidden_methods) + // If the interface type has hidden methods, and the table is for a + // named type, then this is the only definition of the table. + // Otherwise it is a comdat table which may be defined in multiple + // packages. + if (has_hidden_methods && type->named_type() != NULL) TREE_PUBLIC(decl) = 1; else { diff --git a/gcc-4.8/gcc/go/gofrontend/gogo.cc b/gcc-4.8/gcc/go/gofrontend/gogo.cc index 9f918cb81..e16b0d3a5 100644 --- a/gcc-4.8/gcc/go/gofrontend/gogo.cc +++ b/gcc-4.8/gcc/go/gofrontend/gogo.cc @@ -2822,7 +2822,10 @@ Build_recover_thunks::function(Named_object* orig_no) if (orig_fntype->is_varargs()) new_fntype->set_is_varargs(); - std::string name = orig_no->name() + "$recover"; + std::string name = orig_no->name(); + if (orig_fntype->is_method()) + name += "$" + orig_fntype->receiver()->type()->mangled_name(gogo); + name += "$recover"; Named_object *new_no = gogo->start_function(name, new_fntype, false, location); Function *new_func = new_no->func_value(); @@ -2916,7 +2919,25 @@ Build_recover_thunks::function(Named_object* orig_no) && !orig_rec_no->var_value()->is_receiver()); orig_rec_no->var_value()->set_is_receiver(); - const std::string& new_receiver_name(orig_fntype->receiver()->name()); + std::string new_receiver_name(orig_fntype->receiver()->name()); + if (new_receiver_name.empty()) + { + // Find the receiver. It was named "r.NNN" in + // Gogo::start_function. + for (Bindings::const_definitions_iterator p = + new_bindings->begin_definitions(); + p != new_bindings->end_definitions(); + ++p) + { + const std::string& pname((*p)->name()); + if (pname[0] == 'r' && pname[1] == '.') + { + new_receiver_name = pname; + break; + } + } + go_assert(!new_receiver_name.empty()); + } Named_object* new_rec_no = new_bindings->lookup_local(new_receiver_name); if (new_rec_no == NULL) go_assert(saw_errors()); @@ -3320,7 +3341,8 @@ Function::Function(Function_type* type, Function* enclosing, Block* block, closure_var_(NULL), block_(block), location_(location), labels_(), local_type_count_(0), descriptor_(NULL), fndecl_(NULL), defer_stack_(NULL), is_sink_(false), results_are_named_(false), nointerface_(false), - calls_recover_(false), is_recover_thunk_(false), has_recover_thunk_(false), + is_unnamed_type_stub_method_(false), calls_recover_(false), + is_recover_thunk_(false), has_recover_thunk_(false), in_unique_section_(false) { } @@ -3819,6 +3841,81 @@ Function::import_func(Import* imp, std::string* pname, *presults = results; } +// Get the backend representation. + +Bfunction* +Function::get_or_make_decl(Gogo* gogo, Named_object* no) +{ + if (this->fndecl_ == NULL) + { + std::string asm_name; + bool is_visible = false; + if (no->package() != NULL) + ; + else if (this->enclosing_ != NULL || Gogo::is_thunk(no)) + ; + else if (Gogo::unpack_hidden_name(no->name()) == "init" + && !this->type_->is_method()) + ; + else if (Gogo::unpack_hidden_name(no->name()) == "main" + && gogo->is_main_package()) + is_visible = true; + // Methods have to be public even if they are hidden because + // they can be pulled into type descriptors when using + // anonymous fields. + else if (!Gogo::is_hidden_name(no->name()) + || this->type_->is_method()) + { + if (!this->is_unnamed_type_stub_method_) + is_visible = true; + std::string pkgpath = gogo->pkgpath_symbol(); + if (this->type_->is_method() + && Gogo::is_hidden_name(no->name()) + && Gogo::hidden_name_pkgpath(no->name()) != gogo->pkgpath()) + { + // This is a method we created for an unexported + // method of an imported embedded type. We need to + // use the pkgpath of the imported package to avoid + // a possible name collision. See bug478 for a test + // case. + pkgpath = Gogo::hidden_name_pkgpath(no->name()); + pkgpath = Gogo::pkgpath_for_symbol(pkgpath); + } + + asm_name = pkgpath; + asm_name.append(1, '.'); + asm_name.append(Gogo::unpack_hidden_name(no->name())); + if (this->type_->is_method()) + { + asm_name.append(1, '.'); + Type* rtype = this->type_->receiver()->type(); + asm_name.append(rtype->mangled_name(gogo)); + } + } + + // If a function calls the predeclared recover function, we + // can't inline it, because recover behaves differently in a + // function passed directly to defer. If this is a recover + // thunk that we built to test whether a function can be + // recovered, we can't inline it, because that will mess up + // our return address comparison. + bool is_inlinable = !(this->calls_recover_ || this->is_recover_thunk_); + + // If this is a thunk created to call a function which calls + // the predeclared recover function, we need to disable + // stack splitting for the thunk. + bool disable_split_stack = this->is_recover_thunk_; + + Btype* functype = this->type_->get_backend_fntype(gogo); + this->fndecl_ = + gogo->backend()->function(functype, no->get_id(gogo), asm_name, + is_visible, false, is_inlinable, + disable_split_stack, + this->in_unique_section_, this->location()); + } + return this->fndecl_; +} + // Class Block. Block::Block(Block* enclosing, Location location) @@ -5110,6 +5207,75 @@ Named_object::get_backend_variable(Gogo* gogo, Named_object* function) go_unreachable(); } + +// Return the external identifier for this object. + +std::string +Named_object::get_id(Gogo* gogo) +{ + go_assert(!this->is_variable() && !this->is_result_variable()); + std::string decl_name; + if (this->is_function_declaration() + && !this->func_declaration_value()->asm_name().empty()) + decl_name = this->func_declaration_value()->asm_name(); + else if (this->is_type() + && Linemap::is_predeclared_location(this->type_value()->location())) + { + // We don't need the package name for builtin types. + decl_name = Gogo::unpack_hidden_name(this->name_); + } + else + { + std::string package_name; + if (this->package_ == NULL) + package_name = gogo->package_name(); + else + package_name = this->package_->package_name(); + + // Note that this will be misleading if this is an unexported + // method generated for an embedded imported type. In that case + // the unexported method should have the package name of the + // package from which it is imported, but we are going to give + // it our package name. Fixing this would require knowing the + // package name, but we only know the package path. It might be + // better to use package paths here anyhow. This doesn't affect + // the assembler code, because we always set that name in + // Function::get_or_make_decl anyhow. FIXME. + + decl_name = package_name + '.' + Gogo::unpack_hidden_name(this->name_); + + Function_type* fntype; + if (this->is_function()) + fntype = this->func_value()->type(); + else if (this->is_function_declaration()) + fntype = this->func_declaration_value()->type(); + else + fntype = NULL; + if (fntype != NULL && fntype->is_method()) + { + decl_name.push_back('.'); + decl_name.append(fntype->receiver()->type()->mangled_name(gogo)); + } + } + if (this->is_type()) + { + unsigned int index; + const Named_object* in_function = this->type_value()->in_function(&index); + if (in_function != NULL) + { + decl_name += '$' + Gogo::unpack_hidden_name(in_function->name()); + if (index > 0) + { + char buf[30]; + snprintf(buf, sizeof buf, "%u", index); + decl_name += '$'; + decl_name += buf; + } + } + } + return decl_name; +} + // Class Bindings. Bindings::Bindings(Bindings* enclosing) diff --git a/gcc-4.8/gcc/go/gofrontend/gogo.h b/gcc-4.8/gcc/go/gofrontend/gogo.h index 23968d4a1..31b258d62 100644 --- a/gcc-4.8/gcc/go/gofrontend/gogo.h +++ b/gcc-4.8/gcc/go/gofrontend/gogo.h @@ -48,6 +48,7 @@ class Bstatement; class Bblock; class Bvariable; class Blabel; +class Bfunction; // This file declares the basic classes used to hold the internal // representation of Go which is built by the parser. @@ -952,6 +953,15 @@ class Function this->nointerface_ = true; } + // Record that this function is a stub method created for an unnamed + // type. + void + set_is_unnamed_type_stub_method() + { + go_assert(this->is_method()); + this->is_unnamed_type_stub_method_ = true; + } + // Add a new field to the closure variable. void add_closure_field(Named_object* var, Location loc) @@ -1089,17 +1099,13 @@ class Function this->descriptor_ = descriptor; } - // Return the function's decl given an identifier. - tree - get_or_make_decl(Gogo*, Named_object*, tree id); + // Return the backend representation. + Bfunction* + get_or_make_decl(Gogo*, Named_object*); // Return the function's decl after it has been built. tree - get_decl() const - { - go_assert(this->fndecl_ != NULL); - return this->fndecl_; - } + get_decl() const; // Set the function decl to hold a tree of the function code. void @@ -1170,7 +1176,7 @@ class Function // The function descriptor, if any. Expression* descriptor_; // The function decl. - tree fndecl_; + Bfunction* fndecl_; // The defer stack variable. A pointer to this variable is used to // distinguish the defer stack for one function from another. This // is NULL unless we actually need a defer stack. @@ -1181,6 +1187,9 @@ class Function bool results_are_named_ : 1; // True if this method should not be included in the type descriptor. bool nointerface_ : 1; + // True if this function is a stub method created for an unnamed + // type. + bool is_unnamed_type_stub_method_ : 1; // True if this function calls the predeclared recover function. bool calls_recover_ : 1; // True if this a thunk built for a function which calls recover. @@ -1265,9 +1274,9 @@ class Function_declaration has_descriptor() const { return this->descriptor_ != NULL; } - // Return a decl for the function given an identifier. - tree - get_or_make_decl(Gogo*, Named_object*, tree id); + // Return a backend representation. + Bfunction* + get_or_make_decl(Gogo*, Named_object*); // If there is a descriptor, build it into the backend // representation. @@ -1290,7 +1299,7 @@ class Function_declaration // The function descriptor, if any. Expression* descriptor_; // The function decl if needed. - tree fndecl_; + Bfunction* fndecl_; }; // A variable. @@ -2181,8 +2190,8 @@ class Named_object Bvariable* get_backend_variable(Gogo*, Named_object* function); - // Return a tree for the external identifier for this object. - tree + // Return the external identifier for this object. + std::string get_id(Gogo*); // Return a tree representing this object. diff --git a/gcc-4.8/gcc/go/gofrontend/import.h b/gcc-4.8/gcc/go/gofrontend/import.h index c6844cda8..9917937e4 100644 --- a/gcc-4.8/gcc/go/gofrontend/import.h +++ b/gcc-4.8/gcc/go/gofrontend/import.h @@ -149,6 +149,11 @@ class Import location() const { return this->location_; } + // Return the package we are importing. + Package* + package() const + { return this->package_; } + // Return the next character. int peek_char() diff --git a/gcc-4.8/gcc/go/gofrontend/lex.cc b/gcc-4.8/gcc/go/gofrontend/lex.cc index 22a1f6e2a..d03c4bde2 100644 --- a/gcc-4.8/gcc/go/gofrontend/lex.cc +++ b/gcc-4.8/gcc/go/gofrontend/lex.cc @@ -873,7 +873,28 @@ Lex::gather_identifier() && (cc < 'a' || cc > 'z') && cc != '_' && (cc < '0' || cc > '9')) + { + // Check for an invalid character here, as we get better + // error behaviour if we swallow them as part of the + // identifier we are building. + if ((cc >= ' ' && cc < 0x7f) + || cc == '\t' + || cc == '\r' + || cc == '\n') break; + + this->lineoff_ = p - this->linebuf_; + error_at(this->location(), + "invalid character 0x%x in identifier", + cc); + if (!has_non_ascii_char) + { + buf.assign(pstart, p - pstart); + has_non_ascii_char = true; + } + if (!Lex::is_invalid_identifier(buf)) + buf.append("$INVALID$"); + } ++p; if (is_first) { diff --git a/gcc-4.8/gcc/go/gofrontend/parse.cc b/gcc-4.8/gcc/go/gofrontend/parse.cc index 498125bb2..9c7d8277e 100644 --- a/gcc-4.8/gcc/go/gofrontend/parse.cc +++ b/gcc-4.8/gcc/go/gofrontend/parse.cc @@ -744,6 +744,8 @@ Parse::signature(Typed_identifier* receiver, Location location) return NULL; Parse::Names names; + if (receiver != NULL) + names[receiver->name()] = receiver; if (params != NULL) this->check_signature_names(params, &names); if (results != NULL) diff --git a/gcc-4.8/gcc/go/gofrontend/runtime.cc b/gcc-4.8/gcc/go/gofrontend/runtime.cc index ecc508d0d..3b0f18807 100644 --- a/gcc-4.8/gcc/go/gofrontend/runtime.cc +++ b/gcc-4.8/gcc/go/gofrontend/runtime.cc @@ -42,6 +42,8 @@ enum Runtime_function_type RFT_RUNE, // Go type float64, C type double. RFT_FLOAT64, + // Go type complex64, C type __complex float. + RFT_COMPLEX64, // Go type complex128, C type __complex double. RFT_COMPLEX128, // Go type string, C type struct __go_string. @@ -126,6 +128,10 @@ runtime_function_type(Runtime_function_type bft) t = Type::lookup_float_type("float64"); break; + case RFT_COMPLEX64: + t = Type::lookup_complex_type("complex64"); + break; + case RFT_COMPLEX128: t = Type::lookup_complex_type("complex128"); break; @@ -216,6 +222,7 @@ convert_to_runtime_function_type(Runtime_function_type bft, Expression* e, case RFT_UINTPTR: case RFT_RUNE: case RFT_FLOAT64: + case RFT_COMPLEX64: case RFT_COMPLEX128: case RFT_STRING: case RFT_POINTER: diff --git a/gcc-4.8/gcc/go/gofrontend/runtime.def b/gcc-4.8/gcc/go/gofrontend/runtime.def index 0d3fd3c43..a303a5041 100644 --- a/gcc-4.8/gcc/go/gofrontend/runtime.def +++ b/gcc-4.8/gcc/go/gofrontend/runtime.def @@ -68,6 +68,12 @@ DEF_GO_RUNTIME(STRING_TO_INT_ARRAY, "__go_string_to_int_array", P1(STRING), R1(SLICE)) +// Complex division. +DEF_GO_RUNTIME(COMPLEX64_DIV, "__go_complex64_div", + P2(COMPLEX64, COMPLEX64), R1(COMPLEX64)) +DEF_GO_RUNTIME(COMPLEX128_DIV, "__go_complex128_div", + P2(COMPLEX128, COMPLEX128), R1(COMPLEX128)) + // Make a slice. DEF_GO_RUNTIME(MAKESLICE1, "__go_make_slice1", P2(TYPE, UINTPTR), R1(SLICE)) DEF_GO_RUNTIME(MAKESLICE2, "__go_make_slice2", P3(TYPE, UINTPTR, UINTPTR), diff --git a/gcc-4.8/gcc/go/gofrontend/types.cc b/gcc-4.8/gcc/go/gofrontend/types.cc index e1d68e743..9bc356a73 100644 --- a/gcc-4.8/gcc/go/gofrontend/types.cc +++ b/gcc-4.8/gcc/go/gofrontend/types.cc @@ -1834,7 +1834,9 @@ Type::write_specific_type_functions(Gogo* gogo, Named_type* name, bloc); gogo->start_block(bloc); - if (this->struct_type() != NULL) + if (name != NULL && name->real_type()->named_type() != NULL) + this->write_named_hash(gogo, name, hash_fntype, equal_fntype); + else if (this->struct_type() != NULL) this->struct_type()->write_hash_function(gogo, name, hash_fntype, equal_fntype); else if (this->array_type() != NULL) @@ -1852,7 +1854,9 @@ Type::write_specific_type_functions(Gogo* gogo, Named_type* name, false, bloc); gogo->start_block(bloc); - if (this->struct_type() != NULL) + if (name != NULL && name->real_type()->named_type() != NULL) + this->write_named_equal(gogo, name); + else if (this->struct_type() != NULL) this->struct_type()->write_equal_function(gogo, name); else if (this->array_type() != NULL) this->array_type()->write_equal_function(gogo, name); @@ -1865,6 +1869,100 @@ Type::write_specific_type_functions(Gogo* gogo, Named_type* name, gogo->finish_function(bloc); } +// Write a hash function that simply calls the hash function for a +// named type. This is used when one named type is defined as +// another. This ensures that this case works when the other named +// type is defined in another package and relies on calling hash +// functions defined only in that package. + +void +Type::write_named_hash(Gogo* gogo, Named_type* name, + Function_type* hash_fntype, Function_type* equal_fntype) +{ + Location bloc = Linemap::predeclared_location(); + + Named_type* base_type = name->real_type()->named_type(); + go_assert(base_type != NULL); + + // The pointer to the type we are going to hash. This is an + // unsafe.Pointer. + Named_object* key_arg = gogo->lookup("key", NULL); + go_assert(key_arg != NULL); + + // The size of the type we are going to hash. + Named_object* keysz_arg = gogo->lookup("key_size", NULL); + go_assert(keysz_arg != NULL); + + Named_object* hash_fn; + Named_object* equal_fn; + name->real_type()->type_functions(gogo, base_type, hash_fntype, equal_fntype, + &hash_fn, &equal_fn); + + // Call the hash function for the base type. + Expression* key_ref = Expression::make_var_reference(key_arg, bloc); + Expression* keysz_ref = Expression::make_var_reference(keysz_arg, bloc); + Expression_list* args = new Expression_list(); + args->push_back(key_ref); + args->push_back(keysz_ref); + Expression* func = Expression::make_func_reference(hash_fn, NULL, bloc); + Expression* call = Expression::make_call(func, args, false, bloc); + + // Return the hash of the base type. + Expression_list* vals = new Expression_list(); + vals->push_back(call); + Statement* s = Statement::make_return_statement(vals, bloc); + gogo->add_statement(s); +} + +// Write an equality function that simply calls the equality function +// for a named type. This is used when one named type is defined as +// another. This ensures that this case works when the other named +// type is defined in another package and relies on calling equality +// functions defined only in that package. + +void +Type::write_named_equal(Gogo* gogo, Named_type* name) +{ + Location bloc = Linemap::predeclared_location(); + + // The pointers to the types we are going to compare. These have + // type unsafe.Pointer. + Named_object* key1_arg = gogo->lookup("key1", NULL); + Named_object* key2_arg = gogo->lookup("key2", NULL); + go_assert(key1_arg != NULL && key2_arg != NULL); + + Named_type* base_type = name->real_type()->named_type(); + go_assert(base_type != NULL); + + // Build temporaries with the base type. + Type* pt = Type::make_pointer_type(base_type); + + Expression* ref = Expression::make_var_reference(key1_arg, bloc); + ref = Expression::make_cast(pt, ref, bloc); + Temporary_statement* p1 = Statement::make_temporary(pt, ref, bloc); + gogo->add_statement(p1); + + ref = Expression::make_var_reference(key2_arg, bloc); + ref = Expression::make_cast(pt, ref, bloc); + Temporary_statement* p2 = Statement::make_temporary(pt, ref, bloc); + gogo->add_statement(p2); + + // Compare the values for equality. + Expression* t1 = Expression::make_temporary_reference(p1, bloc); + t1 = Expression::make_unary(OPERATOR_MULT, t1, bloc); + + Expression* t2 = Expression::make_temporary_reference(p2, bloc); + t2 = Expression::make_unary(OPERATOR_MULT, t2, bloc); + + Expression* cond = Expression::make_binary(OPERATOR_EQEQ, t1, t2, bloc); + + // Return the equality comparison. + Expression_list* vals = new Expression_list(); + vals->push_back(cond); + Statement* s = Statement::make_return_statement(vals, bloc); + gogo->add_statement(s); +} + // Return a composite literal for the type descriptor for a plain type // of kind RUNTIME_TYPE_KIND named NAME. @@ -2164,26 +2262,9 @@ Type::method_constructor(Gogo*, Type* method_type, ++p; go_assert(p->is_field_name("typ")); - if (!only_value_methods && m->is_value_method()) - { - // This is a value method on a pointer type. Change the type of - // the method to use a pointer receiver. The implementation - // always uses a pointer receiver anyhow. - Type* rtype = mtype->receiver()->type(); - Type* prtype = Type::make_pointer_type(rtype); - Typed_identifier* receiver = - new Typed_identifier(mtype->receiver()->name(), prtype, - mtype->receiver()->location()); - mtype = Type::make_function_type(receiver, - (mtype->parameters() == NULL - ? NULL - : mtype->parameters()->copy()), - (mtype->results() == NULL - ? NULL - : mtype->results()->copy()), - mtype->location()); - } - vals->push_back(Expression::make_type_descriptor(mtype, bloc)); + bool want_pointer_receiver = !only_value_methods && m->is_value_method(); + nonmethod_type = mtype->copy_with_receiver_as_param(want_pointer_receiver); + vals->push_back(Expression::make_type_descriptor(nonmethod_type, bloc)); ++p; go_assert(p->is_field_name("tfn")); @@ -3383,18 +3464,10 @@ Function_type::do_hash_for_method(Gogo* gogo) const // Get the backend representation for a function type. Btype* -Function_type::do_get_backend(Gogo* gogo) +Function_type::get_backend_fntype(Gogo* gogo) { - // When we do anything with a function value other than call it, it - // is represented as a pointer to a struct whose first field is the - // actual function. So that is what we return as the type of a Go - // function. - - Location loc = this->location(); - Btype* struct_type = - gogo->backend()->placeholder_struct_type("__go_descriptor", loc); - Btype* ptr_struct_type = gogo->backend()->pointer_type(struct_type); - + if (this->fnbtype_ == NULL) + { Backend::Btyped_identifier breceiver; if (this->receiver_ != NULL) { @@ -3414,8 +3487,8 @@ Function_type::do_get_backend(Gogo* gogo) { bparameters.resize(this->parameters_->size()); size_t i = 0; - for (Typed_identifier_list::const_iterator p = this->parameters_->begin(); - p != this->parameters_->end(); + for (Typed_identifier_list::const_iterator p = + this->parameters_->begin(); p != this->parameters_->end(); ++p, ++i) { bparameters[i].name = Gogo::unpack_hidden_name(p->name()); @@ -3430,8 +3503,8 @@ Function_type::do_get_backend(Gogo* gogo) { bresults.resize(this->results_->size()); size_t i = 0; - for (Typed_identifier_list::const_iterator p = this->results_->begin(); - p != this->results_->end(); + for (Typed_identifier_list::const_iterator p = + this->results_->begin(); p != this->results_->end(); ++p, ++i) { bresults[i].name = Gogo::unpack_hidden_name(p->name()); @@ -3441,11 +3514,33 @@ Function_type::do_get_backend(Gogo* gogo) go_assert(i == bresults.size()); } - Btype* fntype = gogo->backend()->function_type(breceiver, bparameters, - bresults, loc); + this->fnbtype_ = gogo->backend()->function_type(breceiver, bparameters, + bresults, + this->location()); + + } + + return this->fnbtype_; +} + +// Get the backend representation for a Go function type. + +Btype* +Function_type::do_get_backend(Gogo* gogo) +{ + // When we do anything with a function value other than call it, it + // is represented as a pointer to a struct whose first field is the + // actual function. So that is what we return as the type of a Go + // function. + + Location loc = this->location(); + Btype* struct_type = + gogo->backend()->placeholder_struct_type("__go_descriptor", loc); + Btype* ptr_struct_type = gogo->backend()->pointer_type(struct_type); + std::vector fields(1); fields[0].name = "code"; - fields[0].btype = fntype; + fields[0].btype = this->get_backend_fntype(gogo); fields[0].location = loc; if (!gogo->backend()->set_placeholder_struct_type(struct_type, fields)) return gogo->backend()->error_type(); @@ -3821,6 +3916,32 @@ Function_type::copy_with_receiver(Type* receiver_type) const return ret; } +// Make a copy of a function type with the receiver as the first +// parameter. + +Function_type* +Function_type::copy_with_receiver_as_param(bool want_pointer_receiver) const +{ + go_assert(this->is_method()); + Typed_identifier_list* new_params = new Typed_identifier_list(); + Type* rtype = this->receiver_->type(); + if (want_pointer_receiver) + rtype = Type::make_pointer_type(rtype); + Typed_identifier receiver(this->receiver_->name(), rtype, + this->receiver_->location()); + new_params->push_back(receiver); + const Typed_identifier_list* orig_params = this->parameters_; + if (orig_params != NULL && !orig_params->empty()) + { + for (Typed_identifier_list::const_iterator p = orig_params->begin(); + p != orig_params->end(); + ++p) + new_params->push_back(*p); + } + return Type::make_function_type(NULL, new_params, this->results_, + this->location_); +} + // Make a copy of a function type ignoring any receiver and adding a // closure parameter. @@ -4195,7 +4316,8 @@ Struct_field::is_field_name(const std::string& name) const // This is a horrible hack caused by the fact that we don't pack // the names of builtin types. FIXME. - if (nt != NULL + if (!this->is_imported_ + && nt != NULL && nt->is_builtin() && nt->name() == Gogo::unpack_hidden_name(name)) return true; @@ -4204,6 +4326,36 @@ Struct_field::is_field_name(const std::string& name) const } } +// Return whether this field is an unexported field named NAME. + +bool +Struct_field::is_unexported_field_name(Gogo* gogo, + const std::string& name) const +{ + const std::string& field_name(this->field_name()); + if (Gogo::is_hidden_name(field_name) + && name == Gogo::unpack_hidden_name(field_name) + && gogo->pack_hidden_name(name, false) != field_name) + return true; + + // Check for the name of a builtin type. This is like the test in + // is_field_name, only there we return false if this->is_imported_, + // and here we return true. + if (this->is_imported_ && this->is_anonymous()) + { + Type* t = this->typed_identifier_.type(); + if (t->points_to() != NULL) + t = t->points_to(); + Named_type* nt = t->named_type(); + if (nt != NULL + && nt->is_builtin() + && nt->name() == Gogo::unpack_hidden_name(name)) + return true; + } + + return false; +} + // Return whether this field is an embedded built-in type. bool @@ -4264,12 +4416,7 @@ Struct_type::do_verify() ++p) { Type* t = p->type(); - if (t->is_undefined()) - { - error_at(p->location(), "struct field type is incomplete"); - p->set_type(Type::make_error_type()); - } - else if (p->is_anonymous()) + if (p->is_anonymous()) { if (t->named_type() != NULL && t->points_to() != NULL) { @@ -4641,14 +4788,9 @@ Struct_type::is_unexported_local_field(Gogo* gogo, for (Struct_field_list::const_iterator pf = fields->begin(); pf != fields->end(); ++pf) - { - const std::string& field_name(pf->field_name()); - if (Gogo::is_hidden_name(field_name) - && name == Gogo::unpack_hidden_name(field_name) - && gogo->pack_hidden_name(name, false) != field_name) + if (pf->is_unexported_field_name(gogo, name)) return true; } - } return false; } @@ -5250,6 +5392,7 @@ Struct_type::do_import(Import* imp) Type* ftype = imp->read_type(); Struct_field sf(Typed_identifier(name, ftype, imp->location())); + sf.set_is_imported(); if (imp->peek_char() == ' ') { @@ -9022,6 +9165,8 @@ Type::build_stub_methods(Gogo* gogo, const Type* type, const Methods* methods, fntype->is_varargs(), location); gogo->finish_function(fntype->location()); + if (type->named_type() == NULL && stub->is_function()) + stub->func_value()->set_is_unnamed_type_stub_method(); if (m->nointerface() && stub->is_function()) stub->func_value()->set_nointerface(); } @@ -9289,7 +9434,9 @@ Type::bind_field_or_method(Gogo* gogo, const Type* type, Expression* expr, else { bool is_unexported; - if (!Gogo::is_hidden_name(name)) + // The test for 'a' and 'z' is to handle builtin names, + // which are not hidden. + if (!Gogo::is_hidden_name(name) && (name[0] < 'a' || name[0] > 'z')) is_unexported = false; else { diff --git a/gcc-4.8/gcc/go/gofrontend/types.h b/gcc-4.8/gcc/go/gofrontend/types.h index d8a3080f5..0c712aaf5 100644 --- a/gcc-4.8/gcc/go/gofrontend/types.h +++ b/gcc-4.8/gcc/go/gofrontend/types.h @@ -1138,6 +1138,13 @@ class Type Function_type* equal_fntype, Named_object** hash_fn, Named_object** equal_fn); + void + write_named_hash(Gogo*, Named_type*, Function_type* hash_fntype, + Function_type* equal_fntype); + + void + write_named_equal(Gogo*, Named_type*); + // Build a composite literal for the uncommon type information. Expression* uncommon_type_constructor(Gogo*, Type* uncommon_type, @@ -1717,7 +1724,8 @@ class Function_type : public Type Typed_identifier_list* results, Location location) : Type(TYPE_FUNCTION), receiver_(receiver), parameters_(parameters), results_(results), - location_(location), is_varargs_(false), is_builtin_(false) + location_(location), is_varargs_(false), is_builtin_(false), + fnbtype_(NULL) { } // Get the receiver. @@ -1789,6 +1797,12 @@ class Function_type : public Type Function_type* copy_with_receiver(Type*) const; + // Return a copy of this type with the receiver treated as the first + // parameter. If WANT_POINTER_RECEIVER is true, the receiver is + // forced to be a pointer. + Function_type* + copy_with_receiver_as_param(bool want_pointer_receiver) const; + // Return a copy of this type ignoring any receiver and using dummy // names for all parameters. This is used for thunks for method // values. @@ -1798,6 +1812,11 @@ class Function_type : public Type static Type* make_function_type_descriptor_type(); + // Return the backend representation of this function type. This is used + // as the real type of a backend function declaration or defintion. + Btype* + get_backend_fntype(Gogo*); + protected: int do_traverse(Traverse*); @@ -1851,6 +1870,9 @@ class Function_type : public Type // Whether this is a special builtin function which can not simply // be called. This is used for len, cap, etc. bool is_builtin_; + // The backend representation of this type for backend function + // declarations and definitions. + Btype* fnbtype_; }; // The type of a pointer. @@ -1915,7 +1937,7 @@ class Struct_field { public: explicit Struct_field(const Typed_identifier& typed_identifier) - : typed_identifier_(typed_identifier), tag_(NULL) + : typed_identifier_(typed_identifier), tag_(NULL), is_imported_(false) { } // The field name. @@ -1926,6 +1948,10 @@ class Struct_field bool is_field_name(const std::string& name) const; + // Return whether this struct field is an unexported field named NAME. + bool + is_unexported_field_name(Gogo*, const std::string& name) const; + // Return whether this struct field is an embedded built-in type. bool is_embedded_builtin(Gogo*) const; @@ -1963,6 +1989,11 @@ class Struct_field set_tag(const std::string& tag) { this->tag_ = new std::string(tag); } + // Record that this field is defined in an imported struct. + void + set_is_imported() + { this->is_imported_ = true; } + // Set the type. This is only used in error cases. void set_type(Type* type) @@ -1973,6 +2004,8 @@ class Struct_field Typed_identifier typed_identifier_; // The field tag. This is NULL if the field has no tag. std::string* tag_; + // Whether this field is defined in an imported struct. + bool is_imported_; }; // A list of struct fields. diff --git a/gcc-4.8/gcc/graphite-scop-detection.c b/gcc-4.8/gcc/graphite-scop-detection.c index ab2897d5c..2cc7dd46c 100644 --- a/gcc-4.8/gcc/graphite-scop-detection.c +++ b/gcc-4.8/gcc/graphite-scop-detection.c @@ -203,7 +203,14 @@ graphite_can_represent_scev (tree scev) switch (TREE_CODE (scev)) { + case NEGATE_EXPR: + case BIT_NOT_EXPR: + CASE_CONVERT: + case NON_LVALUE_EXPR: + return graphite_can_represent_scev (TREE_OPERAND (scev, 0)); + case PLUS_EXPR: + case POINTER_PLUS_EXPR: case MINUS_EXPR: return graphite_can_represent_scev (TREE_OPERAND (scev, 0)) && graphite_can_represent_scev (TREE_OPERAND (scev, 1)); @@ -225,13 +232,15 @@ graphite_can_represent_scev (tree scev) if (!evolution_function_right_is_integer_cst (scev) || !graphite_can_represent_init (scev)) return false; + return graphite_can_represent_scev (CHREC_LEFT (scev)); default: break; } /* Only affine functions can be represented. */ - if (!scev_is_linear_expression (scev)) + if (tree_contains_chrecs (scev, NULL) + || !scev_is_linear_expression (scev)) return false; return true; @@ -330,13 +339,10 @@ stmt_simple_for_scop_p (basic_block scop_entry, loop_p outermost_loop, case GIMPLE_COND: { - tree op; - ssa_op_iter op_iter; - enum tree_code code = gimple_cond_code (stmt); - /* We can handle all binary comparisons. Inequalities are also supported as they can be represented with union of polyhedra. */ + enum tree_code code = gimple_cond_code (stmt); if (!(code == LT_EXPR || code == GT_EXPR || code == LE_EXPR @@ -345,11 +351,14 @@ stmt_simple_for_scop_p (basic_block scop_entry, loop_p outermost_loop, || code == NE_EXPR)) return false; - FOR_EACH_SSA_TREE_OPERAND (op, stmt, op_iter, SSA_OP_ALL_USES) + for (unsigned i = 0; i < 2; ++i) + { + tree op = gimple_op (stmt, i); if (!graphite_can_represent_expr (scop_entry, loop, op) /* We can not handle REAL_TYPE. Failed for pr39260. */ || TREE_CODE (TREE_TYPE (op)) == REAL_TYPE) return false; + } return true; } diff --git a/gcc-4.8/gcc/ifcvt.c b/gcc-4.8/gcc/ifcvt.c index 88967a6c2..e3353a5f2 100644 --- a/gcc-4.8/gcc/ifcvt.c +++ b/gcc-4.8/gcc/ifcvt.c @@ -115,7 +115,11 @@ count_bb_insns (const_basic_block bb) while (1) { - if (CALL_P (insn) || NONJUMP_INSN_P (insn)) + if ((CALL_P (insn) || NONJUMP_INSN_P (insn)) + /* Don't count USE/CLOBBER insns, flow_find_cross_jump etc. + don't count them either and we need consistency. */ + && GET_CODE (PATTERN (insn)) != USE + && GET_CODE (PATTERN (insn)) != CLOBBER) count++; if (insn == BB_END (bb)) @@ -505,7 +509,10 @@ cond_exec_process_if_block (ce_if_block_t * ce_info, n_insns -= 2 * n_matching; } - if (then_start && else_start) + if (then_start + && else_start + && then_n_insns > n_matching + && else_n_insns > n_matching) { int longest_match = MIN (then_n_insns - n_matching, else_n_insns - n_matching); diff --git a/gcc-4.8/gcc/ipa-cp.c b/gcc-4.8/gcc/ipa-cp.c index 7ea66f8cb..23d3e4d93 100644 --- a/gcc-4.8/gcc/ipa-cp.c +++ b/gcc-4.8/gcc/ipa-cp.c @@ -444,6 +444,9 @@ determine_versionability (struct cgraph_node *node) reason = "not a tree_versionable_function"; else if (cgraph_function_body_availability (node) <= AVAIL_OVERWRITABLE) reason = "insufficient body availability"; + else if (!opt_for_fn (node->symbol.decl, optimize) + || !opt_for_fn (node->symbol.decl, flag_ipa_cp)) + reason = "non-optimized function"; if (reason && dump_file && !node->alias && !node->thunk.thunk_p) fprintf (dump_file, "Function %s/%i is not versionable, reason: %s.\n", @@ -1455,22 +1458,21 @@ propagate_constants_accross_call (struct cgraph_edge *cs) args_count = ipa_get_cs_argument_count (args); parms_count = ipa_get_param_count (callee_info); - /* If this call goes through a thunk we must not propagate to the first (0th) - parameter. However, we might need to uncover a thunk from below a series - of aliases first. */ + /* If this call goes through a thunk we should not propagate because we + cannot redirect edges to thunks. However, we might need to uncover a + thunk from below a series of aliases first. */ alias_or_thunk = cs->callee; while (alias_or_thunk->alias) alias_or_thunk = cgraph_alias_aliased_node (alias_or_thunk); if (alias_or_thunk->thunk.thunk_p) { + for (i = 0; i < parms_count; i++) ret |= set_all_contains_variable (ipa_get_parm_lattices (callee_info, - 0)); - i = 1; + i)); + return ret; } - else - i = 0; - for (; (i < args_count) && (i < parms_count); i++) + for (i = 0; (i < args_count) && (i < parms_count); i++) { struct ipa_jump_func *jump_func = ipa_get_ith_jump_func (args, i); struct ipcp_param_lattices *dest_plats; @@ -3119,6 +3121,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct cgraph_edge *cs, struct cgraph_node *node) { struct ipa_node_params *orig_caller_info = IPA_NODE_REF (cs->caller); + struct ipa_node_params *orig_node_info; struct ipa_agg_replacement_value *aggval; int i, ec, count; @@ -3133,6 +3136,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct cgraph_edge *cs, if (aggval->index >= ec) return false; + orig_node_info = IPA_NODE_REF (IPA_NODE_REF (node)->ipcp_orig_node); if (orig_caller_info->ipcp_orig_node) orig_caller_info = IPA_NODE_REF (orig_caller_info->ipcp_orig_node); @@ -3150,7 +3154,7 @@ cgraph_edge_brings_all_agg_vals_for_node (struct cgraph_edge *cs, if (!interesting) continue; - plats = ipa_get_parm_lattices (orig_caller_info, aggval->index); + plats = ipa_get_parm_lattices (orig_node_info, aggval->index); if (plats->aggs_bottom) return false; diff --git a/gcc-4.8/gcc/ipa-prop.c b/gcc-4.8/gcc/ipa-prop.c index c62dc68a2..41aec2feb 100644 --- a/gcc-4.8/gcc/ipa-prop.c +++ b/gcc-4.8/gcc/ipa-prop.c @@ -623,16 +623,22 @@ parm_preserved_before_stmt_p (struct param_analysis_info *parm_ainfo, if (parm_ainfo && parm_ainfo->parm_modified) return false; + if (optimize) + { gcc_checking_assert (gimple_vuse (stmt) != NULL_TREE); ao_ref_init (&refd, parm_load); - /* We can cache visited statements only when parm_ainfo is available and when - we are looking at a naked load of the whole parameter. */ + /* We can cache visited statements only when parm_ainfo is available and + when we are looking at a naked load of the whole parameter. */ if (!parm_ainfo || TREE_CODE (parm_load) != PARM_DECL) visited_stmts = NULL; else visited_stmts = &parm_ainfo->parm_visited_statements; walk_aliased_vdefs (&refd, gimple_vuse (stmt), mark_modified, &modified, visited_stmts); + } + else + modified = true; + if (parm_ainfo && modified) parm_ainfo->parm_modified = true; return !modified; @@ -740,7 +746,7 @@ static bool ipa_load_from_parm_agg_1 (vec descriptors, struct param_analysis_info *parms_ainfo, gimple stmt, tree op, int *index_p, HOST_WIDE_INT *offset_p, - bool *by_ref_p) + HOST_WIDE_INT *size_p, bool *by_ref_p) { int index; HOST_WIDE_INT size, max_size; @@ -758,6 +764,8 @@ ipa_load_from_parm_agg_1 (vec descriptors, { *index_p = index; *by_ref_p = false; + if (size_p) + *size_p = size; return true; } return false; @@ -800,6 +808,8 @@ ipa_load_from_parm_agg_1 (vec descriptors, { *index_p = index; *by_ref_p = true; + if (size_p) + *size_p = size; return true; } return false; @@ -814,7 +824,7 @@ ipa_load_from_parm_agg (struct ipa_node_params *info, gimple stmt, bool *by_ref_p) { return ipa_load_from_parm_agg_1 (info->descriptors, NULL, stmt, op, index_p, - offset_p, by_ref_p); + offset_p, NULL, by_ref_p); } /* Given that an actual argument is an SSA_NAME (given in NAME) and is a result @@ -1051,7 +1061,8 @@ compute_complex_ancestor_jump_func (struct ipa_node_params *info, return; parm = TREE_OPERAND (expr, 0); index = ipa_get_param_decl_index (info, SSA_NAME_VAR (parm)); - gcc_assert (index >= 0); + if (index < 0) + return; cond_bb = single_pred (assign_bb); cond = last_stmt (cond_bb); @@ -1462,6 +1473,9 @@ ipa_compute_jump_functions (struct cgraph_node *node, { struct cgraph_edge *cs; + if (!optimize) + return; + for (cs = node->callees; cs; cs = cs->next_callee) { struct cgraph_node *callee = cgraph_function_or_thunk_node (cs->callee, @@ -1646,7 +1660,7 @@ ipa_analyze_indirect_call_uses (struct cgraph_node *node, if (gimple_assign_single_p (def) && ipa_load_from_parm_agg_1 (info->descriptors, parms_ainfo, def, gimple_assign_rhs1 (def), &index, &offset, - &by_ref)) + NULL, &by_ref)) { struct cgraph_edge *cs = ipa_note_param_call (node, index, call); cs->indirect_info->offset = offset; @@ -1847,8 +1861,7 @@ ipa_analyze_stmt_uses (struct cgraph_node *node, struct ipa_node_params *info, passed in DATA. */ static bool -visit_ref_for_mod_analysis (gimple stmt ATTRIBUTE_UNUSED, - tree op, void *data) +visit_ref_for_mod_analysis (gimple, tree op, tree, void *data) { struct ipa_node_params *info = (struct ipa_node_params *) data; @@ -2126,7 +2139,6 @@ ipa_make_edge_direct_to_target (struct cgraph_edge *ie, tree target) we may create the first reference to the object in the unit. */ if (!callee || callee->global.inlined_to) { - struct cgraph_node *first_clone = callee; /* We are better to ensure we can refer to it. In the case of static functions we are out of luck, since we already @@ -2142,31 +2154,7 @@ ipa_make_edge_direct_to_target (struct cgraph_edge *ie, tree target) xstrdup (cgraph_node_name (ie->callee)), ie->callee->uid); return NULL; } - - /* Create symbol table node. Even if inline clone exists, we can not take - it as a target of non-inlined call. */ - callee = cgraph_create_node (target); - - /* OK, we previously inlined the function, then removed the offline copy and - now we want it back for external call. This can happen when devirtualizing - while inlining function called once that happens after extern inlined and - virtuals are already removed. In this case introduce the external node - and make it available for call. */ - if (first_clone) - { - first_clone->clone_of = callee; - callee->clones = first_clone; - symtab_prevail_in_asm_name_hash ((symtab_node)callee); - symtab_insert_node_to_hashtable ((symtab_node)callee); - if (dump_file) - fprintf (dump_file, "ipa-prop: Introduced new external node " - "(%s/%i) and turned into root of the clone tree.\n", - xstrdup (cgraph_node_name (callee)), callee->uid); - } - else if (dump_file) - fprintf (dump_file, "ipa-prop: Introduced new external node " - "(%s/%i).\n", - xstrdup (cgraph_node_name (callee)), callee->uid); + callee = cgraph_get_create_real_symbol_node (target); } ipa_check_create_node_params (); @@ -3902,7 +3890,7 @@ ipcp_transform_function (struct cgraph_node *node) struct ipa_agg_replacement_value *v; gimple stmt = gsi_stmt (gsi); tree rhs, val, t; - HOST_WIDE_INT offset; + HOST_WIDE_INT offset, size; int index; bool by_ref, vce; @@ -3929,13 +3917,15 @@ ipcp_transform_function (struct cgraph_node *node) continue; if (!ipa_load_from_parm_agg_1 (descriptors, parms_ainfo, stmt, - rhs, &index, &offset, &by_ref)) + rhs, &index, &offset, &size, &by_ref)) continue; for (v = aggval; v; v = v->next) if (v->index == index && v->offset == offset) break; - if (!v || v->by_ref != by_ref) + if (!v + || v->by_ref != by_ref + || tree_low_cst (TYPE_SIZE (TREE_TYPE (v->value)), 0) != size) continue; gcc_checking_assert (is_gimple_ip_invariant (v->value)); diff --git a/gcc-4.8/gcc/ipa-pure-const.c b/gcc-4.8/gcc/ipa-pure-const.c index 94c7315c1..bedc28a8c 100644 --- a/gcc-4.8/gcc/ipa-pure-const.c +++ b/gcc-4.8/gcc/ipa-pure-const.c @@ -588,7 +588,7 @@ check_call (funct_state local, gimple call, bool ipa) /* Wrapper around check_decl for loads in local more. */ static bool -check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_load (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, false, false); @@ -600,7 +600,7 @@ check_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) /* Wrapper around check_decl for stores in local more. */ static bool -check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_store (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, true, false); @@ -612,7 +612,7 @@ check_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) /* Wrapper around check_decl for loads in ipa mode. */ static bool -check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_ipa_load (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, false, true); @@ -624,7 +624,7 @@ check_ipa_load (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) /* Wrapper around check_decl for stores in ipa mode. */ static bool -check_ipa_store (gimple stmt ATTRIBUTE_UNUSED, tree op, void *data) +check_ipa_store (gimple, tree op, tree, void *data) { if (DECL_P (op)) check_decl ((funct_state)data, op, true, true); diff --git a/gcc-4.8/gcc/ipa-split.c b/gcc-4.8/gcc/ipa-split.c index e7d469d74..f18ce82fe 100644 --- a/gcc-4.8/gcc/ipa-split.c +++ b/gcc-4.8/gcc/ipa-split.c @@ -136,7 +136,7 @@ static tree find_retval (basic_block return_bb); variable, check it if it is present in bitmap passed via DATA. */ static bool -test_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data) +test_nonssa_use (gimple, tree t, tree, void *data) { t = get_base_address (t); @@ -229,7 +229,7 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, } if (gimple_code (stmt) == GIMPLE_LABEL && test_nonssa_use (stmt, gimple_label_label (stmt), - non_ssa_vars)) + NULL_TREE, non_ssa_vars)) { ok = false; goto done; @@ -258,7 +258,7 @@ verify_non_ssa_vars (struct split_point *current, bitmap non_ssa_vars, if (virtual_operand_p (gimple_phi_result (stmt))) continue; if (TREE_CODE (op) != SSA_NAME - && test_nonssa_use (stmt, op, non_ssa_vars)) + && test_nonssa_use (stmt, op, op, non_ssa_vars)) { ok = false; goto done; @@ -670,7 +670,7 @@ find_retval (basic_block return_bb) Return true when access to T prevents splitting the function. */ static bool -mark_nonssa_use (gimple stmt ATTRIBUTE_UNUSED, tree t, void *data) +mark_nonssa_use (gimple, tree t, tree, void *data) { t = get_base_address (t); @@ -830,7 +830,7 @@ visit_bb (basic_block bb, basic_block return_bb, if (TREE_CODE (op) == SSA_NAME) bitmap_set_bit (used_ssa_names, SSA_NAME_VERSION (op)); else - can_split &= !mark_nonssa_use (stmt, op, non_ssa_vars); + can_split &= !mark_nonssa_use (stmt, op, op, non_ssa_vars); } } return can_split; diff --git a/gcc-4.8/gcc/ipa.c b/gcc-4.8/gcc/ipa.c index a9b8fb419..d73d105a0 100644 --- a/gcc-4.8/gcc/ipa.c +++ b/gcc-4.8/gcc/ipa.c @@ -359,6 +359,8 @@ symtab_remove_unreachable_nodes (bool before_inlining_p, FILE *file) { if (file) fprintf (file, " %s", cgraph_node_name (node)); + node->alias = false; + node->thunk.thunk_p = false; cgraph_node_remove_callees (node); ipa_remove_all_references (&node->symbol.ref_list); changed = true; diff --git a/gcc-4.8/gcc/ira.c b/gcc-4.8/gcc/ira.c index 9e16465e4..87e72f067 100644 --- a/gcc-4.8/gcc/ira.c +++ b/gcc-4.8/gcc/ira.c @@ -4742,6 +4742,18 @@ do_reload (void) if (need_dce && optimize) run_fast_dce (); + /* Diagnose uses of the hard frame pointer when it is used as a global + register. Often we can get away with letting the user appropriate + the frame pointer, but we should let them know when code generation + makes that impossible. */ + if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) + { + tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; + error_at (DECL_SOURCE_LOCATION (current_function_decl), + "frame pointer required, but reserved"); + inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); + } + timevar_pop (TV_IRA); } diff --git a/gcc-4.8/gcc/java/ChangeLog b/gcc-4.8/gcc/java/ChangeLog index d16146f85..aa2b556f1 100644 --- a/gcc-4.8/gcc/java/ChangeLog +++ b/gcc-4.8/gcc/java/ChangeLog @@ -1,3 +1,7 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/loop-iv.c b/gcc-4.8/gcc/loop-iv.c index be2e0f412..4c34007b4 100644 --- a/gcc-4.8/gcc/loop-iv.c +++ b/gcc-4.8/gcc/loop-iv.c @@ -425,7 +425,9 @@ iv_subreg (struct rtx_iv *iv, enum machine_mode mode) && !iv->first_special) { rtx val = get_iv_value (iv, const0_rtx); - val = lowpart_subreg (mode, val, iv->extend_mode); + val = lowpart_subreg (mode, val, + iv->extend == IV_UNKNOWN_EXTEND + ? iv->mode : iv->extend_mode); iv->base = val; iv->extend = IV_UNKNOWN_EXTEND; @@ -465,8 +467,14 @@ iv_extend (struct rtx_iv *iv, enum iv_extend_code extend, enum machine_mode mode && !iv->first_special) { rtx val = get_iv_value (iv, const0_rtx); + if (iv->extend_mode != iv->mode + && iv->extend != IV_UNKNOWN_EXTEND + && iv->extend != extend) + val = lowpart_subreg (iv->mode, val, iv->extend_mode); val = simplify_gen_unary (iv_extend_to_rtx_code (extend), mode, - val, iv->extend_mode); + val, + iv->extend == extend + ? iv->extend_mode : iv->mode); iv->base = val; iv->extend = IV_UNKNOWN_EXTEND; iv->mode = iv->extend_mode = mode; diff --git a/gcc-4.8/gcc/loop-unswitch.c b/gcc-4.8/gcc/loop-unswitch.c index 6a12952cc..d3b16b898 100644 --- a/gcc-4.8/gcc/loop-unswitch.c +++ b/gcc-4.8/gcc/loop-unswitch.c @@ -191,6 +191,7 @@ may_unswitch_on (basic_block bb, struct loop *loop, rtx *cinsn) if (!test) return NULL_RTX; + mode = VOIDmode; for (i = 0; i < 2; i++) { op[i] = XEXP (test, i); @@ -205,11 +206,15 @@ may_unswitch_on (basic_block bb, struct loop *loop, rtx *cinsn) return NULL_RTX; op[i] = get_iv_value (&iv, const0_rtx); + if (iv.extend != IV_UNKNOWN_EXTEND + && iv.mode != iv.extend_mode) + op[i] = lowpart_subreg (iv.mode, op[i], iv.extend_mode); + if (mode == VOIDmode) + mode = iv.mode; + else + gcc_assert (mode == iv.mode); } - mode = GET_MODE (op[0]); - if (mode == VOIDmode) - mode = GET_MODE (op[1]); if (GET_MODE_CLASS (mode) == MODE_CC) { if (at != BB_END (bb)) diff --git a/gcc-4.8/gcc/lra-coalesce.c b/gcc-4.8/gcc/lra-coalesce.c index 859e02f0d..01748c08e 100644 --- a/gcc-4.8/gcc/lra-coalesce.c +++ b/gcc-4.8/gcc/lra-coalesce.c @@ -221,9 +221,12 @@ lra_coalesce (void) basic_block bb; rtx mv, set, insn, next, *sorted_moves; int i, mv_num, sregno, dregno; + unsigned int regno; int coalesced_moves; int max_regno = max_reg_num (); bitmap_head involved_insns_bitmap; + bitmap_head result_pseudo_vals_bitmap; + bitmap_iterator bi; timevar_push (TV_LRA_COALESCE); @@ -318,6 +321,34 @@ lra_coalesce (void) } } } + /* If we have situation after inheritance pass: + + r1 <- ... insn originally setting p1 + i1 <- r1 setting inheritance i1 from reload r1 + ... + ... <- ... p2 ... dead p2 + .. + p1 <- i1 + r2 <- i1 + ...<- ... r2 ... + + And we are coalescing p1 and p2 using p1. In this case i1 and p1 + should have different values, otherwise they can get the same + hard reg and this is wrong for insn using p2 before coalescing. + So invalidate such inheritance pseudo values. */ + bitmap_initialize (&result_pseudo_vals_bitmap, ®_obstack); + EXECUTE_IF_SET_IN_BITMAP (&coalesced_pseudos_bitmap, 0, regno, bi) + bitmap_set_bit (&result_pseudo_vals_bitmap, + lra_reg_info[first_coalesced_pseudo[regno]].val); + EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) + if (bitmap_bit_p (&result_pseudo_vals_bitmap, lra_reg_info[regno].val)) + { + lra_set_regno_unique_value (regno); + if (lra_dump_file != NULL) + fprintf (lra_dump_file, + " Make unique value for inheritance r%d\n", regno); + } + bitmap_clear (&result_pseudo_vals_bitmap); bitmap_clear (&used_pseudos_bitmap); bitmap_clear (&involved_insns_bitmap); bitmap_clear (&coalesced_pseudos_bitmap); diff --git a/gcc-4.8/gcc/lra-constraints.c b/gcc-4.8/gcc/lra-constraints.c index 32e8c45f2..e75305278 100644 --- a/gcc-4.8/gcc/lra-constraints.c +++ b/gcc-4.8/gcc/lra-constraints.c @@ -1156,6 +1156,8 @@ simplify_operand_subreg (int nop, enum machine_mode reg_mode) enum machine_mode mode; rtx reg, new_reg; rtx operand = *curr_id->operand_loc[nop]; + enum reg_class regclass; + enum op_type type; before = after = NULL_RTX; @@ -1164,6 +1166,7 @@ simplify_operand_subreg (int nop, enum machine_mode reg_mode) mode = GET_MODE (operand); reg = SUBREG_REG (operand); + type = curr_static_id->operand[nop].type; /* If we change address for paradoxical subreg of memory, the address might violate the necessary alignment or the access might be slow. So take this into consideration. We should not worry @@ -1236,6 +1239,55 @@ simplify_operand_subreg (int nop, enum machine_mode reg_mode) "Inserting subreg reload"); return true; } + /* Force a reload for a paradoxical subreg. For paradoxical subreg, + IRA allocates hardreg to the inner pseudo reg according to its mode + instead of the outermode, so the size of the hardreg may not be enough + to contain the outermode operand, in that case we may need to insert + reload for the reg. For the following two types of paradoxical subreg, + we need to insert reload: + 1. If the op_type is OP_IN, and the hardreg could not be paired with + other hardreg to contain the outermode operand + (checked by in_hard_reg_set_p), we need to insert the reload. + 2. If the op_type is OP_OUT or OP_INOUT. */ + else if (REG_P (reg) + && REGNO (reg) >= FIRST_PSEUDO_REGISTER + && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 + && (hard_regno_nregs[hard_regno][GET_MODE (reg)] + < hard_regno_nregs[hard_regno][mode]) + && (regclass = lra_get_allocno_class (REGNO (reg))) + && (type != OP_IN + || !in_hard_reg_set_p (reg_class_contents[regclass], + mode, hard_regno))) + { + /* The class will be defined later in curr_insn_transform. */ + enum reg_class rclass + = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); + rtx subreg; + + new_reg = lra_create_new_reg_with_unique_value (mode, reg, rclass, + "paradoxical subreg"); + PUT_MODE (new_reg, mode); + subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0); + if (type != OP_OUT) + { + push_to_sequence (before); + lra_emit_move (subreg, reg); + before = get_insns (); + end_sequence (); + } + if (type != OP_IN) + { + start_sequence (); + lra_emit_move (reg, subreg); + emit_insn (after); + after = get_insns (); + end_sequence (); + } + SUBREG_REG (operand) = new_reg; + lra_process_new_insns (curr_insn, before, after, + "Inserting paradoxical subreg reload"); + return true; + } return false; } diff --git a/gcc-4.8/gcc/lto/ChangeLog b/gcc-4.8/gcc/lto/ChangeLog index e179310f1..c5d55780e 100644 --- a/gcc-4.8/gcc/lto/ChangeLog +++ b/gcc-4.8/gcc/lto/ChangeLog @@ -1,3 +1,7 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/mode-switching.c b/gcc-4.8/gcc/mode-switching.c index 2bcb154d2..5dd9627c3 100644 --- a/gcc-4.8/gcc/mode-switching.c +++ b/gcc-4.8/gcc/mode-switching.c @@ -568,12 +568,15 @@ optimize_mode_switching (void) info[bb->index].computing = last_mode; /* Check for blocks without ANY mode requirements. - N.B. because of MODE_AFTER, last_mode might still be different - from no_mode. */ + N.B. because of MODE_AFTER, last_mode might still + be different from no_mode, in which case we need to + mark the block as nontransparent. */ if (!any_set_required) { ptr = new_seginfo (no_mode, BB_END (bb), bb->index, live_now); add_seginfo (info + bb->index, ptr); + if (last_mode != no_mode) + bitmap_clear_bit (transp[bb->index], j); } } #if defined (MODE_ENTRY) && defined (MODE_EXIT) diff --git a/gcc-4.8/gcc/objc/ChangeLog b/gcc-4.8/gcc/objc/ChangeLog index 508874cec..c30ff7479 100644 --- a/gcc-4.8/gcc/objc/ChangeLog +++ b/gcc-4.8/gcc/objc/ChangeLog @@ -1,3 +1,18 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-04-07 Dominique d'Humieres + + Backport from mainline + 2013-09-14 Iain Sandoe + + PR target/48094 + * objc-next-runtime-abi-01.c (generate_objc_image_info): Remove. + (objc_generate_v1_next_metadata): Remove generation of ImageInfo. + * objc-next-runtime-abi-02.c (generate_v2_objc_image_info): Remove. + (objc_generate_v2_next_metadata): Remove generation of ImageInfo. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/objc/objc-next-runtime-abi-01.c b/gcc-4.8/gcc/objc/objc-next-runtime-abi-01.c index a9845cfc0..63af0e413 100644 --- a/gcc-4.8/gcc/objc/objc-next-runtime-abi-01.c +++ b/gcc-4.8/gcc/objc/objc-next-runtime-abi-01.c @@ -2332,36 +2332,6 @@ generate_classref_translation_entry (tree chain) return; } - -/* The Fix-and-Continue functionality available in Mac OS X 10.3 and - later requires that ObjC translation units participating in F&C be - specially marked. The following routine accomplishes this. */ - -/* static int _OBJC_IMAGE_INFO[2] = { 0, 1 }; */ - -static void -generate_objc_image_info (void) -{ - tree decl; - int flags - = ((flag_replace_objc_classes && imp_count ? 1 : 0) - | (flag_objc_gc ? 2 : 0)); - vec *v = NULL; - tree array_type; - - array_type = build_sized_array_type (integer_type_node, 2); - - decl = start_var_decl (array_type, "_OBJC_ImageInfo"); - - CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node); - CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags)); - /* The runtime wants this and refers to it in a manner hidden from the compiler. - So we must force the output. */ - DECL_PRESERVE_P (decl) = 1; - OBJCMETA (decl, objc_meta, meta_info); - finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v)); -} - static void objc_generate_v1_next_metadata (void) { @@ -2412,9 +2382,6 @@ objc_generate_v1_next_metadata (void) attr = build_tree_list (objc_meta, meta_modules); build_module_descriptor (vers, attr); - /* This conveys information on GC usage and zero-link. */ - generate_objc_image_info (); - /* Dump the class references. This forces the appropriate classes to be linked into the executable image, preserving unix archive semantics. */ diff --git a/gcc-4.8/gcc/objc/objc-next-runtime-abi-02.c b/gcc-4.8/gcc/objc/objc-next-runtime-abi-02.c index 8ce0c22d3..97d1b295e 100644 --- a/gcc-4.8/gcc/objc/objc-next-runtime-abi-02.c +++ b/gcc-4.8/gcc/objc/objc-next-runtime-abi-02.c @@ -3329,31 +3329,6 @@ build_v2_ivar_offset_ref_table (void) finish_var_decl (ref->decl, ref->offset); } -/* static int _OBJC_IMAGE_INFO[2] = { 0, 16 | flags }; */ - -static void -generate_v2_objc_image_info (void) -{ - tree decl, array_type; - vec *v = NULL; - int flags = - ((flag_replace_objc_classes && imp_count ? 1 : 0) - | (flag_objc_gc ? 2 : 0)); - - flags |= 16; - - array_type = build_sized_array_type (integer_type_node, 2); - - decl = start_var_decl (array_type, "_OBJC_ImageInfo"); - - CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, integer_zero_node); - CONSTRUCTOR_APPEND_ELT (v, NULL_TREE, build_int_cst (integer_type_node, flags)); - /* The Runtime wants this. */ - DECL_PRESERVE_P (decl) = 1; - OBJCMETA (decl, objc_meta, meta_info); - finish_var_decl (decl, objc_build_constructor (TREE_TYPE (decl), v)); -} - static void objc_generate_v2_next_metadata (void) { @@ -3405,9 +3380,6 @@ objc_generate_v2_next_metadata (void) build_v2_address_table (nonlazy_category_list, "_OBJC_NonLazyCategoryList$", meta_label_nonlazy_categorylist); - /* This conveys information on GC usage and zero-link. */ - generate_v2_objc_image_info (); - /* Generate catch objects for eh, if any are needed. */ build_v2_eh_catch_objects (); diff --git a/gcc-4.8/gcc/objcp/ChangeLog b/gcc-4.8/gcc/objcp/ChangeLog index 51c37e4a4..bc73f6131 100644 --- a/gcc-4.8/gcc/objcp/ChangeLog +++ b/gcc-4.8/gcc/objcp/ChangeLog @@ -1,3 +1,7 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/optabs.c b/gcc-4.8/gcc/optabs.c index a3051ad9d..dbf83076f 100644 --- a/gcc-4.8/gcc/optabs.c +++ b/gcc-4.8/gcc/optabs.c @@ -3376,7 +3376,8 @@ expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, { rtx temp; - if (! flag_trapv) + if (GET_MODE_CLASS (mode) != MODE_INT + || ! flag_trapv) result_unsignedp = 1; /* First try to do it with a special abs instruction. */ @@ -3399,7 +3400,8 @@ expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, { rtx last = get_last_insn (); - temp = expand_unop (mode, neg_optab, op0, NULL_RTX, 0); + temp = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, + op0, NULL_RTX, 0); if (temp != 0) temp = expand_binop (mode, smax_optab, op0, temp, target, 0, OPTAB_WIDEN); @@ -3441,7 +3443,8 @@ expand_abs (enum machine_mode mode, rtx op0, rtx target, { rtx temp, op1; - if (! flag_trapv) + if (GET_MODE_CLASS (mode) != MODE_INT + || ! flag_trapv) result_unsignedp = 1; temp = expand_abs_nojump (mode, op0, target, result_unsignedp); @@ -4558,8 +4561,11 @@ emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, if (!COMPARISON_P (comparison)) return NULL_RTX; - do_pending_stack_adjust (); + /* State variables we need to save and restore if cmove can't be used. */ + int save_pending_stack_adjust = pending_stack_adjust; + int save_stack_pointer_delta = stack_pointer_delta; last = get_last_insn (); + do_pending_stack_adjust (); prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, &comparison, &cmode); @@ -4579,6 +4585,8 @@ emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, } } delete_insns_since (last); + pending_stack_adjust = save_pending_stack_adjust; + stack_pointer_delta = save_stack_pointer_delta; return NULL_RTX; } @@ -6233,7 +6241,7 @@ init_tree_optimization_optabs (tree optnode) /* If the optabs changed, record it. */ if (memcmp (tmp_optabs, this_target_optabs, sizeof (struct target_optabs))) - TREE_OPTIMIZATION_OPTABS (optnode) = (unsigned char *) tmp_optabs; + TREE_OPTIMIZATION_OPTABS (optnode) = tmp_optabs; else { TREE_OPTIMIZATION_OPTABS (optnode) = NULL; @@ -7035,8 +7043,7 @@ maybe_emit_atomic_exchange (rtx target, rtx mem, rtx val, enum memmodel model) create_output_operand (&ops[0], target, mode); create_fixed_operand (&ops[1], mem); - /* VAL may have been promoted to a wider mode. Shrink it if so. */ - create_convert_operand_to (&ops[2], val, mode, true); + create_input_operand (&ops[2], val, mode); create_integer_operand (&ops[3], model); if (maybe_expand_insn (icode, 4, ops)) return ops[0].value; @@ -7075,8 +7082,7 @@ maybe_emit_sync_lock_test_and_set (rtx target, rtx mem, rtx val, struct expand_operand ops[3]; create_output_operand (&ops[0], target, mode); create_fixed_operand (&ops[1], mem); - /* VAL may have been promoted to a wider mode. Shrink it if so. */ - create_convert_operand_to (&ops[2], val, mode, true); + create_input_operand (&ops[2], val, mode); if (maybe_expand_insn (icode, 3, ops)) return ops[0].value; } @@ -7118,8 +7124,6 @@ maybe_emit_compare_and_swap_exchange_loop (rtx target, rtx mem, rtx val) { if (!target || !register_operand (target, mode)) target = gen_reg_rtx (mode); - if (GET_MODE (val) != VOIDmode && GET_MODE (val) != mode) - val = convert_modes (mode, GET_MODE (val), val, 1); if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX)) return target; } @@ -7331,8 +7335,8 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval, create_output_operand (&ops[0], target_bool, bool_mode); create_output_operand (&ops[1], target_oval, mode); create_fixed_operand (&ops[2], mem); - create_convert_operand_to (&ops[3], expected, mode, true); - create_convert_operand_to (&ops[4], desired, mode, true); + create_input_operand (&ops[3], expected, mode); + create_input_operand (&ops[4], desired, mode); create_integer_operand (&ops[5], is_weak); create_integer_operand (&ops[6], succ_model); create_integer_operand (&ops[7], fail_model); @@ -7353,8 +7357,8 @@ expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval, create_output_operand (&ops[0], target_oval, mode); create_fixed_operand (&ops[1], mem); - create_convert_operand_to (&ops[2], expected, mode, true); - create_convert_operand_to (&ops[3], desired, mode, true); + create_input_operand (&ops[2], expected, mode); + create_input_operand (&ops[3], desired, mode); if (!maybe_expand_insn (icode, 4, ops)) return false; diff --git a/gcc-4.8/gcc/opts.c b/gcc-4.8/gcc/opts.c index 7d95cc102..8fe2366cd 100644 --- a/gcc-4.8/gcc/opts.c +++ b/gcc-4.8/gcc/opts.c @@ -426,8 +426,8 @@ static const struct default_options default_options_table[] = { OPT_LEVELS_1_PLUS, OPT_fguess_branch_probability, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fcprop_registers, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fforward_propagate, NULL, 1 }, - { OPT_LEVELS_1_PLUS, OPT_fif_conversion, NULL, 1 }, - { OPT_LEVELS_1_PLUS, OPT_fif_conversion2, NULL, 1 }, + { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion, NULL, 1 }, + { OPT_LEVELS_1_PLUS_NOT_DEBUG, OPT_fif_conversion2, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fipa_pure_const, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fipa_reference, NULL, 1 }, { OPT_LEVELS_1_PLUS, OPT_fipa_profile, NULL, 1 }, diff --git a/gcc-4.8/gcc/params.def b/gcc-4.8/gcc/params.def index cb25def32..e51b847a7 100644 --- a/gcc-4.8/gcc/params.def +++ b/gcc-4.8/gcc/params.def @@ -1014,6 +1014,12 @@ DEFPARAM (PARAM_MAX_SLSR_CANDIDATE_SCAN, "strength reduction", 50, 1, 999999) +DEFPARAM (PARAM_UNINIT_CONTROL_DEP_ATTEMPTS, + "uninit-control-dep-attempts", + "Maximum number of nested calls to search for control dependencies " + "during uninitialized variable analysis", + 1000, 1, 0) + /* Local variables: mode:c diff --git a/gcc-4.8/gcc/passes.c b/gcc-4.8/gcc/passes.c index 4a7f8d2ae..844214dd0 100644 --- a/gcc-4.8/gcc/passes.c +++ b/gcc-4.8/gcc/passes.c @@ -1398,6 +1398,7 @@ init_optimization_passes (void) /* After CCP we rewrite no longer addressed locals into SSA form if possible. */ NEXT_PASS (pass_forwprop); + NEXT_PASS (pass_object_sizes); /* pass_build_alias is a dummy pass that ensures that we execute TODO_rebuild_alias at this point. */ NEXT_PASS (pass_build_alias); @@ -1435,7 +1436,6 @@ init_optimization_passes (void) NEXT_PASS (pass_dce); NEXT_PASS (pass_forwprop); NEXT_PASS (pass_phiopt); - NEXT_PASS (pass_object_sizes); NEXT_PASS (pass_strlen); NEXT_PASS (pass_ccp); /* After CCP we rewrite no longer addressed locals into SSA diff --git a/gcc-4.8/gcc/po/ChangeLog b/gcc-4.8/gcc/po/ChangeLog index a01b6cbdc..951c15d2f 100644 --- a/gcc-4.8/gcc/po/ChangeLog +++ b/gcc-4.8/gcc/po/ChangeLog @@ -1,3 +1,7 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + 2013-10-16 Release Manager * GCC 4.8.2 released. diff --git a/gcc-4.8/gcc/print-rtl.c b/gcc-4.8/gcc/print-rtl.c index 3793109aa..31e6fb5af 100644 --- a/gcc-4.8/gcc/print-rtl.c +++ b/gcc-4.8/gcc/print-rtl.c @@ -582,6 +582,8 @@ print_rtx (const_rtx in_rtx) if (MEM_EXPR (in_rtx)) print_mem_expr (outfile, MEM_EXPR (in_rtx)); + else + fputc (' ', outfile); if (MEM_OFFSET_KNOWN_P (in_rtx)) fprintf (outfile, "+" HOST_WIDE_INT_PRINT_DEC, MEM_OFFSET (in_rtx)); diff --git a/gcc-4.8/gcc/recog.c b/gcc-4.8/gcc/recog.c index f00859cf0..ad096301c 100644 --- a/gcc-4.8/gcc/recog.c +++ b/gcc-4.8/gcc/recog.c @@ -3061,6 +3061,9 @@ peep2_reg_dead_p (int ofs, rtx reg) return 1; } +/* Regno offset to be used in the register search. */ +static int search_ofs; + /* Try to find a hard register of mode MODE, matching the register class in CLASS_STR, which is available at the beginning of insn CURRENT_INSN and remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX, @@ -3076,7 +3079,6 @@ rtx peep2_find_free_register (int from, int to, const char *class_str, enum machine_mode mode, HARD_REG_SET *reg_set) { - static int search_ofs; enum reg_class cl; HARD_REG_SET live; df_ref *def_rec; @@ -3541,6 +3543,7 @@ peephole2_optimize (void) /* Initialize the regsets we're going to use. */ for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) peep2_insn_data[i].live_before = BITMAP_ALLOC (®_obstack); + search_ofs = 0; live = BITMAP_ALLOC (®_obstack); FOR_EACH_BB_REVERSE (bb) diff --git a/gcc-4.8/gcc/regcprop.c b/gcc-4.8/gcc/regcprop.c index 896902f30..8bfb64e40 100644 --- a/gcc-4.8/gcc/regcprop.c +++ b/gcc-4.8/gcc/regcprop.c @@ -747,6 +747,7 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) int n_ops, i, alt, predicated; bool is_asm, any_replacements; rtx set; + rtx link; bool replaced[MAX_RECOG_OPERANDS]; bool changed = false; struct kill_set_value_data ksvd; @@ -815,6 +816,23 @@ copyprop_hardreg_forward_1 (basic_block bb, struct value_data *vd) if (recog_op_alt[i][alt].earlyclobber) kill_value (recog_data.operand[i], vd); + /* If we have dead sets in the insn, then we need to note these as we + would clobbers. */ + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) + { + if (REG_NOTE_KIND (link) == REG_UNUSED) + { + kill_value (XEXP (link, 0), vd); + /* Furthermore, if the insn looked like a single-set, + but the dead store kills the source value of that + set, then we can no-longer use the plain move + special case below. */ + if (set + && reg_overlap_mentioned_p (XEXP (link, 0), SET_SRC (set))) + set = NULL; + } + } + /* Special-case plain move instructions, since we may well be able to do the move from a different register class. */ if (set && REG_P (SET_SRC (set))) diff --git a/gcc-4.8/gcc/reginfo.c b/gcc-4.8/gcc/reginfo.c index 0153cd9d8..3d08a9a70 100644 --- a/gcc-4.8/gcc/reginfo.c +++ b/gcc-4.8/gcc/reginfo.c @@ -85,7 +85,7 @@ static const char initial_call_really_used_regs[] = CALL_REALLY_USED_REGISTERS; char global_regs[FIRST_PSEUDO_REGISTER]; /* Declaration for the global register. */ -static tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER]; +tree global_regs_decl[FIRST_PSEUDO_REGISTER]; /* Same information as REGS_INVALIDATED_BY_CALL but in regset form to be used in dataflow more conveniently. */ @@ -620,40 +620,35 @@ choose_hard_reg_mode (unsigned int regno ATTRIBUTE_UNUSED, mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; - if (found_mode != VOIDmode) - return found_mode; - for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT); mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; - if (found_mode != VOIDmode) - return found_mode; - for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_FLOAT); mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; - if (found_mode != VOIDmode) - return found_mode; - for (mode = GET_CLASS_NARROWEST_MODE (MODE_VECTOR_INT); mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) if ((unsigned) hard_regno_nregs[regno][mode] == nregs && HARD_REGNO_MODE_OK (regno, mode) - && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))) + && (! call_saved || ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode)) + && GET_MODE_SIZE (mode) > GET_MODE_SIZE (found_mode)) found_mode = mode; if (found_mode != VOIDmode) diff --git a/gcc-4.8/gcc/reorg.c b/gcc-4.8/gcc/reorg.c index c19fb4c42..e7cb112b4 100644 --- a/gcc-4.8/gcc/reorg.c +++ b/gcc-4.8/gcc/reorg.c @@ -1105,6 +1105,7 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, int used_annul = 0; int i; struct resources cc_set; + bool *redundant; /* We can't do anything if there are more delay slots in SEQ than we can handle, or if we don't know that it will be a taken branch. @@ -1145,6 +1146,7 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, return delay_list; #endif + redundant = XALLOCAVEC (bool, XVECLEN (seq, 0)); for (i = 1; i < XVECLEN (seq, 0); i++) { rtx trial = XVECEXP (seq, 0, i); @@ -1166,7 +1168,8 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, /* If this insn was already done (usually in a previous delay slot), pretend we put it in our delay slot. */ - if (redundant_insn (trial, insn, new_delay_list)) + redundant[i] = redundant_insn (trial, insn, new_delay_list); + if (redundant[i]) continue; /* We will end up re-vectoring this branch, so compute flags @@ -1199,6 +1202,12 @@ steal_delay_list_from_target (rtx insn, rtx condition, rtx seq, return delay_list; } + /* Record the effect of the instructions that were redundant and which + we therefore decided not to copy. */ + for (i = 1; i < XVECLEN (seq, 0); i++) + if (redundant[i]) + update_block (XVECEXP (seq, 0, i), insn); + /* Show the place to which we will be branching. */ *pnew_thread = first_active_target_insn (JUMP_LABEL (XVECEXP (seq, 0, 0))); @@ -1262,6 +1271,7 @@ steal_delay_list_from_fallthrough (rtx insn, rtx condition, rtx seq, /* If this insn was already done, we don't need it. */ if (redundant_insn (trial, insn, delay_list)) { + update_block (trial, insn); delete_from_delay_slot (trial); continue; } @@ -3266,6 +3276,7 @@ relax_delay_slots (rtx first) to reprocess this insn. */ if (redundant_insn (XVECEXP (pat, 0, 1), delay_insn, 0)) { + update_block (XVECEXP (pat, 0, 1), insn); delete_from_delay_slot (XVECEXP (pat, 0, 1)); next = prev_active_insn (next); continue; @@ -3385,6 +3396,7 @@ relax_delay_slots (rtx first) && redirect_with_delay_slots_safe_p (delay_insn, target_label, insn)) { + update_block (XVECEXP (PATTERN (trial), 0, 1), insn); reorg_redirect_jump (delay_insn, target_label); next = insn; continue; diff --git a/gcc-4.8/gcc/rtl.h b/gcc-4.8/gcc/rtl.h index 93a64f4d8..91f3387c7 100644 --- a/gcc-4.8/gcc/rtl.h +++ b/gcc-4.8/gcc/rtl.h @@ -2705,6 +2705,8 @@ extern int canon_true_dependence (const_rtx, enum machine_mode, rtx, const_rtx, rtx); extern int read_dependence (const_rtx, const_rtx); extern int anti_dependence (const_rtx, const_rtx); +extern int canon_anti_dependence (const_rtx, bool, + const_rtx, enum machine_mode, rtx); extern int output_dependence (const_rtx, const_rtx); extern int may_alias_p (const_rtx, const_rtx); extern void init_alias_target (void); @@ -2789,6 +2791,8 @@ extern void _fatal_insn (const char *, const_rtx, const char *, int, const char #define fatal_insn_not_found(insn) \ _fatal_insn_not_found (insn, __FILE__, __LINE__, __FUNCTION__) +/* reginfo.c */ +extern tree GTY(()) global_regs_decl[FIRST_PSEUDO_REGISTER]; #endif /* ! GCC_RTL_H */ diff --git a/gcc-4.8/gcc/rtlanal.c b/gcc-4.8/gcc/rtlanal.c index b19868579..89455d361 100644 --- a/gcc-4.8/gcc/rtlanal.c +++ b/gcc-4.8/gcc/rtlanal.c @@ -224,10 +224,10 @@ rtx_varies_p (const_rtx x, bool for_alias) return 0; } -/* Return nonzero if the use of X as an address in a MEM can cause a trap. - MODE is the mode of the MEM (not that of X) and UNALIGNED_MEMS controls - whether nonzero is returned for unaligned memory accesses on strict - alignment machines. */ +/* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE + bytes can cause a trap. MODE is the mode of the MEM (not that of X) and + UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory + references on strict alignment machines. */ static int rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, @@ -235,11 +235,12 @@ rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, { enum rtx_code code = GET_CODE (x); - if (STRICT_ALIGNMENT - && unaligned_mems - && GET_MODE_SIZE (mode) != 0) + /* The offset must be a multiple of the mode size if we are considering + unaligned memory references on strict alignment machines. */ + if (STRICT_ALIGNMENT && unaligned_mems && GET_MODE_SIZE (mode) != 0) { HOST_WIDE_INT actual_offset = offset; + #ifdef SPARC_STACK_BOUNDARY_HACK /* ??? The SPARC port may claim a STACK_BOUNDARY higher than the real alignment of %sp. However, when it does this, the @@ -298,8 +299,27 @@ rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, return 0; case REG: - /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ - if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx + /* Stack references are assumed not to trap, but we need to deal with + nonsensical offsets. */ + if (x == frame_pointer_rtx) + { + HOST_WIDE_INT adj_offset = offset - STARTING_FRAME_OFFSET; + if (size == 0) + size = GET_MODE_SIZE (mode); + if (FRAME_GROWS_DOWNWARD) + { + if (adj_offset < frame_offset || adj_offset + size - 1 >= 0) + return 1; + } + else + { + if (adj_offset < 0 || adj_offset + size - 1 >= frame_offset) + return 1; + } + return 0; + } + /* ??? Need to add a similar guard for nonsensical offsets. */ + if (x == hard_frame_pointer_rtx || x == stack_pointer_rtx /* The arg pointer varies if it is not a fixed register. */ || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) @@ -320,9 +340,7 @@ rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1))) return 0; - /* - or it is an address that can't trap plus a constant integer, - with the proper remainder modulo the mode size if we are - considering unaligned memory references. */ + /* - or it is an address that can't trap plus a constant integer. */ if (CONST_INT_P (XEXP (x, 1)) && !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)), size, mode, unaligned_mems)) diff --git a/gcc-4.8/gcc/sdbout.c b/gcc-4.8/gcc/sdbout.c index 13c11c296..44bdf3ef0 100644 --- a/gcc-4.8/gcc/sdbout.c +++ b/gcc-4.8/gcc/sdbout.c @@ -1226,7 +1226,10 @@ static void sdbout_parms (tree parms) { for (; parms; parms = TREE_CHAIN (parms)) - if (DECL_NAME (parms)) + if (DECL_NAME (parms) + && TREE_TYPE (parms) != error_mark_node + && DECL_RTL_SET_P (parms) + && DECL_INCOMING_RTL (parms)) { int current_sym_value = 0; const char *name = IDENTIFIER_POINTER (DECL_NAME (parms)); @@ -1358,7 +1361,10 @@ static void sdbout_reg_parms (tree parms) { for (; parms; parms = TREE_CHAIN (parms)) - if (DECL_NAME (parms)) + if (DECL_NAME (parms) + && TREE_TYPE (parms) != error_mark_node + && DECL_RTL_SET_P (parms) + && DECL_INCOMING_RTL (parms)) { const char *name = IDENTIFIER_POINTER (DECL_NAME (parms)); diff --git a/gcc-4.8/gcc/sel-sched.c b/gcc-4.8/gcc/sel-sched.c index 11bf2e62c..71a01146c 100644 --- a/gcc-4.8/gcc/sel-sched.c +++ b/gcc-4.8/gcc/sel-sched.c @@ -1253,7 +1253,7 @@ mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p, if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) add_to_hard_reg_set (®_rename_p->unavailable_hard_regs, - Pmode, HARD_FRAME_POINTER_IS_FRAME_POINTER); + Pmode, HARD_FRAME_POINTER_REGNUM); } #ifdef STACK_REGS diff --git a/gcc-4.8/gcc/simplify-rtx.c b/gcc-4.8/gcc/simplify-rtx.c index 43e794ebd..d6b872b9f 100644 --- a/gcc-4.8/gcc/simplify-rtx.c +++ b/gcc-4.8/gcc/simplify-rtx.c @@ -639,11 +639,16 @@ simplify_truncation (enum machine_mode mode, rtx op, XEXP (op, 0), origmode); } - /* Simplify (truncate:SI (op:DI (x:DI) (y:DI))) - to (op:SI (truncate:SI (x:DI)) (truncate:SI (x:DI))). */ - if (GET_CODE (op) == PLUS + /* If the machine can perform operations in the truncated mode, distribute + the truncation, i.e. simplify (truncate:QI (op:SI (x:SI) (y:SI))) into + (op:QI (truncate:QI (x:SI)) (truncate:QI (y:SI))). */ + if (1 +#ifdef WORD_REGISTER_OPERATIONS + && precision >= BITS_PER_WORD +#endif + && (GET_CODE (op) == PLUS || GET_CODE (op) == MINUS - || GET_CODE (op) == MULT) + || GET_CODE (op) == MULT)) { rtx op0 = simplify_gen_unary (TRUNCATE, mode, XEXP (op, 0), op_mode); if (op0) diff --git a/gcc-4.8/gcc/stmt.c b/gcc-4.8/gcc/stmt.c index 7bdc9329b..ce90206f8 100644 --- a/gcc-4.8/gcc/stmt.c +++ b/gcc-4.8/gcc/stmt.c @@ -1602,19 +1602,28 @@ expand_nl_goto_receiver (void) #ifdef HAVE_nonlocal_goto if (! HAVE_nonlocal_goto) #endif + { /* First adjust our frame pointer to its actual value. It was previously set to the start of the virtual area corresponding to the stacked variables when we branched here and now needs to be adjusted to the actual hardware fp value. - Assignments are to virtual registers are converted by + Assignments to virtual registers are converted by instantiate_virtual_regs into the corresponding assignment to the underlying register (fp in this case) that makes the original assignment true. - So the following insn will actually be - decrementing fp by STARTING_FRAME_OFFSET. */ + So the following insn will actually be decrementing fp by + STARTING_FRAME_OFFSET. */ emit_move_insn (virtual_stack_vars_rtx, hard_frame_pointer_rtx); + /* Restoring the frame pointer also modifies the hard frame pointer. + Mark it used (so that the previous assignment remains live once + the frame pointer is eliminated) and clobbered (to represent the + implicit update from the assignment). */ + emit_use (hard_frame_pointer_rtx); + emit_clobber (hard_frame_pointer_rtx); + } + #if !HARD_FRAME_POINTER_IS_ARG_POINTER if (fixed_regs[ARG_POINTER_REGNUM]) { diff --git a/gcc-4.8/gcc/testsuite/ChangeLog b/gcc-4.8/gcc/testsuite/ChangeLog index 5a0b168ba..190837dc0 100644 --- a/gcc-4.8/gcc/testsuite/ChangeLog +++ b/gcc-4.8/gcc/testsuite/ChangeLog @@ -1,3 +1,1865 @@ +2014-05-22 Release Manager + + * GCC 4.8.3 released. + +2014-05-14 Matthias Klose + + PR driver/61106 + * gcc-dg/unused-8a.c: Remove. + +2014-05-13 Peter Bergner + + * lib/target-support.exp (check_dfp_hw_available): New function. + (is-effective-target): Check $arg for dfp_hw. + (is-effective-target-keyword): Likewise. + * gcc.target/powerpc/pack03.c: (dg-require-effective-target): + Change target to dfp_hw. + +2014-05-12 Senthil Kumar Selvaraj + + Backport from mainline + 2014-05-12 Senthil Kumar Selvaraj + + PR target/60991 + * gcc.target/avr/pr60991.c: New testcase. + +2014-05-09 Georg-Johann Lay + + Backport from 2014-05-09 trunk r210267 + + PR target/61055 + * gcc.target/avr/torture/pr61055.c: New test. + +2014-05-08 Matthias Klose + + PR driver/61106 + * gcc-dg/unused-8a.c: New. + * gcc-dg/unused-8b.c: Likewise. + +2014-05-07 Richard Biener + + PR tree-optimization/57864 + * gcc.dg/torture/pr57864.c: New testcase. + +2014-05-06 Richard Biener + + Backport from mainline + 2014-04-14 Richard Biener + + PR middle-end/55022 + * gcc.dg/graphite/pr55022.c: New testcase. + +2014-05-06 Richard Biener + + Backport from mainline + 2014-04-17 Richard Biener + + PR middle-end/60849 + * g++.dg/opt/pr60849.C: New testcase. + + 2014-04-07 Richard Biener + + PR tree-optimization/60766 + * gcc.dg/torture/pr60766.c: New testcase. + + 2014-04-23 Richard Biener + + PR tree-optimization/60903 + * gcc.dg/torture/pr60903.c: New testcase. + +2014-05-05 Richard Biener + + Backport from mainline + 2014-04-23 Richard Biener + + PR middle-end/60895 + * g++.dg/torture/pr60895.C: New testcase. + + 2014-04-07 Richard Biener + + PR middle-end/60750 + * g++.dg/torture/pr60750.C: New testcase. + * gcc.dg/tree-ssa/20040517-1.c: Adjust. + + 2014-04-14 Richard Biener + + PR tree-optimization/59817 + PR tree-optimization/60453 + * gfortran.dg/graphite/pr59817.f: New testcase. + * gcc.dg/graphite/pr59817-1.c: Likewise. + * gcc.dg/graphite/pr59817-2.c: Likewise. + + 2014-04-17 Richard Biener + + PR tree-optimization/60836 + * g++.dg/vect/pr60836.cc: New testcase. + +2014-05-05 Jakub Jelinek + + Backported from mainline + 2014-04-25 Jakub Jelinek + + PR tree-optimization/60960 + * gcc.c-torture/execute/pr60960.c: New test. + +2014-05-04 Peter Bergner + + * gcc.target/powerpc/pack02.c (dg-options): Add -mhard-float. + (dg-require-effective-target): Change target to powerpc_fprs. + * gcc.target/powerpc/pack03.c (dg-options): Add -mhard-dfp. + (dg-require-effective-target): Change target to dfprt. + +2014-05-02 Bill Schmidt + + PR tree-optimization/60930 + * gcc.dg/torture/pr60930.c: New test. + +2014-04-30 Michael Meissner + + Back port from mainline + 2014-04-24 Michael Meissner + + * gcc.target/powerpc/pack01.c: New test to test the new pack and + unpack builtin functionss for 128-bit types. + * gcc.target/powerpc/pack02.c: Likewise. + * gcc.target/powerpc/pack03.c: Likewise. + * gcc.target/powerpc/extend-divide-1.c: New test to test extended + divide builtin functionss. + * gcc.target/powerpc/extend-divide-2.c: Likewise. + * gcc.target/powerpc/bcd-1.c: New test for the new BCD builtin + functions. + * gcc.target/powerpc/bcd-2.c: Likewise. + * gcc.target/powerpc/bcd-3.c: Likewise. + * gcc.target/powerpc/dfp-builtin-1.c: New test for the new DFP + builtin functionss. + * gcc.target/powerpc/dfp-builtin-2.c: Likewise. + +2014-04-29 Pat Haugen + + Backport from mainline + 2014-04-17 Pat Haugen + + * gcc.target/powerpc/ti_math1.c: New. + * gcc.target/powerpc/ti_math2.c: New. + +2014-04-25 Eric Botcazou + + * gcc.c-torture/execute/20140425-1.c: New test. + +2014-04-23 Michael Meissner + + Back port from main line: + 2014-03-27 Michael Meissner + + * gcc.target/powerpc/p8vector-vbpermq.c: New test to test the + vbpermq builtin. + +2014-04-23 Uros Bizjak + + Backport from mainline + 2014-04-21 Uros Bizjak + + PR target/60909 + * gcc.target/i386/pr60909-1.c: New test. + * gcc.target/i386/pr60909-2.c: Ditto. + +2014-04-23 Richard Biener + + Backport from mainline + 2014-04-02 Richard Biener + + PR middle-end/60729 + * g++.dg/vect/pr60729.cc: New testcase. + + 2014-04-03 Richard Biener + + PR tree-optimization/60740 + * gcc.dg/graphite/pr60740.c: New testcase. + +2014-04-23 Richard Biener + + PR middle-end/60635 + * gfortran.dg/lto/pr60635_0.f90: New testcase. + * gfortran.dg/lto/pr60635_1.c: Likewise. + +2014-04-21 Michael Meissner + + Back port from the trunk, subversion id 209546. + + 2014-04-21 Michael Meissner + + PR target/60735 + * gcc.target/powerpc/pr60735.c: New test. Insure _Decimal64 does + not cause errors if -mspe. + +2014-04-17 Bill Schmidt + + * gcc.dg/vmx/merge-vsx.c: Add V4SI and V4SF tests. + * gcc.dg/vmx/merge-vsx-be-order.c: Likewise. + +2014-04-12 Jerry DeLisle + + Backport from mainline + PR libfortran/60810 + * gfortran.dg/arrayio_13.f90: New test. + +2014-04-11 Hans-Peter Nilsson + + * gfortran.dg/fmt_en.f90: Gate test on effective_target + fd_truncate. + +2014-04-11 Andreas Krebbel + + * gcc.target/s390/htm-nofloat-1.c: Rename to ... + * gcc.target/s390/htm-nofloat-compile-1.c: ... this one. + * gcc.target/s390/htm-nofloat-2.c: Add check for htm target and + rename to ... + * gcc.target/s390/htm-nofloat-1.c: ... this one. + * gcc.target/s390/s390.exp: Make sure the assembler supports htm + instructions as well. + +2014-04-11 Andreas Krebbel + + * gcc.target/s390/htm-builtins-compile-1.c: Replace long long with + long. + +2014-04-11 Andreas Krebbel + + * gcc.target/s390/htm-builtins-compile-1.c: Remove htm check. + * gcc.target/s390/htm-builtins-compile-2.c: Remove htm check. + +2014-04-10 Vladimir Makarov + + PR rtl-optimization/60769 + * g++.dg/pr60769.C: New. + +2014-04-10 Jakub Jelinek + + Backport from mainline + 2014-03-12 Jakub Jelinek + Marc Glisse + + PR tree-optimization/60502 + * gcc.c-torture/compile/pr60502.c: New test. + + 2014-03-28 Jakub Jelinek + + PR target/60693 + * gcc.target/i386/pr60693.c: New test. + + PR c++/60689 + * c-c++-common/pr60689.c: New test. + + 2014-03-22 Jakub Jelinek + + PR debug/60603 + * gcc.dg/debug/dwarf2/dwarf2-macro2.c: New test. + + 2014-03-17 Jakub Jelinek + + PR target/60516 + * gcc.target/i386/pr60516.c: New test. + + 2014-03-13 Jakub Jelinek + + PR middle-end/36282 + * c-c++-common/pr36282-1.c: New test. + * c-c++-common/pr36282-2.c: New test. + * c-c++-common/pr36282-3.c: New test. + * c-c++-common/pr36282-4.c: New test. + + 2014-03-06 Jakub Jelinek + + PR target/58595 + * gcc.dg/tls/pr58595.c: New test. + +2014-04-07 Martin Jambor + + PR ipa/60640 + * g++.dg/ipa/pr60640-1.C: New test. + * g++.dg/ipa/pr60640-2.C: Likewise. + * g++.dg/ipa/pr60640-3.C: Likewise. + +2014-04-06 Dominique d'Humieres + Iain Sandoe + + PR target/54083 + * gcc.dg/attr-weakref-1.c: Allow the test on darwin with + the additional options -Wl,-undefined,dynamic_lookup and + -Wl,-flat_namespace + * gcc.dg/torture/pr53922.c: Additional option + -Wl,-flat_namespace for darwin[89]. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-04-05 David Edelsohn + + * gcc.target/powerpc/sd-vsx.c: Skip on AIX. + * gcc.target/powerpc/sd-pwr6.c: Same. + +2014-04-04 Bill Schmidt + + Back port from trunk + 2014-03-12 Michael Meissner + + * gcc.target/powerpc/p8vector-int128-1.c: New test to test ISA + 2.07 128-bit arithmetic. + * gcc.target/powerpc/p8vector-int128-2.c: Likewise. + + * gcc.target/powerpc/timode_off.c: Restrict cpu type to power5, + due to when TImode is allowed in VSX registers, the allowable + address modes for TImode is just a single indirect address in + order for the value to be loaded and store in either GPR or VSX + registers. This affects the generated code, and it would cause + this test to fail, when such an option is used. + +2014-04-04 Bill Schmidt + + Backport from mainline r207699. + 2014-02-11 Michael Meissner + + PR target/60137 + * gcc.target/powerpc/pr60137.c: New file. + + Backport from mainline r207808. + 2014-02-15 Michael Meissner + + PR target/60203 + * gcc.target/powerpc/pr60203.c: New testsuite. + +2014-04-04 Bill Schmidt + + Little Endian Vector API Support + Backport from mainline r206590 + 2014-01-13 Bill Schmidt + + * gcc.dg/vmx/insert.c: New. + * gcc.dg/vmx/insert-be-order.c: New. + * gcc.dg/vmx/extract.c: New. + * gcc.dg/vmx/extract-be-order.c: New. + + Backport from mainline r206641 + 2014-01-15 Bill Schmidt + + * gcc.dg/vmx/mult-even-odd.c: New. + * gcc.dg/vmx/mult-even-odd-be-order.c: New. + + Backport from mainline r206926 + 2014-01-22 Bill Schmidt + + * gcc.dg/vmx/insert-vsx-be-order.c: New. + * gcc.dg/vmx/extract-vsx.c: New. + * gcc.dg/vmx/extract-vsx-be-order.c: New. + * gcc.dg/vmx/insert-vsx.c: New. + + Backport from mainline r207262 + 2014-01-29 Bill Schmidt + + * gcc.dg/vmx/merge-be-order.c: New. + * gcc.dg/vmx/merge.c: New. + * gcc.dg/vmx/merge-vsx-be-order.c: New. + * gcc.dg/vmx/merge-vsx.c: New. + + Backport from mainline r207318 + 2014-01-30 Bill Schmidt + + * gcc.dg/vmx/splat.c: New. + * gcc.dg/vmx/splat-vsx.c: New. + * gcc.dg/vmx/splat-be-order.c: New. + * gcc.dg/vmx/splat-vsx-be-order.c: New. + * gcc.dg/vmx/eg-5.c: Remove special casing for little endian. + * gcc.dg/vmx/sn7153.c: Add special casing for little endian. + + Backport from mainline r207414 + 2014-02-02 Bill Schmidt + + * gcc.dg/vmx/vsums.c: New. + * gcc.dg/vmx/vsums-be-order.c: New. + + Backport from mainline r207415 + 2014-02-02 Bill Schmidt + + * gcc.dg/vmx/3b-15.c: Remove special handling for little endian. + * gcc.dg/vmx/perm.c: New. + * gcc.dg/vmx/perm-be-order.c: New. + + Backport from mainline r207520 + 2014-02-05 Bill Schmidt + + * gcc.dg/vmx/pack.c: New. + * gcc.dg/vmx/pack-be-order.c: New. + * gcc.dg/vmx/unpack.c: New. + * gcc.dg/vmx/unpack-be-order.c: New. + + Backport from mainline r207521 + 2014-02-05 Bill Schmidt + + * gcc.dg/vmx/sum2s.c: New. + * gcc.dg/vmx/sum2s-be-order.c: New. + + Backport from mainline 208019 + 2014-02-21 Bill Schmidt + + * gcc.dg/vmx/ld.c: New test. + * gcc.dg/vmx/ld-be-order.c: New test. + * gcc.dg/vmx/ld-vsx.c: New test. + * gcc.dg/vmx/ld-vsx-be-order.c: New test. + * gcc.dg/vmx/ldl.c: New test. + * gcc.dg/vmx/ldl-be-order.c: New test. + * gcc.dg/vmx/ldl-vsx.c: New test. + * gcc.dg/vmx/ldl-vsx-be-order.c: New test. + * gcc.dg/vmx/st.c: New test. + * gcc.dg/vmx/st-be-order.c: New test. + * gcc.dg/vmx/st-vsx.c: New test. + * gcc.dg/vmx/st-vsx-be-order.c: New test. + * gcc.dg/vmx/stl.c: New test. + * gcc.dg/vmx/stl-be-order.c: New test. + * gcc.dg/vmx/stl-vsx.c: New test. + * gcc.dg/vmx/stl-vsx-be-order.c: New test. + + Backport from mainline 208021 + 2014-02-21 Bill Schmidt + + * gcc.dg/vmx/vsums.c: Check entire result vector. + * gcc.dg/vmx/vsums-be-order.c: Likewise. + + Backport from mainline 208049 + 2014-02-23 Bill Schmidt + + * gcc.dg/vmx/lde.c: New test. + * gcc.dg/vmx/lde-be-order.c: New test. + * gcc.dg/vmx/ste.c: New test. + * gcc.dg/vmx/ste-be-order.c: New test. + + Backport from mainline 208120 + 2014-02-25 Bill Schmidt + + * gcc.dg/vmx/ld-vsx.c: Don't use vec_all_eq. + * gcc.dg/vmx/ld-vsx-be-order.c: Likewise. + * gcc.dg/vmx/ldl-vsx.c: Likewise. + * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise. + * gcc.dg/vmx/merge-vsx.c: Likewise. + * gcc.dg/vmx/merge-vsx-be-order.c: Likewise. + + Backport from mainline 208321 + 2014-03-04 Bill Schmidt + + * gcc.dg/vmx/extract-vsx.c: Replace "vector long" with "vector + long long" throughout. + * gcc.dg/vmx/extract-vsx-be-order.c: Likewise. + * gcc.dg/vmx/insert-vsx.c: Likewise. + * gcc.dg/vmx/insert-vsx-be-order.c: Likewise. + * gcc.dg/vmx/ld-vsx.c: Likewise. + * gcc.dg/vmx/ld-vsx-be-order.c: Likewise. + * gcc.dg/vmx/ldl-vsx.c: Likewise. + * gcc.dg/vmx/ldl-vsx-be-order.c: Likewise. + * gcc.dg/vmx/merge-vsx.c: Likewise. + * gcc.dg/vmx/merge-vsx-be-order.c: Likewise. + * gcc.dg/vmx/st-vsx.c: Likewise. + * gcc.dg/vmx/st-vsx-be-order.c: Likewise. + * gcc.dg/vmx/stl-vsx.c: Likewise. + * gcc.dg/vmx/stl-vsx-be-order.c: Likewise. + +2014-04-04 Bill Schmidt + + Back port from mainline + 2014-01-23 Michael Meissner + + PR target/59909 + * gcc.target/powerpc/quad-atomic.c: New file to test power8 quad + word atomic functions at runtime. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-10-23 Pat Haugen + + * gcc.target/powerpc/direct-move.h: Fix header for executable tests. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-04-05 Bill Schmidt + + PR target/56843 + * gcc.target/powerpc/recip-1.c: Modify expected output. + * gcc.target/powerpc/recip-3.c: Likewise. + * gcc.target/powerpc/recip-4.c: Likewise. + * gcc.target/powerpc/recip-5.c: Add expected output for iterations. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-08-19 Peter Bergner + + * gcc.target/powerpc/dfp-dd-2.c: New test. + * gcc.target/powerpc/dfp-td-2.c: Likewise. + * gcc.target/powerpc/dfp-td-3.c: Likewise. + +2014-04-04 Bill Schmidt + + ELFv2 ABI Support + Backport from mainline r204808: + + 2013-11-14 Ulrich Weigand + + * gcc.target/powerpc/ppc64-abi-1.c (stack_frame_t): Remove + compiler and linker field if _CALL_ELF == 2. + * gcc.target/powerpc/ppc64-abi-2.c (stack_frame_t): Likewise. + * gcc.target/powerpc/ppc64-abi-dfp-1.c (stack_frame_t): Likewise. + * gcc.dg/stack-usage-1.c (SIZE): Update value for _CALL_ELF == 2. + + 2013-11-14 Ulrich Weigand + + * gcc.target/powerpc/ppc64-abi-dfp-1.c (FUNC_START): New macro. + (WRAPPER): Use it. + * gcc.target/powerpc/no-r11-1.c: Skip on powerpc_elfv2. + * gcc.target/powerpc/no-r11-2.c: Skip on powerpc_elfv2. + * gcc.target/powerpc/no-r11-3.c: Skip on powerpc_elfv2. + + 2013-11-14 Ulrich Weigand + + * lib/target-supports.exp (check_effective_target_powerpc_elfv2): + New function. + * gcc.target/powerpc/pr57949-1.c: Disable for powerpc_elfv2. + * gcc.target/powerpc/pr57949-2.c: Likewise. + + Backport from mainline r204799: + + 2013-11-14 Ulrich Weigand + + * g++.dg/eh/ppc64-sighandle-cr.C: New test. + +2014-04-04 Bill Schmidt + + Backport from mainline r201750. + Note: Default setting of -mcompat-align-parm inverted! + + 2013-08-14 Bill Schmidt + + PR target/57949 + * gcc.target/powerpc/pr57949-1.c: New. + * gcc.target/powerpc/pr57949-2.c: New. + +2014-04-04 Bill Schmidt + + Little Endian Vector Support + Backport from mainline r205638 + 2013-12-03 Bill Schmidt + + * gcc.dg/vect/costmodel/ppc/costmodel-slp-34.c: Skip for little + endian. + + Backport from mainline r205146 + 2013-11-20 Bill Schmidt + + * gcc.target/powerpc/pr48258-1.c: Skip for little endian. + + Backport from mainline r204862 + 2013-11-15 Bill Schmidt + + * gcc.dg/vmx/3b-15.c: Revise for little endian. + + Backport from mainline r204321 + 2013-11-02 Bill Schmidt + + * gcc.dg/vmx/vec-set.c: New. + + Backport from mainline r204138 + 2013-10-28 Bill Schmidt + + * gcc.dg/vmx/gcc-bug-i.c: Add little endian variant. + * gcc.dg/vmx/eg-5.c: Likewise. + + Backport from mainline r203930 + 2013-10-22 Bill Schmidt + + * gcc.target/powerpc/altivec-perm-1.c: Move the two vector pack + tests into... + * gcc.target/powerpc/altivec-perm-3.c: ...this new test, which is + restricted to big-endian targets. + + Backport from mainline r203246 + 2013-10-07 Bill Schmidt + + * gcc.target/powerpc/pr43154.c: Skip for ppc64 little endian. + * gcc.target/powerpc/fusion.c: Likewise. + +2014-04-04 Bill Schmidt + + Backport from mainline + 2013-11-27 Bill Schmidt + + * gfortran.dg/nan_7.f90: Disable for little endian PowerPC. + + Backport from mainline r205106: + + 2013-11-20 Ulrich Weigand + + * gcc.target/powerpc/darwin-longlong.c (msw): Make endian-safe. + + Backport from mainline r205046: + + 2013-11-19 Ulrich Weigand + + * gcc.target/powerpc/ppc64-abi-2.c (MAKE_SLOT): New macro to + construct parameter slot value in endian-independent way. + (fcevv, fciievv, fcvevv): Use it. + +2014-04-04 Bill Schmidt + + Power8 HTM Support + Backport from mainline + * lib/target-supports.exp (check_effective_target_powerpc_htm_ok): New + function to test if HTM is available. + * gcc.target/powerpc/htm-xl-intrin-1.c: New test. + * gcc.target/powerpc/htm-builtin-1.c: New test. + +2014-04-04 Bill Schmidt + + Power8 Base Support + Backport from mainline + 2013-11-22 Michael Meissner + + PR target/59054 + * gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to + specify an appropriate register class for VSX operations. + (load_vsx): Use it. + (load_gpr_to_vsx): Likewise. + (load_vsx_to_gpr): Likewise. + * gcc.target/powerpc/direct-move-vint1.c: Use an appropriate + register class for VSX registers that the type can handle. Remove + checks for explicit number of instructions generated, just check + if the instruction is generated. + * gcc.target/powerpc/direct-move-vint2.c: Likewise. + * gcc.target/powerpc/direct-move-float1.c: Likewise. + * gcc.target/powerpc/direct-move-float2.c: Likewise. + * gcc.target/powerpc/direct-move-double1.c: Likewise. + * gcc.target/powerpc/direct-move-double2.c: Likewise. + * gcc.target/powerpc/direct-move-long1.c: Likewise. + * gcc.target/powerpc/direct-move-long2.c: Likewise. + + * gcc.target/powerpc/bool3-av.c: Limit to 64-bit mode for now. + * gcc.target/powerpc/bool3-p7.c: Likewise. + * gcc.target/powerpc/bool3-p8.c: Likewise. + + * gcc.target/powerpc/p8vector-ldst.c: Just check that the + appropriate instructions are generated, don't check the count. + + 2013-11-12 Michael Meissner + + PR target/59054 + * gcc.target/powerpc/pr59054.c: New test. + + 2013-08-22 Michael Meissner + + * gcc.target/powerpc/pr57744.c: Declare abort. + + 2013-07-18 Pat Haugen + + * gcc.target/powerpc/pr57744.c: Fix typo. + + Back port from mainline + 2013-10-03 Michael Meissner + + * gcc.target/powerpc/p8vector-fp.c: New test for floating point + scalar operations when using -mupper-regs-sf and -mupper-regs-df. + * gcc.target/powerpc/ppc-target-1.c: Update tests to allow either + VSX scalar operations or the traditional floating point form of + the instruction. + * gcc.target/powerpc/ppc-target-2.c: Likewise. + * gcc.target/powerpc/recip-3.c: Likewise. + * gcc.target/powerpc/recip-5.c: Likewise. + * gcc.target/powerpc/pr72747.c: Likewise. + * gcc.target/powerpc/vsx-builtin-3.c: Likewise. + + Back port from mainline + 2013-09-27 Michael Meissner + + * gcc.target/powerpc/p8vector-ldst.c: New test for -mupper-regs-sf + and -mupper-regs-df. + + Back port from mainline + 2013-10-17 Michael Meissner + + PR target/58673 + * gcc.target/powerpc/pr58673-1.c: New file to test whether + -mquad-word + -mno-vsx-timode causes errors. + * gcc.target/powerpc/pr58673-2.c: Likewise. + + + Backport from trunk. + 2013-07-23 Michael Meissner + + * gcc.target/powerpc/bool2.h: New file, test the code generation + of logical operations for power5, altivec, power7, and power8 systems. + * gcc.target/powerpc/bool2-p5.c: Likewise. + * gcc.target/powerpc/bool2-av.c: Likewise. + * gcc.target/powerpc/bool2-p7.c: Likewise. + * gcc.target/powerpc/bool2-p8.c: Likewise. + * gcc.target/powerpc/bool3.h: Likewise. + * gcc.target/powerpc/bool3-av.c: Likewise. + * gcc.target/powerpc/bool2-p7.c: Likewise. + * gcc.target/powerpc/bool2-p8.c: Likewise. + + Backport from trunk. + 2013-07-31 Michael Meissner + + * gcc.target/powerpc/fusion.c: New file, test power8 fusion support. + + Back port from the trunk + 2013-06-28 Michael Meissner + + PR target/57744 + * gcc.target/powerpc/pr57744.c: New test to make sure lqarx and + stqcx. get even registers. + + Back port from the trunk + + 2013-06-12 Michael Meissner + Pat Haugen + Peter Bergner + + * gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic + load/store instructions on power7, power8. + * gcc.target/powerpc/atomic-p8.c: Likewise. + + Back port from the trunk + + 2013-06-10 Michael Meissner + Pat Haugen + Peter Bergner + + * gcc.target/powerpc/direct-move-vint1.c: New tests for power8 + direct move instructions. + * gcc.target/powerpc/direct-move-vint2.c: Likewise. + * gcc.target/powerpc/direct-move.h: Likewise. + * gcc.target/powerpc/direct-move-float1.c: Likewise. + * gcc.target/powerpc/direct-move-float2.c: Likewise. + * gcc.target/powerpc/direct-move-double1.c: Likewise. + * gcc.target/powerpc/direct-move-double2.c: Likewise. + * gcc.target/powerpc/direct-move-long1.c: Likewise. + * gcc.target/powerpc/direct-move-long2.c: Likewise. + + Backport from the trunk + + 2013-06-06 Michael Meissner + Pat Haugen + Peter Bergner + + * gcc.target/powerpc/p8vector-builtin-1.c: New test to test + power8 builtin functions. + * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-2.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-3.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-4.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-5.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-6.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-builtin-7.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-1.c: New + tests to test power8 auto-vectorization. + * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-2.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-3.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-4.c: Likewise. + * gcc/testsuite/gcc.target/powerpc/p8vector-vectorize-5.c: Likewise. + + * gcc.target/powerpc/crypto-builtin-1.c: Use effective target + powerpc_p8vector_ok instead of powerpc_vsx_ok. + + * gcc.target/powerpc/bool.c: New file, add eqv, nand, nor tests. + + * lib/target-supports.exp (check_p8vector_hw_available) Add power8 + support. + (check_effective_target_powerpc_p8vector_ok): Likewise. + (is-effective-target): Likewise. + (check_vect_support_and_set_flags): Likewise. + + Backport from trunk + + 2013-05-22 Michael Meissner + Pat Haugen + Peter Bergner + + * gcc.target/powerpc/crypto-builtin-1.c: New file, test for power8 + crypto builtins. + + Backport from mainline + 2013-03-20 Michael Meissner + + * gcc.target/powerpc/mmfpgpr.c: New test. + * gcc.target/powerpc/sd-vsx.c: Likewise. + * gcc.target/powerpc/sd-pwr6.c: Likewise. + * gcc.target/powerpc/vsx-float0.c: Likewise. + +2014-04-01 Dominique d'Humieres + + PR libfortran/60128 + * gfortran.dg/fmt_en.f90: Skip unsupported rounding tests. + XFAIL for i?86-*-solaris2.9* and hppa*-*-hpux*. + +2014-03-31 H.J. Lu + + Backport from mainline + 2014-03-31 H.J. Lu + + PR rtl-optimization/60700 + * gcc.target/i386/pr60700.c: New test. + +2014-03-28 H.J. Lu + + PR rtl-optimization/60700 + Backport from mainline + 2013-07-30 Zhenqiang Chen + + * gcc.target/arm/pr57637.c: New testcase. + +2014-04-28 Thomas Koenig + + PR fortran/60522 + * gfortran.dg/where_4.f90: New test case. + +2014-03-26 Martin Jambor + + PR ipa/60419 + * g++.dg/ipa/pr60419.C: New test. + +2014-03-26 Eric Botcazou + + * gcc.c-torture/execute/20140326-1.c: New test. + +2014-03-20 Tobias Burnus + + PR fortran/60543 + PR fortran/60283 + * gfortran.dg/implicit_pure_4.f90: New. + +2014-03-17 Mikael Pettersson + Committed by Bill Schmidt + + Backport from mainline: + + 2013-06-16 Joern Rennecke + + PR rtl-optimization/57425 + PR rtl-optimization/57569 + * gcc.dg/torture/pr57425-1.c, gcc.dg/torture/pr57425-2.c: New files. + * gcc.dg/torture/pr57425-3.c, gcc.dg/torture/pr57569.c: Likewise. + +2014-03-17 Richard Biener + + Backport from mainline + 2014-03-11 Richard Biener + + PR tree-optimization/60429 + PR tree-optimization/60485 + * gcc.dg/pr60485-1.c: New testcase. + * gcc.dg/pr60485-2.c: Likewise. + +2014-03-15 Dominique d'Humieres + + Backport from mainline + PR libfortran/60128 + * gfortran.dg/fmt_en.f90: New test. + +2014-03-15 Jerry DeLisle + + Backport from mainline + PR libfortran/58324 + * gfortran.dg/list_read_12.f90: New test. + +2014-03-13 Joey Ye + + Backport from mainline + 2014-03-12 Thomas Preud'homme + + PR tree-optimization/60454 + * gcc.c-torture/execute/pr60454.c: New test. + +2014-03-08 Janus Weil + + PR fortran/60450 + * gfortran.dg/shape_8.f90: New. + +2014-03-06 Jakub Jelinek + + Backport from mainline + 2014-02-19 Jakub Jelinek + + PR c/37743 + * g++.dg/ext/builtin-bswap1.C: New test. + * c-c++-common/pr37743.c: New test. + + PR preprocessor/58844 + * c-c++-common/cpp/pr58844-1.c: New test. + * c-c++-common/cpp/pr58844-2.c: New test. + + 2014-02-13 Jakub Jelinek + + PR target/43546 + * gcc.target/i386/pr43546.c: New test. + + 2014-02-12 Jakub Jelinek + + PR c/60101 + * c-c++-common/pr60101.c: New test. + + 2014-02-11 Jakub Jelinek + + PR fortran/52370 + * gfortran.dg/pr52370.f90: New test. + + PR debug/59776 + * gcc.dg/guality/pr59776.c: New test. + + 2014-02-07 Jakub Jelinek + + PR preprocessor/56824 + * gcc.dg/pr56824.c: New test. + + 2014-02-06 Jakub Jelinek + + PR target/60062 + * gcc.c-torture/execute/pr60062.c: New test. + * gcc.c-torture/execute/pr60072.c: New test. + + 2014-02-04 Jakub Jelinek + + PR ipa/60026 + * c-c++-common/torture/pr60026.c: New test. + + 2014-02-05 Jakub Jelinek + + PR middle-end/57499 + * g++.dg/torture/pr57499.C: New test. + + 2014-03-03 Jakub Jelinek + + PR preprocessor/60400 + * c-c++-common/cpp/pr60400.c: New test. + * c-c++-common/cpp/pr60400-1.h: New file. + * c-c++-common/cpp/pr60400-2.h: New file. + +2014-03-04 Richard Biener + + PR tree-optimization/60382 + * gcc.dg/vect/pr60382.c: New testcase. + +2014-03-02 Mikael Morin + + PR fortran/60341 + * gfortran.dg/str_comp_optimize_1.f90: New test. + +2014-02-25 Richard Biener + + Backport from mainline + 2014-02-21 Richard Biener + + PR tree-optimization/60276 + * gcc.dg/vect/pr60276.c: New testcase. + +2014-02-25 Richard Biener + + Backport from mainline + 2014-02-14 Richard Biener + + PR tree-optimization/60183 + * gcc.dg/torture/pr60183.c: New testcase. + +2014-02-24 Fabien Chêne + + PR c++/37140 + * g++.dg/template/using27.C: New. + * g++.dg/template/using28.C: New. + * g++.dg/template/using29.C: New. + +2014-02-23 David Holsgrove + + * gcc/testsuite/gcc.target/microblaze/others/mem_reload.c: New test. + +2014-02-22 Mikael Morin + + PR fortran/59599 + * gfortran.dg/ichar_3.f90: New test. + +2014-02-21 Steven G. Kargl + + Backport from mainline + PR fortran/59700 + * gfortran.dg/pr59700.f90: New test. + +2014-02-21 Martin Jambor + + PR ipa/55260 + * gcc.dg/ipa/pr55260.c: New test. + +2014-02-19 Tobias Burnus + + PR fortran/49397 + * gfortran.dg/proc_ptr_45.f90: New. + * gfortran.dg/proc_ptr_46.f90: New. + +2014-02-19 Uros Bizjak + + Backport from mainline + 2014-02-19 Uros Bizjak + + PR target/59794 + * gcc.target/i386/pr39162.c: Add dg-prune-output. + (dg-options): Remove -Wno-psabi. + * gcc.target/i386/pr59794-2.c: Ditto. + * gcc.target/i386/sse-5.c: Ditto. + +2014-02-19 Janus Weil + + Backports from mainline: + 2014-02-17 Janus Weil + + PR fortran/55907 + * gfortran.dg/init_flag_12.f90: New. + + 2014-02-18 Janus Weil + + PR fortran/60231 + * gfortran.dg/typebound_generic_15.f90: New. + +2014-02-18 Kai Tietz + + PR target/60193 + * gcc.target/i386/nest-1.c: New testcase. + +2014-02-18 Eric Botcazou + + * gnat.dg/opt32.adb: New test. + +2014-02-15 Jerry DeLisle + Dominique d'Humieres + + Backport from mainline + PR libfortran/59771 + PR libfortran/59774 + PR libfortran/59836 + * gfortran.dg/fmt_g_1.f90: New test. + * gfortran.dg/round_3.f08: New cases added. + +2014-02-13 Dominik Vogt + + * gcc.target/s390/hotpatch-compile-8.c: New test. + +2014-02-12 Eric Botcazou + + * gcc.c-torture/execute/20140212-1.c: New test. + +2014-02-10 Richard Biener + + Backport from mainline + 2014-01-30 Richard Biener + + PR tree-optimization/59903 + * gcc.dg/torture/pr59903.c: New testcase. + + 2014-02-10 Richard Biener + + PR tree-optimization/60115 + * gcc.dg/torture/pr60115.c: New testcase. + +2014-02-09 Janus Weil + + Backport from mainline + 2013-10-21 Tobias Burnus + + PR fortran/58803 + PR fortran/59395 + * gfortran.dg/proc_ptr_comp_38.f90: New. + +2014-02-08 Mikael Morin + + PR fortran/57033 + * gfortran.dg/default_initialization_7.f90: New test. + +2014-02-07 Paul Thomas + + PR fortran/59906 + * gfortran.dg/elemental_subroutine_9.f90 : New test + +2014-02-04 Uros Bizjak + + Backport from mainline + 2014-02-02 Uros Bizjak + + PR target/60017 + * gcc.c-torture/execute/pr60017.c: New test. + +2014-02-01 Paul Thomas + + PR fortran/59414 + * gfortran.dg/allocate_class_3.f90 : New test + +2014-01-30 David Holsgrove + + Backport from mainline. + * gcc.target/microblaze/isa/fcmp4.c: New. + +2014-01-26 Mikael Morin + + PR fortran/58007 + * gfortran.dg/unresolved_fixup_1.f90: New test. + * gfortran.dg/unresolved_fixup_2.f90: New test. + +2014-01-24 H.J. Lu + + Backport from mainline. + 2014-01-23 H.J. Lu + + PR target/59929 + * gcc.target/i386/pr59929.c: New test. + +2014-01-24 Paolo Carlini + + PR c++/57524 + * g++.dg/ext/timevar2.C: New. + +2014-01-23 David Holsgrove + + Backport from mainline. + * gcc.target/microblaze/others/builtin-trap.c: New test. + +2014-01-23 Marek Polacek + + Backport from mainline + 2013-10-21 Marek Polacek + + PR middle-end/58809 + * gcc.dg/gomp/pr58809.c: New test. + +2014-01-23 Jakub Jelinek + + PR middle-end/58809 + * c-c++-common/gomp/pr58809.c: New test. + +2014-01-22 Marek Polacek + + Backport from mainline + 2014-01-22 Marek Polacek + + PR c/59891 + * gcc.dg/torture/pr59891.c: New test. + +2014-01-21 Jakub Jelinek + + PR middle-end/59860 + * gcc.dg/strlenopt-4.c: Expect the same counts on s390*-* as on all + other targets. + +2014-01-20 Richard Biener + + PR middle-end/59860 + * gcc.dg/pr59860.c: New testcase. + +2014-01-20 Marek Polacek + + Backported from mainline + 2014-01-17 Marek Polacek + + PR c++/59838 + * g++.dg/diagnostic/pr59838.C: New test. + +2014-01-19 Paul Thomas + + Backport from mainline + 2013-12-01 Paul Thomas + + PR fortran/34547 + * gfortran.dg/null_5.f90 : Include new error. + * gfortran.dg/null_6.f90 : Include new error. + +2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-15 H.J. Lu + + PR target/59794 + * c-c++-common/convert-vec-1.c: Also prune ABI change for + Linux/x86. + * g++.dg/cpp0x/constexpr-53094-2.C: Likewise. + * g++.dg/ext/attribute-test-1.C: Likewise. + * g++.dg/ext/attribute-test-2.C: Likewise. + * g++.dg/ext/attribute-test-3.C: Likewise. + * g++.dg/ext/attribute-test-4.C: Likewise. + * g++.dg/torture/pr38565.C: Likewise. + * gcc.dg/pr53060.c: Likewise. + * c-c++-common/scal-to-vec2.c: Add -msse2 for x86. + * c-c++-common/vector-compare-2.c: Likewise. + * gcc.dg/Wstrict-aliasing-bogus-ref-all-2.c: Likewise. + * g++.dg/conversion/simd1.C: Add -msse2 for x86. Adjust + dg-message line number. + +2014-01-17 H.J. Lu + + Backport from mainline + 2014-01-14 H.J. Lu + + PR target/59794 + * gcc.target/i386/pr39162.c (y): New __m256i variable. + (bar): Change return type to void. Set y to x. + * gcc.target/i386/pr59794-1.c: New testcase. + * gcc.target/i386/pr59794-2.c: Likewise. + * gcc.target/i386/pr59794-3.c: Likewise. + * gcc.target/i386/pr59794-4.c: Likewise. + * gcc.target/i386/pr59794-5.c: Likewise. + * gcc.target/i386/pr59794-6.c: Likewise. + * gcc.target/i386/pr59794-7.c: Likewise. + +2014-01-17 Matthias Klose + + Backport from the trunk: + 2014-01-09 Uros Bizjak + * go.test/go-test.exp (go-gc-tests): Don't run peano.go on systems + which don't support -fsplit-stack. Skip rotate[0123].go tests. + +2014-01-15 Kugan Vivekanandarajah + + Backport from mainline + 2014-01-15 Matthew Gretton-Dann + Kugan Vivekanandarajah + + PR target/59695 + * g++.dg/pr59695.C: New testcase. + +2014-01-17 Terry Guo + + * gcc.target/arm/pr59826.c: New test. + +2014-01-16 Jakub Jelinek + + PR target/59839 + * gcc.target/i386/pr59839.c: New test. + + PR debug/54694 + * gcc.target/i386/pr9771-1.c (main): Rename to... + (real_main): ... this. Add __asm name "main". + (ASMNAME, ASMNAME2, STRING): Define. + +2014-01-16 Marek Polacek + + Backported from mainline + 2014-01-16 Marek Polacek + + PR middle-end/59827 + * gcc.dg/pr59827.c: New test. + +2014-01-15 Andreas Krebbel + + PR target/59803 + * gcc.c-torture/compile/pr59803.c: New testcase. + +2014-01-10 Yufeng Zhang + + * gcc.target/arm/neon/vst1Q_laneu64-1.c: New test. + +2014-01-10 Hans-Peter Nilsson + + * gcc.dg/pr46309.c: Disable for cris*-*-*. + +2014-01-10 Paolo Carlini + + PR c++/56060 + PR c++/59730 + * g++.dg/cpp0x/variadic144.C: New. + * g++.dg/cpp0x/variadic145.C: Likewise. + +2014-01-10 Richard Biener + + PR tree-optimization/59715 + * gcc.dg/torture/pr59715.c: New testcase. + +2014-01-09 Richard Sandiford + + * gcc.target/mips/bswap-1.c, gcc.target/mips/bswap-2.c, + gcc.target/mips/bswap-3.c, gcc.target/mips/bswap-4.c, + gcc.target/mips/bswap-5.c, gcc.target/mips/bswap-6.c: New tests. + +2014-01-09 Richard Sandiford + + PR rtl-optimization/59137 + * gcc.target/mips/pr59137.c: New test. + +2014-01-09 Richard Biener + + Backport from mainline + 2013-11-18 Richard Biener + + PR tree-optimization/59125 + PR tree-optimization/54570 + * gcc.dg/builtin-object-size-8.c: Un-xfail. + * gcc.dg/builtin-object-size-14.c: New testcase. + * gcc.dg/strlenopt-14gf.c: Adjust. + * gcc.dg/strlenopt-1f.c: Likewise. + * gcc.dg/strlenopt-4gf.c: Likewise. + + 2013-12-03 Jakub Jelinek + + PR tree-optimization/59362 + * gcc.c-torture/compile/pr59362.c: New test. + +2014-01-09 Richard Earnshaw + + PR rtl-optimization/54300 + * gcc.target/arm/pr54300.C: New test. + +2014-01-08 Martin Jambor + + PR ipa/59610 + * gcc.dg/ipa/pr59610.c: New test. + +2014-01-07 Jakub Jelinek + + PR rtl-optimization/58668 + * gcc.dg/pr58668.c: New test. + + Backported from mainline + 2013-12-16 Jakub Jelinek + + PR middle-end/58956 + PR middle-end/59470 + * gcc.target/i386/pr59470.c: New test. + +2014-01-04 Janus Weil + + Backport from mainline + 2014-01-02 Janus Weil + + PR fortran/59654 + * gfortran.dg/dynamic_dispatch_12.f90: New. + +2014-01-03 Joseph Myers + + * gcc.target/powerpc/rs6000-ldouble-3.c: New test. + +2014-01-03 Jakub Jelinek + + PR target/59625 + * gcc.target/i386/pr59625.c: New test. + +2014-01-01 Jakub Jelinek + + PR rtl-optimization/59647 + * g++.dg/opt/pr59647.C: New test. + +2013-12-31 Janus Weil + + Backport from mainline + 2013-12-30 Janus Weil + + PR fortran/58998 + * gfortran.dg/generic_28.f90: New. + +2013-12-20 Jakub Jelinek + + PR c++/59255 + * g++.dg/tree-prof/pr59255.C: New test. + +2013-12-19 James Greenhalgh + + Backport from Mainline + 2013-05-01 James Greenhalgh + + * gcc.target/aarch64/scalar_intrinsics.c (force_simd): New. + (test_vceqd_s64): Force arguments to SIMD registers. + (test_vceqzd_s64): Likewise. + (test_vcged_s64): Likewise. + (test_vcled_s64): Likewise. + (test_vcgezd_s64): Likewise. + (test_vcged_u64): Likewise. + (test_vcgtd_s64): Likewise. + (test_vcltd_s64): Likewise. + (test_vcgtzd_s64): Likewise. + (test_vcgtd_u64): Likewise. + (test_vclezd_s64): Likewise. + (test_vcltzd_s64): Likewise. + (test_vtst_s64): Likewise. + (test_vtst_u64): Likewise. + +2013-12-19 Dominik Vogt + Andreas Krebbel + + Backport from mainline + 2013-12-19 Dominik Vogt + * gcc/testsuite/gcc.target/s390/hotpatch-1.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-2.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-3.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-4.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-5.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-6.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-7.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-8.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-9.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-10.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-11.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-12.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-1.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-2.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-3.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-4.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-5.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-6.c: New test + * gcc/testsuite/gcc.target/s390/hotpatch-compile-7.c: New test + +2013-12-18 Janus Weil + + Backport from mainline + 2013-12-15 Janus Weil + + PR fortran/59493 + * gfortran.dg/unlimited_polymorphic_15.f90: New. + +2013-12-15 Uros Bizjak + + PR testsuite/58630 + * gcc.target/i386/pr43662.c (dg-options): + Add -maccumulate-outgoing-args. + * gcc.target/i386/pr43869.c (dg-options): Ditto. + * gcc.target/i386/pr57003.c (dg-options): Ditto. + * gcc.target/i386/avx-vzeroupper-16.c (dg-options): + Remove -mtune=generic and add -maccumulate-outgoing-args instead. + * gcc.target/i386/avx-vzeroupper-17.c (dg-options): Ditto. + * gcc.target/i386/avx-vzeroupper-18.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/func-1.c (dg-options): + Add -maccumulate-outgoing-args. + * gcc.target/x86_64/abi/callabi/func-2a.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/func-2b.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/func-indirect.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/func-indirect-2a.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/func-indirect-2b.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/leaf-1.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/leaf-2.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/pr38891.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-1.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-2.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-3.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-4a.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-4b.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-5a.c (dg-options): Ditto. + * gcc.target/x86_64/abi/callabi/vaarg-5b.c (dg-options): Ditto. + +2013-12-12 Jakub Jelinek + + PR middle-end/59470 + * g++.dg/opt/pr59470.C: New test. + + PR libgomp/59467 + * gfortran.dg/gomp/pr59467.f90: New test. + * c-c++-common/gomp/pr59467.c: New test. + +2013-12-12 Uros Bizjak + + Backport from mainline + 2013-12-12 Ryan Mansfield + + PR testsuite/59442 + * gcc.target/i386/sse2-movapd-1.c: Fix alignment attributes. + * gcc.target/i386/sse2-movapd-2.c: Likewise. + * gcc.target/i386/avx-vmovapd-256-1.c: Likewise. + * gcc.target/i386/avx-vmovapd-256-2.c: Likewise. + +2013-12-08 Uros Bizjak + + Backport from mainline + 2013-12-06 Uros Bizjak + + PR target/59405 + * gcc.target/i386/pr59405.c: New test. + +2013-12-06 Jakub Jelinek + + PR tree-optimization/59388 + * gcc.c-torture/execute/pr59388.c: New test. + +2013-12-06 Richard Biener + + Backport from mainline + 2013-11-28 Richard Biener + + PR tree-optimization/59330 + * gcc.dg/torture/pr59330.c: New testcase. + +2013-12-06 Richard Biener + + Backport from mainline + 2013-11-27 Richard Biener + + PR tree-optimization/59288 + * gcc.dg/torture/pr59288.c: New testcase. + + 2013-11-19 Richard Biener + + PR tree-optimization/59164 + * gcc.dg/torture/pr59164.c: New testcase. + + 2013-09-05 Richard Biener + + PR tree-optimization/58137 + * gcc.target/i386/pr58137.c: New testcase. + +2013-12-06 Oleg Endo + + PR target/51244 + PR target/59343 + * gcc.target/sh/pr51244-19.c: Adjust test case. + +2013-12-05 Richard Biener + + Backport from mainline + 2013-11-19 Richard Biener + + PR middle-end/58956 + * gcc.dg/torture/pr58956.c: New testcase. + +2013-12-04 Jakub Jelinek + + PR c++/59268 + * g++.dg/cpp0x/constexpr-template6.C: New test. + + PR rtl-optimization/58726 + * gcc.c-torture/execute/pr58726.c: New test. + + PR target/59163 + * g++.dg/torture/pr59163.C: New test. + +2013-12-03 Marek Polacek + + Backport from mainline + 2013-12-03 Marek Polacek + + PR c/59351 + * gcc.dg/pr59351.c: New test. + +2013-12-03 Jakub Jelinek + + PR middle-end/59011 + * gcc.dg/pr59011.c: New test. + + PR target/58864 + * g++.dg/opt/pr58864.C: New test. + +2013-12-02 Jakub Jelinek + + PR tree-optimization/59358 + * gcc.c-torture/execute/pr59358.c: New test. + +2013-12-02 Richard Biener + + PR tree-optimization/59139 + * gcc.dg/torture/pr59139.c: New testcase. + +2013-11-27 Tom de Vries + Marc Glisse + + PR c++/59032 + * c-c++-common/pr59032.c: New testcase. + +2013-11-27 Tom de Vries + Marc Glisse + + PR middle-end/59037 + * c-c++-common/pr59037.c: New testcase. + +2013-11-30 Paul Thomas + + Backport from mainline + 2013-11-04 Paul Thomas + + PR fortran/57445 + * gfortran.dg/optional_class_1.f90 : New test + +2013-11-29 Jakub Jelinek + + PR c/59280 + * c-c++-common/pr59280.c: New test. + +2013-11-28 Jakub Jelinek + + PR c++/59297 + * g++.dg/gomp/pr59297.C: New test. + +2013-11-28 Kyrylo Tkachov + + Backport from mainline + 2013-11-28 Kyrylo Tkachov + + * gcc.target/arm/vrinta-ce.c: New testcase. + +2013-11-28 Uros Bizjak + + Backport from mainline + 2013-11-23 Uros Bizjak + + PR target/56788 + * config/i386/i386.c (bdesc_multi_arg) : + Declare as MULTI_ARG_1_SF instruction. + : Decleare as MULTI_ARG_1_DF instruction. + * config/i386/sse.md (*xop_vmfrcz2): Rename + from *xop_vmfrcz_. + * config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss + to merge scalar result with __A. + (_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar + result with __A. + +2013-11-28 Terry Guo + + Backport mainline r205391 + 2013-11-26 Terry Guo + + * gcc.target/arm/thumb1-pic-high-reg.c: New case. + * gcc.target/arm/thumb1-pic-single-base.c: New case. + +2013-11-27 Jakub Jelinek + + Backported from mainline + 2013-11-27 Jakub Jelinek + + PR tree-optimization/59014 + * gcc.c-torture/execute/pr59014-2.c: New test. + + 2013-11-26 Jakub Jelinek + + PR tree-optimization/59014 + * gcc.c-torture/execute/pr59014.c: New test. + +2013-11-27 Eric Botcazou + + * gcc.c-torture/execute/20131127-1.c: New test. + +2013-11-25 Vidya Praveen + + Backport from mainline + 2013-10-21 Vidya Praveen + + * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort(). + * gcc.dg/20050922-1.c: Remove stdlib.h and declare abort() and exit(). + +2013-11-20 Dominik Vogt + + Backport from mainline + * gcc.target/s390/htm-1.c: Rename to ... + * gcc/testsuite/gcc.target/s390/htm-builtins-compile-1.c: ... this + one. + * gcc.target/s390/htm-xl-intrin-1.c: Rename to ... + * gcc.target/s390/htm-builtins-compile-3.c: ... this one. + * gcc.target/s390/htm-builtins-compile-2.c: New testcase. + * gcc.target/s390/htm-builtins-1.c: New testcase. + * gcc.target/s390/htm-builtins-2.c: New testcase. + * gcc.target/s390/s390.exp: Add check for htm machine. + +2013-11-19 Richard Biener + + PR tree-optimization/57517 + * gfortran.fortran-torture/compile/pr57517.f90: New testcase. + * gcc.dg/torture/pr57517.c: Likewise. + +2013-11-19 Richard Biener + + Backport from mainline + 2013-11-05 Richard Biener + + PR middle-end/58941 + * gcc.dg/torture/pr58941.c: New testcase. + +2013-11-18 Richard Biener + + Backport from mainline + 2013-10-21 Richard Biener + + PR tree-optimization/58794 + * c-c++-common/torture/pr58794-1.c: New testcase. + * c-c++-common/torture/pr58794-2.c: Likewise. + + 2013-10-21 Richard Biener + + PR middle-end/58742 + * c-c++-common/fold-divmul-1.c: New testcase. + + 2013-11-06 Richard Biener + + PR tree-optimization/58653 + * gcc.dg/tree-ssa/predcom-6.c: New testcase. + * gcc.dg/tree-ssa/predcom-7.c: Likewise. + + PR tree-optimization/59047 + * gcc.dg/torture/pr59047.c: New testcase. + + 2013-10-15 Richard Biener + + PR tree-optimization/58143 + * gcc.dg/torture/pr58143-1.c: New testcase. + * gcc.dg/torture/pr58143-2.c: Likewise. + * gcc.dg/torture/pr58143-3.c: Likewise. + +2013-11-17 Janus Weil + + Backport from mainline + 2013-11-07 Janus Weil + + PR fortran/58471 + * gfortran.dg/constructor_9.f90: New. + +2013-11-16 Janus Weil + + Backport from mainline + 2013-09-20 Janus Weil + + PR fortran/58099 + * gfortran.dg/proc_ptr_43.f90: New. + +2013-11-16 Paul Thomas + + PR fortran/58771 + * gfortran.dg/derived_external_function_1.f90 : New test + +2013-11-14 Uros Bizjak + + Backport from mainline + 2013-11-06 Uros Bizjak + + PR target/59021 + * gcc.target/i386/pr59021.c: New test. + +2013-11-14 Jakub Jelinek + + PR target/59101 + * gcc.c-torture/execute/pr59101.c: New test. + +2013-11-11 Jakub Jelinek + + Backported from mainline + 2013-11-06 Jakub Jelinek + + PR middle-end/58970 + * gcc.c-torture/compile/pr58970-1.c: New test. + * gcc.c-torture/compile/pr58970-2.c: New test. + + 2013-11-05 Jakub Jelinek + + PR rtl-optimization/58997 + * gcc.c-torture/compile/pr58997.c: New test. + +2013-11-10 Wei Mi + + * gcc.dg/pr57518.c: Backport regex fix from r200720. + +2013-11-07 H.J. Lu + + Backport from mainline + 2013-11-07 H.J. Lu + + PR target/59034 + * gcc.target/i386/pr59034-1.c: New test. + * gcc.target/i386/pr59034-2.c: Likewise. + +2013-11-06 Wei Mi + + PR regression/58985 + * gcc.dg/pr57518.c: Add subreg in regexp pattern. + +2013-11-05 Steven G. Kargl + + PR fortran/58989 + * gfortran.dg/reshape_6.f90: New test. + +2013-11-05 Jakub Jelinek + + PR tree-optimization/58984 + * gcc.c-torture/execute/pr58984.c: New test. + +2013-11-04 Marek Polacek + + Backport from mainline + 2013-11-04 Marek Polacek + + PR c++/58979 + * g++.dg/diagnostic/pr58979.C: New test. + +2013-11-03 H.J. Lu + + Backport from mainline + 2013-10-12 H.J. Lu + + PR target/58690 + * gcc.target/i386/pr58690.c: New test + +2013-11-02 Janus Weil + + Backport from mainline + 2013-09-23 Janus Weil + + PR fortran/58355 + * gfortran.dg/extends_15.f90: New. + +2013-10-29 Uros Bizjak + + Backport from mainline + 2013-08-08 Richard Sandiford + + PR rtl-optimization/58079 + * gcc.dg/torture/pr58079.c: New test. + +2013-10-28 Tom de Vries + + * gcc.target/arm/require-pic-register-loc.c: New test. + +2013-10-26 Uros Bizjak + + Backport from mainline + 2013-10-22 Uros Bizjak + + PR target/58779 + * gcc.target/i386/pr30315.c: Remove MINUSCC, DECCC, MINUSCCONLY + and MINUSCCZEXT defines. Update scan-assembler dg directive. + * gcc.dg/torture/pr58779.c: New test. + +2013-10-25 Richard Henderson + + PR rtl/58542 + * gcc.dg/atomic-store-6.c: New. + +2013-10-25 Tom de Vries + + PR c++/58282 + * g++.dg/tm/noexcept-6.C: New test. + +2013-10-25 Eric Botcazou + + * gcc.c-torture/execute/pr58831.c: New test. + +2013-10-23 Tom de Vries + + PR tree-optimization/58805 + * gcc.dg/pr58805.c: New test. + +2013-10-23 Richard Biener + + * gcc.dg/torture/pr58830.c: New testcase. + + Backport from mainline + 2013-06-24 Richard Biener + + PR tree-optimization/57488 + * gcc.dg/torture/pr57488.c: New testcase. + +2013-10-19 Oleg Endo + + * gcc.target/sh/pr54089-3.c: Fix test for load of constant 31. + +2013-10-17 Paolo Carlini + + PR c++/58596 + * g++.dg/cpp0x/lambda/lambda-nsdmi5.C: New + +2013-10-16 Paolo Carlini + + PR c++/58633 + * g++.dg/cpp0x/decltype57.C: New. + * g++.dg/cpp0x/enum18.C: Revert r174385 changes. + 2013-10-16 Release Manager * GCC 4.8.2 released. @@ -494,7 +2356,7 @@ 2013-06-19 Wei Mi PR rtl-optimization/57518 - * testsuite/gcc.dg/pr57518.c: New test. + * gcc.dg/pr57518.c: New test. 2013-06-11 Tobias Burnus @@ -1102,7 +2964,7 @@ 2013-03-29 Tobias Burnus PR fortran/56737 - * testsuite/gfortran.dg/fmt_cache_3.f90: New. + * gfortran.dg/fmt_cache_3.f90: New. 2013-04-02 Richard Biener @@ -1636,7 +3498,7 @@ 2013-02-20 Jan Hubicka PR tree-optimization/56265 - * testsuite/g++.dg/ipa/devirt-11.C: New testcase. + * g++.dg/ipa/devirt-11.C: New testcase. 2013-02-20 Richard Biener @@ -1823,11 +3685,9 @@ Avoid instrumenting duplicated memory access in the same basic block * c-c++-common/asan/no-redundant-instrumentation-1.c: New test. - * testsuite/c-c++-common/asan/no-redundant-instrumentation-2.c: - Likewise. - * testsuite/c-c++-common/asan/no-redundant-instrumentation-3.c: - Likewise. - * testsuite/c-c++-common/asan/inc.c: Likewise. + * c-c++-common/asan/no-redundant-instrumentation-2.c: Likewise. + * c-c++-common/asan/no-redundant-instrumentation-3.c: Likewise. + * c-c++-common/asan/inc.c: Likewise. 2013-02-12 Vladimir Makarov diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-1.c b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-1.c new file mode 100644 index 000000000..3abf8a768 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-1.c @@ -0,0 +1,8 @@ +/* PR preprocessor/58844 */ +/* { dg-do compile } */ +/* { dg-options "-ftrack-macro-expansion=0" } */ + +#define A x######x +int A = 1; +#define A x######x /* { dg-message "previous definition" } */ +#define A x##x /* { dg-warning "redefined" } */ diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-2.c b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-2.c new file mode 100644 index 000000000..1e219152f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr58844-2.c @@ -0,0 +1,8 @@ +/* PR preprocessor/58844 */ +/* { dg-do compile } */ +/* { dg-options "-ftrack-macro-expansion=2" } */ + +#define A x######x +int A = 1; +#define A x######x /* { dg-message "previous definition" } */ +#define A x##x /* { dg-warning "redefined" } */ diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-1.h b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-1.h new file mode 100644 index 000000000..3e32175fe --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-1.h @@ -0,0 +1,3 @@ +??=ifndef PR60400_1_H +??=define PR60400_1_H +??=endif diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-2.h b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-2.h new file mode 100644 index 000000000..d9a590636 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400-2.h @@ -0,0 +1,4 @@ +??=ifndef PR60400_2_H +??=define PR60400_2_H +??=include "pr60400-1.h" +??=endif diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400.c b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400.c new file mode 100644 index 000000000..fc3e0d9f4 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/cpp/pr60400.c @@ -0,0 +1,13 @@ +/* PR preprocessor/60400 */ +/* { dg-do compile } */ +/* { dg-options "-trigraphs -Wtrigraphs" } */ + +??=include "pr60400-1.h" +??=include "pr60400-2.h" + +/* { dg-warning "trigraph" "" { target *-*-* } 1 } */ +/* { dg-warning "trigraph" "" { target *-*-* } 2 } */ +/* { dg-warning "trigraph" "" { target *-*-* } 3 } */ +/* { dg-warning "trigraph" "" { target *-*-* } 4 } */ +/* { dg-warning "trigraph" "" { target *-*-* } 5 } */ +/* { dg-warning "trigraph" "" { target *-*-* } 6 } */ diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/fold-divmul-1.c b/gcc-4.8/gcc/testsuite/c-c++-common/fold-divmul-1.c new file mode 100644 index 000000000..5c867923d --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/fold-divmul-1.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-fdump-tree-original" } */ + +int * +fx (int *b, int *e) +{ + return b + (e - b); +} + +/* { dg-final { scan-tree-dump-not "/\\\[ex\\\]" "original" } } */ +/* { dg-final { cleanup-tree-dump "original" } } */ diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr58809.c b/gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr58809.c new file mode 100644 index 000000000..d1ea51b99 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr58809.c @@ -0,0 +1,31 @@ +/* PR middle-end/58809 */ +/* { dg-do compile } */ +/* { dg-options "-fopenmp" } */ + +_Complex int j; +_Complex double d; + +void +foo (void) +{ + #pragma omp parallel reduction (&:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (|:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (^:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (min:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (max:j) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (&:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (|:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (^:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (min:d) /* { dg-error "has invalid type for" } */ + ; + #pragma omp parallel reduction (max:d) /* { dg-error "has invalid type for" } */ + ; +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr59467.c b/gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr59467.c new file mode 100644 index 000000000..475182a62 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/gomp/pr59467.c @@ -0,0 +1,68 @@ +/* PR libgomp/59467 */ + +int v; + +void +foo (void) +{ + int x = 0, y = 0; + #pragma omp parallel + { + int z; + #pragma omp single copyprivate (x) /* { dg-error "is not threadprivate or private in outer context" } */ + { + #pragma omp atomic write + x = 6; + } + #pragma omp atomic read + z = x; + #pragma omp atomic + y += z; + } + #pragma omp parallel + { + int z; + #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */ + { + #pragma omp atomic write + v = 6; + } + #pragma omp atomic read + z = v; + #pragma omp atomic + y += z; + } + #pragma omp parallel private (x) + { + int z; + #pragma omp single copyprivate (x) + { + #pragma omp atomic write + x = 6; + } + #pragma omp atomic read + z = x; + #pragma omp atomic + y += z; + } + x = 0; + #pragma omp parallel reduction (+:x) + { + #pragma omp single copyprivate (x) + { + #pragma omp atomic write + x = 6; + } + #pragma omp atomic + y += x; + } + #pragma omp single copyprivate (x) + { + x = 7; + } + #pragma omp single copyprivate (v) /* { dg-error "is not threadprivate or private in outer context" } */ + { + #pragma omp atomic write + v = 6; + } +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-1.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-1.c new file mode 100644 index 000000000..abe11e7ec --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-1.c @@ -0,0 +1,12 @@ +/* PR middle-end/36282 */ +/* { dg-do compile } */ + +#pragma weak bar + +extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n); +extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */ + +void +foo (void) +{ +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-2.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-2.c new file mode 100644 index 000000000..86d3ad657 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-2.c @@ -0,0 +1,10 @@ +/* PR middle-end/36282 */ +/* { dg-do compile } */ + +extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n); +extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */ + +void +foo (void) +{ +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-3.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-3.c new file mode 100644 index 000000000..8982470c0 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-3.c @@ -0,0 +1,13 @@ +/* PR middle-end/36282 */ +/* { dg-do compile } */ + +void bar (void); +#pragma weak bar + +extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n); +extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */ + +void +foo (void) +{ +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-4.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-4.c new file mode 100644 index 000000000..f6f40f8e4 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr36282-4.c @@ -0,0 +1,13 @@ +/* PR middle-end/36282 */ +/* { dg-do compile } */ + +#pragma weak bar +void bar (void); + +extern void *baz (void *dest, const void *src, __SIZE_TYPE__ n); +extern __typeof (baz) baz __asm("bazfn"); /* { dg-bogus "asm declaration ignored due to conflict with previous rename" } */ + +void +foo (void) +{ +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr37743.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr37743.c new file mode 100644 index 000000000..2ea678e09 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr37743.c @@ -0,0 +1,13 @@ +/* PR c/37743 */ +/* This needs to be run only on targets where __UINT32_TYPE__ is defined + to unsigned int. */ +/* { dg-do compile { target *-*-linux-gnu* } } */ +/* { dg-options "-Wformat" } */ + +int foo (const char *, ...) __attribute__ ((format (printf, 1, 2))); + +void +bar (unsigned int x) +{ + foo ("%x", __builtin_bswap32 (x)); +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr59032.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr59032.c new file mode 100644 index 000000000..327f5aeb6 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr59032.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +void +foo() +{ + float v __attribute__((vector_size(8))); + v++; +} + +void +foo2 () +{ + float v __attribute__((vector_size(8))); + ++v; +} + +void +foo3 () +{ + float v __attribute__((vector_size(8))); + v--; +} + +void +foo4 () +{ + float v __attribute__((vector_size(8))); + --v; +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr59037.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr59037.c new file mode 100644 index 000000000..fae13c2fa --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr59037.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +typedef int v4si __attribute__ ((vector_size (16))); + +int +main (int argc, char** argv) +{ + v4si x = {0,1,2,3}; + x = (v4si) {(x)[3], (x)[2], (x)[1], (x)[0]}; + return x[4]; +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr59280.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr59280.c new file mode 100644 index 000000000..779f0fb85 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr59280.c @@ -0,0 +1,4 @@ +/* PR c/59280 */ +/* { dg-do compile } */ + +void bar (char *) __attribute__((constructor(foo))); /* { dg-error "constructor priorities must be integers|was not declared|constructor priorities are not supported" } */ diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr60101.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr60101.c new file mode 100644 index 000000000..b1634c49f --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr60101.c @@ -0,0 +1,112 @@ +/* PR c/60101 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -Wall" } */ + +extern int *a, b, *c, *d; + +void +foo (double _Complex *x, double _Complex *y, double _Complex *z, unsigned int l, int w) +{ + unsigned int e = (unsigned int) a[3]; + double _Complex (*v)[l][4][e][l][4] = (double _Complex (*)[l][4][e][l][4]) z; + double _Complex (*f)[l][b][l] = (double _Complex (*)[l][b][l]) y; + unsigned int g = c[0] * c[1] * c[2]; + unsigned int h = d[0] + c[0] * (d[1] + c[1] * d[2]); + unsigned int i; + + for (i = 0; i < e; i++) + { + int j = e * d[3] + i; + + unsigned int n0, n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11; + float _Complex s = 0.; + unsigned int t = 0; + + for (n0 = 0; n0 < l; n0++) + for (n1 = 0; n1 < l; n1++) + for (n2 = 0; n2 < l; n2++) + for (n3 = 0; n3 < l; n3++) + for (n4 = 0; n4 < l; n4++) + for (n5 = 0; n5 < l; n5++) + for (n6 = 0; n6 < l; n6++) + for (n7 = 0; n7 < l; n7++) + for (n8 = 0; n8 < l; n8++) + for (n9 = 0; n9 < l; n9++) + for (n10 = 0; n10 < l; n10++) + for (n11 = 0; n11 < l; n11++) + { + if (t % g == h) + s + += f[n0][n4][j][n8] * f[n1][n5][j][n9] * ~(f[n2][n6][w][n10]) * ~(f[n3][n7][w][n11]) + * (+0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1] + * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 0.25 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0] + - 0.5 * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n10][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0] + - 0.5 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0] + + 0.25 * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1] + * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] + - 0.5 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0] + + 0.25 * v[0][n3][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n10][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] + + 0.25 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0] + - 0.5 * v[0][n3][0][i][n9][1] * v[0][n10][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] + - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] + - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0] + + 0.25 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 1. * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0] + - 0.5 * v[0][n10][0][i][n9][1] * v[0][n2][0][i][n5][1] * v[0][n3][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0] + - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n6][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] + + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n6][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] + + 0.25 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n7][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n11][1][i][n0][0] + - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n6][1][i][n0][0] + - 0.5 * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n6][1][i][n1][0] * v[0][n7][1][i][n0][0] + + 1. * v[0][n10][0][i][n9][1] * v[0][n3][0][i][n5][1] * v[0][n2][0][i][n4][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n6][1][i][n0][0] + + 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] + * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n8][0] + - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] + * v[0][n11][1][i][n1][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n8][0] + - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] + * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n10][0][i][n1][0] + + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] + * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n1][0] * v[0][n10][0][i][n0][0] + + 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n0][0] * v[0][n10][0][i][n1][0] + - 0.5 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n3][0][i][n5][1] + * v[0][n11][1][i][n8][0] * v[0][n7][1][i][n1][0] * v[0][n10][0][i][n0][0] + - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] + * v[0][n7][1][i][n1][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n8][0] + - 0.25 * v[0][n6][1][i][n4][1] * v[0][n2][0][i][n9][1] * v[0][n10][0][i][n5][1] + * v[0][n7][1][i][n8][0] * v[0][n11][1][i][n0][0] * v[0][n3][0][i][n1][0]); + t++; + } + int u = (j - w + b) % b; + int q = (j >= w ? +1 : -1); + int r = q; + x[u] += r * s; + } +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/pr60689.c b/gcc-4.8/gcc/testsuite/c-c++-common/pr60689.c new file mode 100644 index 000000000..9475bd835 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/pr60689.c @@ -0,0 +1,10 @@ +/* PR c++/60689 */ +/* { dg-do compile } */ + +struct S { char x[9]; }; + +void +foo (struct S *x, struct S *y, struct S *z) +{ + __atomic_exchange (x, y, z, __ATOMIC_SEQ_CST); +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-1.c b/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-1.c new file mode 100644 index 000000000..175629fec --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-1.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ + +struct S0 +{ + int f; +}; + +struct S1 +{ + struct S0 f1; + volatile int f2; +}; + +struct S2 +{ + struct S1 g; +} a, b; + +static int *c[1][2] = {{0, (int *)&a.g.f2}}; +static int d; + +int +main () +{ + for (d = 0; d < 1; d++) + for (b.g.f1.f = 0; b.g.f1.f < 1; b.g.f1.f++) + *c[b.g.f1.f][d + 1] = 0; + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-2.c b/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-2.c new file mode 100644 index 000000000..767798806 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr58794-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ + +struct S +{ + volatile int f; +} a; + +unsigned int b; + +static int *c[1][2] = {{0, (int *)&a.f}}; +static unsigned int d; + +int +main () +{ + for (; d < 1; d++) + for (; b < 1; b++) + *c[b][d + 1] = 0; + + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr60026.c b/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr60026.c new file mode 100644 index 000000000..1cc5f55a4 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/c-c++-common/torture/pr60026.c @@ -0,0 +1,28 @@ +/* PR ipa/60026 */ +/* { dg-do compile } */ + +struct S { int f; } a; + +__attribute__((optimize (0))) +struct S foo (int x, struct S y) +{ + int b = y.f; + return a; +} + +void +bar () +{ + while (a.f) + { + struct S c = {0}; + foo (0, c); + } +} + +int +main () +{ + bar (); + return 0; +} diff --git a/gcc-4.8/gcc/testsuite/g++.dg/cpp0x/access02.C b/gcc-4.8/gcc/testsuite/g++.dg/cpp0x/access02.C new file mode 100644 index 000000000..74960a66a --- /dev/null +++ b/gcc-4.8/gcc/testsuite/g++.dg/cpp0x/access02.C @@ -0,0 +1,39 @@ +// PR c++/58954 +// { dg-require-effective-target c++11 } + +template +T&& declval(); + +template +struct foo_argument +{ + template + static Arg test(Ret (C::*)(Arg)); + + typedef decltype(test(&T::template foo<>)) type; +}; + +template +struct dependent { typedef T type; }; + +template +struct base +{ + template + auto foo(int i) -> decltype(declval< + typename dependent::type + >().foo_impl(i)); +}; + +struct derived : base +{ + friend struct base; +private: + int foo_impl(int i); +}; + +int main() +{ + foo_argument::type var = 0; + return var; +} diff --git a/gcc-4.8/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C b/gcc-4.8/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C new file mode 100644 index 000000000..c444217b0 --- /dev/null +++ b/gcc-4.8/gcc/testsuite/g++.dg/cpp0x/alias-decl-41.C @@ -0,0 +1,18 @@ +// PR c++/60182 +// { dg-require-effective-target c++11 } + +class B {}; +template using __allocator_base = B; +template class F : __allocator_base {}; +class C {}; +template > class G : C {}; +template class D; +class A { + using Container = G>; + A(); + A(D const &); + Container m_elements; +}; +template