From 6e6510c702f12bc6320681075cc0ba8dc2c814a7 Mon Sep 17 00:00:00 2001 From: Andrew Hsieh Date: Fri, 26 Apr 2013 12:56:39 +0800 Subject: Add new GCC/MIPS option -mldc1-sdc1 ldc1/sdc1 needs memory to be 8-byte aligned. This option is on by default for arch supports it, but can be turned off by "-mno-ldc1-sdc1" to workaround issue, for example. Change-Id: I14291dc4280e75f6c765c933b60eb1b7cd44f974 --- gcc-4.4.3/gcc/config/mips/mips.h | 2 +- gcc-4.4.3/gcc/config/mips/mips.opt | 4 ++++ gcc-4.6/gcc/config/mips/mips.h | 2 +- gcc-4.6/gcc/config/mips/mips.opt | 4 ++++ gcc-4.7/gcc/config/mips/mips.h | 2 +- gcc-4.7/gcc/config/mips/mips.opt | 4 ++++ gcc-4.8/gcc/config/mips/mips.h | 2 +- gcc-4.8/gcc/config/mips/mips.opt | 4 ++++ 8 files changed, 20 insertions(+), 4 deletions(-) diff --git a/gcc-4.4.3/gcc/config/mips/mips.h b/gcc-4.4.3/gcc/config/mips/mips.h index 88f5d832e..2d6d313f1 100644 --- a/gcc-4.4.3/gcc/config/mips/mips.h +++ b/gcc-4.4.3/gcc/config/mips/mips.h @@ -821,7 +821,7 @@ enum mips_code_readable_setting { #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ -#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) +#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16 && TARGET_LDC1_SDC1) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ diff --git a/gcc-4.4.3/gcc/config/mips/mips.opt b/gcc-4.4.3/gcc/config/mips/mips.opt index 901675427..5808ae41d 100644 --- a/gcc-4.4.3/gcc/config/mips/mips.opt +++ b/gcc-4.4.3/gcc/config/mips/mips.opt @@ -188,6 +188,10 @@ mips3d Target Report RejectNegative Mask(MIPS3D) Use MIPS-3D instructions +mldc1-sdc1 +Target Report Var(TARGET_LDC1_SDC1) Init(1) +Use ldc1 and sdc1 instruction + mllsc Target Report Mask(LLSC) Use ll, sc and sync instructions diff --git a/gcc-4.6/gcc/config/mips/mips.h b/gcc-4.6/gcc/config/mips/mips.h index 6e34a2a00..79b806dd2 100644 --- a/gcc-4.6/gcc/config/mips/mips.h +++ b/gcc-4.6/gcc/config/mips/mips.h @@ -850,7 +850,7 @@ enum mips_code_readable_setting { #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ -#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) +#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16 && TARGET_LDC1_SDC1) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ diff --git a/gcc-4.6/gcc/config/mips/mips.opt b/gcc-4.6/gcc/config/mips/mips.opt index 20b0b6cde..4be40b1d6 100644 --- a/gcc-4.6/gcc/config/mips/mips.opt +++ b/gcc-4.6/gcc/config/mips/mips.opt @@ -194,6 +194,10 @@ mips3d Target Report RejectNegative Mask(MIPS3D) Use MIPS-3D instructions +mldc1-sdc1 +Target Report Var(TARGET_LDC1_SDC1) Init(1) +Use ldc1 and sdc1 instruction + mllsc Target Report Mask(LLSC) Use ll, sc and sync instructions diff --git a/gcc-4.7/gcc/config/mips/mips.h b/gcc-4.7/gcc/config/mips/mips.h index 61bbd949c..5146cc5de 100644 --- a/gcc-4.7/gcc/config/mips/mips.h +++ b/gcc-4.7/gcc/config/mips/mips.h @@ -847,7 +847,7 @@ struct mips_cpu_info { #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ -#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) +#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16 && TARGET_LDC1_SDC1) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ diff --git a/gcc-4.7/gcc/config/mips/mips.opt b/gcc-4.7/gcc/config/mips/mips.opt index e3294a7f7..8dba482ce 100644 --- a/gcc-4.7/gcc/config/mips/mips.opt +++ b/gcc-4.7/gcc/config/mips/mips.opt @@ -233,6 +233,10 @@ mips3d Target Report RejectNegative Mask(MIPS3D) Use MIPS-3D instructions +mldc1-sdc1 +Target Report Var(TARGET_LDC1_SDC1) Init(1) +Use ldc1 and sdc1 instruction + mllsc Target Report Mask(LLSC) Use ll, sc and sync instructions diff --git a/gcc-4.8/gcc/config/mips/mips.h b/gcc-4.8/gcc/config/mips/mips.h index 798a3cce9..1ad8d7dbb 100644 --- a/gcc-4.8/gcc/config/mips/mips.h +++ b/gcc-4.8/gcc/config/mips/mips.h @@ -841,7 +841,7 @@ struct mips_cpu_info { #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF) /* ISA has LDC1 and SDC1. */ -#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16) +#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16 && TARGET_LDC1_SDC1) /* ISA has the mips4 FP condition code instructions: FP-compare to CC, branch on CC, and move (both FP and non-FP) on CC. */ diff --git a/gcc-4.8/gcc/config/mips/mips.opt b/gcc-4.8/gcc/config/mips/mips.opt index d8ef2e771..b9655a5ec 100644 --- a/gcc-4.8/gcc/config/mips/mips.opt +++ b/gcc-4.8/gcc/config/mips/mips.opt @@ -233,6 +233,10 @@ mips3d Target Report RejectNegative Mask(MIPS3D) Use MIPS-3D instructions +mldc1-sdc1 +Target Report Var(TARGET_LDC1_SDC1) Init(1) +Use ldc1 and sdc1 instruction + mllsc Target Report Mask(LLSC) Use ll, sc and sync instructions -- cgit v1.2.3