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With this change, -fexceptions and -frtti become default options
when compiling C++ sources.
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BUG=23157315
This reverts commit 659b5199aa009008a003062ff828f44b6bd70b65.
Change-Id: I3564560d3aa57c039c6bc78e0cd630cea3a4bb8b
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2014-11-19 Wilco Dijkstra <wdijkstr@arm.com>
PR target/61915
* config/aarch64/aarch64.c (generic_regmove_cost): Increase FP move cost.
Change-Id: Ifaa0c2d1a72955e42f3882c68d1e52acf5a790e7
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
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2015-03-11 Junmo Park <junmoz.park@samsung.com>
* config/arm/cortex-a57.md (cortex_a57_crypto_simple): Add
crypto_sha256_fast.
(cortex_a57_crypto_complex): Add crypto_sha256_slow.
2015-01-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a57.md: Remove duplicate of file accidentally
introduced in revision 219724.
2015-01-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/cortex-a57.md: New.
* config/aarch64/aarch64.md: Include it.
* config/aarch64/aarch64-cores.def (cortex-a57): Tune for it.
* config/aarch64/aarch64-tune.md: Regenerate.
Change-Id: Id089f9d746c222a7ffe224b69e3249f083bbaf3b
Signed-off-by: Junmo Park <junmoz.park@samsung.com>
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BUG=23157315
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[AArch64 costs 5/18] Factor out common MULT cases
gcc/
* config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename
to...
(aarch64_strip_extend): ...this, don't strip shifts, check RTX is
well formed.
(aarch64_rtx_mult_cost): New.
(aarch64_rtx_costs): Use it, refactor as appropriate.
Change-Id: I298e5af1b4006f37d873b113c8d05643e897f6f1
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After call to pointer_map_insert, the caller need to write the value.
This fixes the following regression,
gfortran.dg/array_constructor_6.f90
gfortran.dg/subref_array_pointer_2.f90
Change-Id: Ic7aec96c24d17c527291aefe30e726989ecd9a8f
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support them."
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does not support them.
Change-Id: I0b36e48a9dd0317b65442291752500880b549fb6
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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This change is re-based and modified to work with the older context, as the
context code is changed a lot in GCC trunk.
It is about to insert some barriers on stack-pointer register, so that the
adjust-stack-pointer code does not get scheduled before any code in the
fuction epilogue, which may access some stack space without explicit use of
stack pointer.
Examples are a load from an auto array and some access to an area of alloca.
Anyway, the barriers would make all such alias dependences not violated.
For more details, please refer to GCC bug 63293.
(Personally I think there may be a bit too many barriers generated.)
Change-Id: I61ea54e500b6965feab69a62165d10b6c3a21c20
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Change-Id: I3d6f06fc613c8f8b6a82143dc44b7338483aac5d
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The update is necessary so that LRA is able to detect the conflict
between these regisers and LRA registers.
The change is a back-port from GCC 5.0 r217783, and please refer to
gcc bug 63762 for some details. That bug report has an example, which
is about VFP register file, but the issue applies to ARM integer
register file too, with the same mechanism. The change is mainly about
Thumb, although theoretically not limitted to.
Change-Id: I1fedb410ae5ca39f168dab874f310d7337ab9bcc
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Change-Id: I54a6469aa140e7b24853237ac51398f8e8f4ea95
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BUG=19872411
2014-07-01 Jan Hubicka <hubicka@ucw.cz>
* ipa-utils.h (method_class_type, vtable_pointer_value_to_binfo,
vtable_pointer_value_to_vtable): Constify.
(contains_polymorphic_type_p): Declare.
* ipa-devirt.c (method_class_type, vtable_pointer_value_to_binfo,
vtable_pointer_value_to_vtable): Constify.
(contains_polymorphic_type_p): New predicate.
* ipa-prop.c (ipa_set_jf_known_type): Allow types containing
polymorphic types.
(ipa_set_ancestor_jf): Likewise.
(detect_type_change): Return false in easy cases.
(compute_complex_assign_jump_func): Require type to contain
polymorphic type.
(compute_known_type_jump_func): Likewise.
Change-Id: If4b1a919f00fb1b23c6ebce84141c04120e0e2b6
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Change-Id: Id19630f78848dc3ccfa564e2e925f892b8ea4433
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Fix builtin vector types for 64 bit mode.
Change-Id: I0641798eb23646dcd3fc4d5ee623ad4d8dcbd142
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2014-06-30 Joseph Myers <joseph@codesourcery.com>
* var-tracking.c (add_stores): Return instead of asserting if old
and new values for conditional store are the same.
Change-Id: Ibb5775a3ad90e57bd6882a86a6b4c7a5262c09d0
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("O0")
In google/google-4_9 branch
------------------------------------------------------------------------
r221700 | wmi | 2015-03-26 11:11:16 -0700 (Thu, 26 Mar 2015) | 13 lines
Fix the problem in b/19277289 by avoiding calling walk_aliased_vdefs in O0 function.
gcc/
2015-03-26 Carrot Wei <carrot@google.com>
* ipa-inline-analysis.c: Early return.
gcc/testsuite
2015-03-26 Carrot Wei <carrot@google.com>
* testsuite/gcc.dg/19277289.c: New test.
Change-Id: I6bd7353b65fb918f9651dd737cbe3112fca1fa17
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Change-Id: Id87035be4552719dc05096bb98b49d4bed91a07a
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2014-11-21 Evgeny Stupachenko <evstupac@gmail.com>
PR target/60451
* config/i386/i386.c (expand_vec_perm_even_odd_pack): New.
(expand_vec_perm_even_odd_1): Add new expand for V8HI mode,
replace for V16QI, V16HI and V32QI modes.
(ix86_expand_vec_perm_const_1): Add new expand.
2014-06-11 Evgeny Stupachenko <evstupac@gmail.com>
* tree-vect-data-refs.c (vect_grouped_store_supported): New
check for stores group of length 3.
(vect_permute_store_chain): New permutations for stores group of
length 3.
* tree-vect-stmts.c (vect_model_store_cost): Change cost
of vec_perm_shuffle for the new permutations.
2014-11-28 Evgeny Stupachenko <evstupac@gmail.com>
* tree-vect-data-refs.c (vect_transform_grouped_load): Limit shift
permutations to loads group of size 3.
2014-12-18 Bin Cheng <bin.cheng@arm.com>
PR tree-optimization/62178
* tree-ssa-loop-ivopts.c (cheaper_cost_with_cand): New function.
(iv_ca_replace): New function.
(try_improve_iv_set): New parameter try_replace_p.
Break local optimal fixed-point by calling iv_ca_replace.
(find_optimal_iv_set_1): Pass new argument to try_improve_iv_set.
Change-Id: I5dca8236d3807cedc5e09d7eda65f0ccec9f5cb2
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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2014-11-24 Richard Biener <rguenther@suse.de>
PR tree-optimization/55334
* function.h (struct function): Add last_clique member.
* tree-inline.c (remap_dependence_clique): New function.
(remap_gimple_op_r): Remap dependence cliques in MEM_REFs.
(copy_tree_body_r): Likewise.
(copy_cfg_body): Free dependence map.
(copy_gimple_seq_and_replace_locals): Likewise.
* tree-pretty-print.c (dump_generic_node): Dump
dependence info.
* tree-ssa-alias.c (refs_may_alias_p_1): Use dependence info
to answer alias query.
* tree-ssa-structalias.c: Include tree-phinodes.h, ssa-iterators.h,
tree-pretty-print.h and gimple-walk.h.
(struct variable_info): Add is_restrict_var flag and ruid
member.
(new_var_info): Initialize is_restrict_var.
(make_constraint_from_restrict): Likewise.
(create_variable_info_for): Exclude restricts from global vars
from new handling.
(intra_create_variable_infos): But not those from parameters.
(visit_loadstore): New function.
(maybe_set_dependence_info): Likewise.
(compute_dependence_clique): Likewise.
(compute_may_aliases): Call compute_dependence_clique.
* tree-data-ref.c (dr_analyze_indices): Copy dependence info
to fake MEM_REF.
(dr_may_alias_p): Use recorded dependence info to answer
alias query.
* tree-core.h (struct tree_base): Add clique, base struct in
union.
* tree.h (MR_DEPENDENCE_CLIQUE): New macro.
(MR_DEPENDENCE_BASE): Likewise.
* tree-inline.h (dependence_hasher): New hash-map kind.
(struct copy_body_data): Add dependence_map pointer.
* tree-streamer-in.c (unpack_value_fields): Stream dependence info.
* tree-streamer-out.c (streamer_pack_tree_bitfields): Likewise.
* gcc.dg/tree-ssa/restrict-5.c: New testcase.
Change-Id: I45c8d5eac758aea881a884c131f627cc916cbaf3
Signed-off-by: Andrew Senkevich <andrew.senkevich@intel.com>
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is costly"
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Author: uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Sat Nov 22 19:02:12 2014 +0000
* params.def (PARAM_MAX_COMPLETELY_PEELED_INSNS): Increase to 200.
* config/i386/i386.c (ix86_option_override_internal): Do not increase
PARAM_MAX_COMPLETELY_PEELED_INSNS.
Change-Id: I202e14a29f2436872910301efec863afdd4127e7
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false positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed.""
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positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed."
This reverts commit 407a2d5c2c63bdc0c842ffcd57a139ef8a4f33e2, because https://android-review.googlesource.com/#/c/125800 provides fixes to root cause.
Change-Id: I3ceda349beca8e558ccfac5602de942b9be4d31d
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2015-01-28 Ilya Enkovich <ilya.enkovich@intel.com>
PR tree-optimization/64277
* tree-ssa-loop-niter.c (record_nonwrapping_iv): Use base
range info when possible to refine estimation.
2015-01-27 Richard Biener <rguenther@suse.de>
PR tree-optimization/56273
PR tree-optimization/59124
PR tree-optimization/64277
* tree-vrp.c (vrp_finalize): Emit array-bound warnings only
from the first VRP pass.
* g++.dg/warn/Warray-bounds-6.C: New testcase.
* gcc.dg/Warray-bounds-12.c: Likewise.
* gcc.dg/Warray-bounds-13.c: Likewise.
Change-Id: I175b420a4c8150ecf986d477e4c51cbbff276c82
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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2014-11-21 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/i386.c (ix86_option_override_internal): Increase
PARAM_MAX_COMPLETELY_PEELED_INSNS.
Change-Id: I529a9297cb8d230a5821d73d5b462d433a8c2108
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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We are seeing some false positive array bound warnings due to an
issue in complete unroll. This patch disables this warning
so we can switch the ARM build to 4.9. Will re-enable the
warning once the issue is fixed.
Change-Id: Ifefe470b9e9146665e9096e5ac6f2f5fec7b9627
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2014-10-13 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY):
Remove m_SILVERMONT and m_INTEL from the tune.
Change-Id: I5d793525c43015f10f15cd46505e326039dd4b7e
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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This patch backports svn r216853 from upsteam gcc-4.9 branch that
fixed a bug introduced in fixing cortex a53 erratum 835769.
Change-Id: Iccc6fd04ede28c2deba51be3f8e348ce374c8b4f
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Android does not use the LINK_SPEC in aarch64-linux.h.
Rather, it picks up LINUX_TARGET_LINK_SPEC. Move the SPEC
change in r216979 to LINUX_TRAGET_LINK_SPEC.
Change-Id: I6c39522efcfe067a8a66397954b386f5d104dc02
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Backport 3 patches from upstream gcc that fixed some vectorization
issues: r215585 fixed PR63341
r216508 fixed PR63563
r216770 fixed PR63530
Change-Id: I650bf25ef0843b1ff01911b567fb26e069fd4550
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This is proted from upstream gcc-4_9 branch: svn r216979.
Change-Id: I1cee530fb4f50843a9832aa678c1630f51564fa6
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r216292 from google/gcc-4_9 branch: Move update_ssa after vpt transformation. BUG=17997360"
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Backport r216292 from google/gcc-4_9 branch: Move update_ssa
after vpt transformation.
BUG=17997360
Change-Id: Iae9e15be6ff5655b1514e349c55f05647388df36
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google/gcc-4_9 branches which makes ifunc support available for BIONIC (still controlled by configure)."
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Backport r216764 from google/gcc-4_9 branches which makes ifunc support
available for BIONIC (still controlled by configure).
Change-Id: I515d4d38e11bd0378899e64e68ab5b255e2c6df3
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For ndk docs change, please refer to:
https://android-review.googlesource.com/#/c/110100/
Change-Id: Icbe13a158511d519312b2a1d3e606c9dd2bff4af
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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This patch cherry picks r216116 from google/gcc-4_9 branch (which
is r216077 and r216079 from upstream gcc-4_9 branch).
Tested the built compiler with aarch64 devicde.
Change-Id: I75745fe35aae83bc3b64135a2efc7f8ffd9cfb1f
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Set bionic linker to /system/bin/linker64 for aarch64 in Android.
The default /system/bin/linker causes run-time error reads:
/system/bin/sh: /path/to/your/app: Accessing a corrupted shared library
Change-Id: Ieaaebd267c87e7803372171478ae8f8b9ab71dfe
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Improve NEON instrinsics coverage from ~41% to ~93%. This change brings
new intrinsics and modifies old ones for better maintainability.
Also take into account that IA32 now supports SSSE3 by default, so we
can get rid of SSSE3 checks.
Change-Id: I599c3b93dcf92d0c94bdb786a4aad705f075893b
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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and ICE on some inline assembly constructs.
Change-Id: I47be8ff0d5119f2e95611c0b6ed119414c49c6f8
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Backport two patches from upstream gcc 4.9 branch that fix PR62040 and PR62262
Change-Id: If4f557a650e00261b9bc83e008eb63b13ca798cb
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source r214745 from google/gcc-4_9 branch."
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Merge gcc-4_9 source r214745 from google/gcc-4_9 branch.
Change-Id: Ie6fa0fd72f4b4eec3adc4db4bb922e652d1c2605
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