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* gcc: backport patch to support vrnd<*>_f64 aarch64 intrinsics.Yunlian Jiang2018-04-245-3/+48
| | | | | | | | | | | | | | | | | | | | This backports upstream patch to add support of vrdn<*>_f64 intrinisics for aarch64. This is needed because glibc 2.27 uses some of them. Author: mshawcroft <mshawcroft@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Tue Apr 22 08:39:48 2014 +0000 [AArch64] vrnd<*>_f64 patch This patch adds vrnd<*>_f64 aarch64 intrinsics. A testcase for those intrinsics is added. Run a complete LE and BE regression run with no regressions. BUG=chromium:834385 TEST=./setup_board --board kevin --nousepkg cross-aarch64-cros-linux-gnu-glibc builds for glibc 2.27 Change-Id: Iaf9508a433e35d3304e44ac4b6c93071ff6c5ec0
* [GCC] Update with latest retpoline fixes from Intel.Caroline Tice2018-01-296-88/+245
| | | | | | | | | | | | Intel has updated their retpoline patches since we created our original patch. This CL updates our retpoline changes to match the latest from Intel. Bug: None Test: Tested extensively in ChromeOS. Built x86 platform & kernel images in Android. Change-Id: Id1a18cb1f1f4461832a017cb5c5d59e5400d9d08
* [GCC] Commit retpoline patch code, for fixing security issues.Caroline Tice2018-01-086-372/+683
| | | | | | | | | | | | This applies the Intel GCC code patches, to allow compiling with appropriate flags for mitigating the indirect branch variant of the speculative execution security flaw. Bug: None Test: This is already in place in ChromeOS and has been tested on the ChromeOS kernels. Change-Id: Ideffb433b697f1fe7e4ca2c1eaa968160abfcc8b
* Merge "Remove -Bsymbolic from the Android link spec."Treehugger Robot2017-09-141-1/+1
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| * Remove -Bsymbolic from the Android link spec.Dan Albert2016-01-141-1/+1
| | | | | | | | | | Bug: http://b.android.com/68956 Change-Id: I60bef8715de7920d72ebc9a6bd7f18ceaea05966
* | [GCC 4.9] Fix posix_memalign declaration.Caroline Tice2016-10-041-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the 'throw()' from posix_memalign declaration if __GLIBC__ is not defined, so that it matches declaration in bionic's stdlib.h (avoid conflicting decl error). Can't remove 'throw ()' altogether, because it IS in glibc's stdlib.h, which this has to match in ChromeOS. BUG=b:31366027 TEST=successfully built ChromeOS for x86, x86_64, arm, arm64 and ran HWTests on all; successfully built chromiumos-sdk. Built Android platform & kernel. Successfully ran NDK checkbuild.py script. Change-Id: I0a8b4daf5d10f56f7a318738a0946e4ad5b7dd90
* | Unify ChromeOS and Android versions of GCC.Caroline Tice2016-02-269-41/+559
| | | | | | | | | | | | | | | | This CL updates Android's GCC to match ChromeOS's GCC (with appropriate patches applied in both places to make sure no cherry-picked changes are lost). Change-Id: I390140c449b0e5df9ee78a06268319c8c510302f
* | Revert "Fix toolchain/gcc build for mingw."Than McIntosh2016-01-151-10/+0
|/ | | | | | | | | This reverts commit f1c3ad6cac0465017759cce0cb381ce66760d907. [Change no longer needed since we're switching to a different gcc for the mingw build.] Change-Id: I03a57335e9ca94c6848cb71bbc1a451f0c0ef18f
* Fix toolchain/gcc build for mingw.Than McIntosh2016-01-141-0/+10
| | | | | | | | | | | | | | | Theses changes are intended to restore the ability to build toolchain/gcc cross compiler for non-Android targets (in this specific case, to allow us to compile toolchain/gcc as part of the mingw-w64 build). What has happened over time is that references android-specific synbols and constructs have crept into the non-target-specific portions of the gcc code. I've done my best to push these things back into the config/* subtree. Bug: 26523949 Change-Id: I59334e791875632d51093207c298052a034d2f4a
* Merge "[4.9] Disable inlining of memcpy for x86 with 'rep movs'."Dan Albert2016-01-041-1/+1
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| * [4.9] Disable inlining of memcpy for x86 with 'rep movs'.Alexander Ivchenko2015-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | On big length 'rep movs' are less efficient than libcall of highly-optimized Bionic memcpy. Change-Id: I9435b9e438e0e40c28c505c43ec7f9797384afd6 Signed-off-by: Andrew Senkevich <andrew.senkevich@intel.com> Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* | Default to TLS guard for x86 stack-protector.Than McIntosh2015-11-171-3/+2
| | | | | | | | | | | | | | | | | | Change the default guard flavor for -fstack-protector on x86 from global to TLS. The original default was intended to provide compatibility with pre-4.2. versions of Android, which is less of concern now. Bug: 25183510 Change-Id: I71931e778efed2ba0fa2a6740f8d5510776c113f
* | Fix for N9 kernel build.Than McIntosh2015-10-161-60/+76
|/ | | | | | | | | | | | | | | | Cherry-pick from trunk: commit 39f4504dbc88d17c496cdf7b12fb0d32277d281d Author: pinskia <pinskia@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Tue Jun 3 22:42:47 2014 +0000 2014-06-03 Andrew Pinski <apinski@cavium.com> * config/aarch64/aarch64.c (aarch64_if_then_else_costs): New function. (aarch64_rtx_costs): Use aarch64_if_then_else_costs. Bug: 24985248 Change-Id: Ic03ba2552615fca0aa0de6af47f47ae4cf074e3b
* Reapplied the patch 525b640e8dc9e6063897a7ce8034283Alexander Ivchenko2015-09-141-0/+6
| | | | | | | | | | | | | | | | | ... with peeling limit set to 400 instead of 200 as it used to be. [4.9] Another backport from trunk of additional slm tuning. 2014-11-21 Evgeny Stupachenko <evstupac@gmail.com> * config/i386/i386.c (ix86_option_override_internal): Increase PARAM_MAX_COMPLETELY_PEELED_INSNS. Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com> Signed-off-by: Egor Kochetov <egor.kochetov@intel.com> (cherry picked from commit 1f170f4a426b1ed354345de5aaba634036854e43) Change-Id: Ie395a6602c8305530ebc02f9006d84f98365857a
* [4.9] Add several improvements for AArch64ktkachov2015-09-092-39/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backported from GCC 5. 2015-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Properly handle mvn-register and add EON+shift pattern and cost appropriately * config/aarch64/aarch64.md (*eor_one_cmpl_<SHIFT:optab><mode>3_alt): New pattern. (*eor_one_cmpl_<SHIFT:optab>sidi3_alt_ze): Likewise. * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle MVN-shift appropriately. Handle alternative EON form. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222637 138bc75d-0d04-0410-961f-82ee72b054a4 2015-04-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Properly cost FABD pattern * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle pattern for fabd in ABS case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222638 138bc75d-0d04-0410-961f-82ee72b054a4 2015-05-01 Kyrylo Tkachov <kyrylo.tkachov@arm.com> Remember to cost operand 0 in FP compare-with-0.0 case * config/aarch64/aarch64.c (aarch64_rtx_costs, COMPARE case): Add cost of op0 in the compare-with-fpzero case. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222673 138bc75d-0d04-0410-961f-82ee72b054a4 2015-05-01 Wilco Dijkstra <wdijkstr@arm.com> Fix aarch64_rtx_costs of PLUS/MINUS * gcc/config/aarch64/aarch64.c (aarch64_rtx_costs): Calculate cost of op0 and op1 in PLUS and MINUS cases. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@222676 138bc75d-0d04-0410-961f-82ee72b054a4 2015-07-27 Wilco Dijkstra <wdijkstr@arm.com> Improve spill code - swap order in shl pattern * config/aarch64/aarch64.md (aarch64_ashl_sisd_or_int_<mode>3): Place integer variant first. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226247 138bc75d-0d04-0410-961f-82ee72b054a4 2015-07-27 Wilco Dijkstra <wdijkstr@arm.com> Improve spill code - swap order in shr patterns * gcc/config/aarch64/aarch64.md (aarch64_lshr_sisd_or_int_<mode>3): Place integer variant first. (aarch64_ashr_sisd_or_int_<mode>3): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226253 138bc75d-0d04-0410-961f-82ee72b054a4 2015-08-04 Pawel Kupidura <pawel.kupidura@arm.com> * config/aarch64/aarch64.c: Change inner loop statement cost to be consistent with other targets. Change-Id: If5b10466302d733fcae6eacc9d128fdb8f95c0de git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@226575 138bc75d-0d04-0410-961f-82ee72b054a4
* Merge "[4.9] Adjust several costs for AArch64."Dan Albert2015-09-082-206/+1092
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| * [4.9] Adjust several costs for AArch64.jgreenhalgh2015-08-282-206/+1092
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport from trunk 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Refactor aarch64_address_costs. gcc/ * config/aarch64/aarch64-protos.h (scale_addr_mode_cost): New. (cpu_addrcost_table): Use it. * config/aarch64/aarch64.c (generic_addrcost_table): Initialize it. (aarch64_address_cost): Rewrite using aarch64_classify_address, move it. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210493 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Add cost tables for Cortex-A57 gcc/ * config/aarch64/aarch64.c (cortexa57_addrcost_table): New. (cortexa57_vector_cost): Likewise. (cortexa57_tunings): Use them. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210494 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Better estimate cost of building a constant gcc/ * config/aarch64/aarch64.c (aarch64_build_constant): Conditionally emit instructions, return number of instructions which would be emitted. (aarch64_add_constant): Update call to aarch64_build_constant. (aarch64_output_mi_thunk): Likewise. (aarch64_rtx_costs): Estimate cost of a CONST_INT, cost a CONST_DOUBLE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210496 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Add cost tables for Cortex-A57 gcc/ * config/aarch64/aarch64.c (cortexa57_addrcost_table): New. (cortexa57_vector_cost): Likewise. (cortexa57_tunings): Use them. 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Wrap aarch64_rtx_costs to dump verbose output gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs_wrapper): New. (TARGET_RTX_COSTS): Call it. 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Better estimate cost of building a constant gcc/ * config/aarch64/aarch64.c (aarch64_build_constant): Conditionally emit instructions, return number of instructions which would be emitted. (aarch64_add_constant): Update call to aarch64_build_constant. (aarch64_output_mi_thunk): Likewise. (aarch64_rtx_costs): Estimate cost of a CONST_INT, cost a CONST_DOUBLE. 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Factor out common MULT cases gcc/ * config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename to... (aarch64_strip_extend): ...this, don't strip shifts, check RTX is well formed. (aarch64_rtx_mult_cost): New. (aarch64_rtx_costs): Use it, refactor as appropriate. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210497 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Set default costs and handle vector modes. gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Set default costs. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210498 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philip Tomsich <philipp.tomsich@theobroma-systems.com> Improve SET cost. gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costing for SET RTX. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210499 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philip Tomsich <philipp.tomsich@theobroma-systems.com> Cost memory accesses using address costs gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Use address costs when costing loads and stores to memory. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210500 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philip Tomsich <philipp.tomsich@theobroma-systems.com> Better cost logical operations gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Improve cost for logical operations. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210501 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philip Tomsich <philipp.tomsich@theobroma-systems.com> Improve costs for sign/zero extend operations gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Cost ZERO_EXTEND and SIGN_EXTEND better. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210502 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philip Tomsich <philipp.tomsich@theobroma-systems.com> Improve costs for rotate and shift operations. * config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for rotates and shifts. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210503 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philip Tomsich <philipp.tomsich@theobroma-systems.com> Improve costs for sign/zero extracts gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for SIGN/ZERO_EXTRACT. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210504 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Improve costs for div/mod gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for DIV/MOD. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210505 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cost comparisons, flag setting operators and IF_THEN_ELSE gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Cost comparison operators. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210506 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cost more Floating point RTX. gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Cost FMA, FLOAT_EXTEND, FLOAT_TRUNCATE, ABS, SMAX, and SMIN. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210507 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cost TRUNCATE gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Cost TRUNCATE. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210508 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Cost for SYMBOL_REF, HIGH and LO_SUM gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Cost SYMBOL_REF, HIGH, LO_SUM. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210509 138bc75d-0d04-0410-961f-82ee72b054a4 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Dump a message if we are unable to cost an insn. gcc/ * config/aarch64/aarch64.c (aarch64_rtx_costs): Handle the case where we were unable to cost an RTX. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@210510 138bc75d-0d04-0410-961f-82ee72b054a4 2014-08-26 Evandro Menezes <e.menezes@samsung.com> Fix typos in cost data structure. * config/arm/aarch64/aarch64.c (generic_addrcost_table): Delete qi cost; add di cost. (cortexa57_addrcost_table): Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@214503 138bc75d-0d04-0410-961f-82ee72b054a4
* | Drop mips64r2 from Android compiler's multilibDuane Sand2015-08-271-4/+4
| | | | | | | | Change-Id: Ic2549845a10d16620d492cbf91a8cfc4cb2e6c61
* | Modify LINK_SPEC to pass --fix-cortex-a53-843419 as default.Lai Wei-Chih2015-08-274-2/+20
| | | | | | | | | | | | | | For NDK toolchains, always enable the fix of cortex-a53 erratum 843419. Use -mno-fix-cortex-a53-843419 to disable this workaround. Change-Id: I69b8a71113abb172138bf0986697a94e42a5117e
* | Enable C++ exceptions and RTTI by default.David 'Digit' Turner2015-08-271-2/+2
|/ | | | | With this change, -fexceptions and -frtti become default options when compiling C++ sources.
* Revert "cherrypick GCC trunk 210497", but extract fix for the SEGV from itYiran Wang2015-08-261-254/+110
| | | | | | | BUG=23157315 This reverts commit 659b5199aa009008a003062ff828f44b6bd70b65. Change-Id: I3564560d3aa57c039c6bc78e0cd630cea3a4bb8b
* [4.9] Adjust generic move costs for aarch64. Backport from trunkJunmo Park2015-08-221-2/+4
| | | | | | | | | | 2014-11-19 Wilco Dijkstra <wdijkstr@arm.com> PR target/61915 * config/aarch64/aarch64.c (generic_regmove_cost): Increase FP move cost. Change-Id: Ifaa0c2d1a72955e42f3882c68d1e52acf5a790e7 Signed-off-by: Junmo Park <junmoz.park@samsung.com>
* [4.9] Backport Cortex-A57's machine description support from trunkJunmo Park2015-08-144-5/+803
| | | | | | | | | | | | | | | | | | | | | | | 2015-03-11 Junmo Park <junmoz.park@samsung.com> * config/arm/cortex-a57.md (cortex_a57_crypto_simple): Add crypto_sha256_fast. (cortex_a57_crypto_complex): Add crypto_sha256_slow. 2015-01-16 James Greenhalgh <james.greenhalgh@arm.com> * config/arm/cortex-a57.md: Remove duplicate of file accidentally introduced in revision 219724. 2015-01-16 James Greenhalgh <james.greenhalgh@arm.com> * config/arm/cortex-a57.md: New. * config/aarch64/aarch64.md: Include it. * config/aarch64/aarch64-cores.def (cortex-a57): Tune for it. * config/aarch64/aarch64-tune.md: Regenerate. Change-Id: Id089f9d746c222a7ffe224b69e3249f083bbaf3b Signed-off-by: Junmo Park <junmoz.park@samsung.com>
* cherrypick GCC trunk 210497Yiran Wang2015-08-131-110/+255
| | | | | | | | | | | | | | | | | | BUG=23157315 2014-05-16 James Greenhalgh <james.greenhalgh@arm.com> Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [AArch64 costs 5/18] Factor out common MULT cases gcc/ * config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename to... (aarch64_strip_extend): ...this, don't strip shifts, check RTX is well formed. (aarch64_rtx_mult_cost): New. (aarch64_rtx_costs): Use it, refactor as appropriate. Change-Id: I298e5af1b4006f37d873b113c8d05643e897f6f1
* cherry-pick gcc r217091.Yiran Wang2015-07-081-0/+12
| | | | | | | | | | | | | | | This change is re-based and modified to work with the older context, as the context code is changed a lot in GCC trunk. It is about to insert some barriers on stack-pointer register, so that the adjust-stack-pointer code does not get scheduled before any code in the fuction epilogue, which may access some stack space without explicit use of stack pointer. Examples are a load from an auto array and some access to an area of alloca. Anyway, the barriers would make all such alias dependences not violated. For more details, please refer to GCC bug 63293. (Personally I think there may be a bit too many barriers generated.) Change-Id: I61ea54e500b6965feab69a62165d10b6c3a21c20
* Synchronize with google/gcc-4_9 to r224707 (from r214835)Yiran Wang2015-06-2976-1058/+3459
| | | | Change-Id: I3d6f06fc613c8f8b6a82143dc44b7338483aac5d
* Merge "Add -mno-odd-spreg option as default mode for mips32r6 android builds."Andrew Hsieh2015-05-121-0/+3
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| * Add -mno-odd-spreg option as default mode for mips32r6 android builds.Steve Ellcey2015-05-111-0/+3
| | | | | | | | Change-Id: Id19630f78848dc3ccfa564e2e925f892b8ea4433
* | Remove prototypes for vector builtins for clang.Steve Ellcey2015-05-112-540/+11
|/ | | | | | Fix builtin vector types for 64 bit mode. Change-Id: I0641798eb23646dcd3fc4d5ee623ad4d8dcbd142
* Update MSA Support in MIPS GCC.Steve Ellcey2015-03-1924-2253/+3648
| | | | Change-Id: Id87035be4552719dc05096bb98b49d4bed91a07a
* [4.9] Several improvements in code generation for x86. Backport from trunk.Alexander Ivchenko2015-03-171-24/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2014-11-21 Evgeny Stupachenko <evstupac@gmail.com> PR target/60451 * config/i386/i386.c (expand_vec_perm_even_odd_pack): New. (expand_vec_perm_even_odd_1): Add new expand for V8HI mode, replace for V16QI, V16HI and V32QI modes. (ix86_expand_vec_perm_const_1): Add new expand. 2014-06-11 Evgeny Stupachenko <evstupac@gmail.com> * tree-vect-data-refs.c (vect_grouped_store_supported): New check for stores group of length 3. (vect_permute_store_chain): New permutations for stores group of length 3. * tree-vect-stmts.c (vect_model_store_cost): Change cost of vec_perm_shuffle for the new permutations. 2014-11-28 Evgeny Stupachenko <evstupac@gmail.com> * tree-vect-data-refs.c (vect_transform_grouped_load): Limit shift permutations to loads group of size 3. 2014-12-18 Bin Cheng <bin.cheng@arm.com> PR tree-optimization/62178 * tree-ssa-loop-ivopts.c (cheaper_cost_with_cand): New function. (iv_ca_replace): New function. (try_improve_iv_set): New parameter try_replace_p. Break local optimal fixed-point by calling iv_ca_replace. (find_optimal_iv_set_1): Pass new argument to try_improve_iv_set. Change-Id: I5dca8236d3807cedc5e09d7eda65f0ccec9f5cb2 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Merge "Cherry-pick: Increase PARAM_MAX_COMPLETELY_PEELED_INSNS when branch ↵Andrew Hsieh2015-03-021-6/+0
|\ | | | | | | is costly"
| * Cherry-pick: Increase PARAM_MAX_COMPLETELY_PEELED_INSNS when branch is costlyUros Bizjak2015-02-111-6/+0
| | | | | | | | | | | | | | | | | | | | | | Author: uros <uros@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Sat Nov 22 19:02:12 2014 +0000 * params.def (PARAM_MAX_COMPLETELY_PEELED_INSNS): Increase to 200. * config/i386/i386.c (ix86_option_override_internal): Do not increase PARAM_MAX_COMPLETELY_PEELED_INSNS. Change-Id: I202e14a29f2436872910301efec863afdd4127e7
* | Merge "Revert "[4.9] Disable array bound warning in ARM We are seeing some ↵Rong Xu2015-02-131-7/+0
|\ \ | |/ |/| | | false positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed.""
| * Revert "[4.9] Disable array bound warning in ARM We are seeing some false ↵Andrew Hsieh2015-01-291-7/+0
| | | | | | | | | | | | | | | | positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed." This reverts commit 407a2d5c2c63bdc0c842ffcd57a139ef8a4f33e2, because https://android-review.googlesource.com/#/c/125800 provides fixes to root cause. Change-Id: I3ceda349beca8e558ccfac5602de942b9be4d31d
* | Merge "[4.9] Another backport from trunk of additional slm tuning."Andrew Hsieh2014-12-081-0/+6
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| * [4.9] Another backport from trunk of additional slm tuning.Alexander Ivchenko2014-12-031-0/+6
| | | | | | | | | | | | | | | | | | | | 2014-11-21 Evgeny Stupachenko <evstupac@gmail.com> * config/i386/i386.c (ix86_option_override_internal): Increase PARAM_MAX_COMPLETELY_PEELED_INSNS. Change-Id: I529a9297cb8d230a5821d73d5b462d433a8c2108 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* | [4.9] Disable array bound warning in ARMRong Xu2014-12-031-0/+7
|/ | | | | | | | | We are seeing some false positive array bound warnings due to an issue in complete unroll. This patch disables this warning so we can switch the ARM build to 4.9. Will re-enable the warning once the issue is fixed. Change-Id: Ifefe470b9e9146665e9096e5ac6f2f5fec7b9627
* [4.9] Backport from trunk of some additional slm tuning.Alexander Ivchenko2014-11-191-2/+2
| | | | | | | | | | 2014-10-13 Evgeny Stupachenko <evstupac@gmail.com> * config/i386/x86-tune.def (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Remove m_SILVERMONT and m_INTEL from the tune. Change-Id: I5d793525c43015f10f15cd46505e326039dd4b7e Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* [4.9] Restore recog state after finding pre-madd instruction.Rong Xu2014-11-051-0/+4
| | | | | | | This patch backports svn r216853 from upsteam gcc-4.9 branch that fixed a bug introduced in fixing cortex a53 erratum 835769. Change-Id: Iccc6fd04ede28c2deba51be3f8e348ce374c8b4f
* [4.9] Android fix for Cortex-A53 erratum 835769 workaroundRong Xu2014-10-311-3/+4
| | | | | | | | Android does not use the LINK_SPEC in aarch64-linux.h. Rather, it picks up LINUX_TARGET_LINK_SPEC. Move the SPEC change in r216979 to LINUX_TRAGET_LINK_SPEC. Change-Id: I6c39522efcfe067a8a66397954b386f5d104dc02
* [4.9] LINK_SPEC changes for Cortex-A53 erratum 835769 workaroundRong Xu2014-10-312-2/+20
| | | | | | This is proted from upstream gcc-4_9 branch: svn r216979. Change-Id: I1cee530fb4f50843a9832aa678c1630f51564fa6
* Merge "[4.9] Backport r216764: Enable ifunc for BINOIC Backport r216764 from ↵Rong Xu2014-10-271-1/+1
|\ | | | | | | google/gcc-4_9 branches which makes ifunc support available for BIONIC (still controlled by configure)."
| * [4.9] Backport r216764: Enable ifunc for BINOICRong Xu2014-10-271-1/+1
| | | | | | | | | | | | | | Backport r216764 from google/gcc-4_9 branches which makes ifunc support available for BIONIC (still controlled by configure). Change-Id: I515d4d38e11bd0378899e64e68ab5b255e2c6df3
* | Merge "[gcc] Remove "-mstackrealign" option turned on by default on x86."Andrew Hsieh2014-10-162-2/+2
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| * | [gcc] Remove "-mstackrealign" option turned on by default on x86.Alexander Ivchenko2014-10-142-2/+2
| |/ | | | | | | | | | | | | | | For ndk docs change, please refer to: https://android-review.googlesource.com/#/c/110100/ Change-Id: Icbe13a158511d519312b2a1d3e606c9dd2bff4af Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* / [gcc-4.9] fix for for cortex-a53 erratum 835769Rong Xu2014-10-134-0/+146
|/ | | | | | | | This patch cherry picks r216116 from google/gcc-4_9 branch (which is r216077 and r216079 from upstream gcc-4_9 branch). Tested the built compiler with aarch64 devicde. Change-Id: I75745fe35aae83bc3b64135a2efc7f8ffd9cfb1f
* Merge "Change aarch64-linux-android dynamic linker to /system/bin/linker64"Andrew Hsieh2014-09-151-0/+2
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| * Change aarch64-linux-android dynamic linker to /system/bin/linker64Andrew Hsieh2014-09-081-0/+2
| | | | | | | | | | | | | | | | | | Set bionic linker to /system/bin/linker64 for aarch64 in Android. The default /system/bin/linker causes run-time error reads: /system/bin/sh: /path/to/your/app: Accessing a corrupted shared library Change-Id: Ieaaebd267c87e7803372171478ae8f8b9ab71dfe
* | [4.6,4.8,4.9] Neon2SSE porting solution updatePavel Chupin2014-09-121-3051/+11030
|/ | | | | | | | | | Improve NEON instrinsics coverage from ~41% to ~93%. This change brings new intrinsics and modifies old ones for better maintainability. Also take into account that IA32 now supports SSSE3 by default, so we can get rid of SSSE3 checks. Change-Id: I599c3b93dcf92d0c94bdb786a4aad705f075893b Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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