| Commit message (Collapse) | Author | Age | Files | Lines |
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With this change, -fexceptions and -frtti become default options
when compiling C++ sources.
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2014-06-30 Joseph Myers <joseph@codesourcery.com>
* var-tracking.c (add_stores): Return instead of asserting if old
and new values for conditional store are the same.
Change-Id: Ibb5775a3ad90e57bd6882a86a6b4c7a5262c09d0
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For ndk docs change, please refer to:
https://android-review.googlesource.com/#/c/110100/
Change-Id: Icbe13a158511d519312b2a1d3e606c9dd2bff4af
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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Improve NEON instrinsics coverage from ~41% to ~93%. This change brings
new intrinsics and modifies old ones for better maintainability.
Also take into account that IA32 now supports SSSE3 by default, so we
can get rid of SSSE3 checks.
Change-Id: I599c3b93dcf92d0c94bdb786a4aad705f075893b
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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For multilib compiler x86_64-* we need to pass compiler ABI flags based on
flags -m32 or -m64, and no flags means -m64. But for 32-bit target compiler
i686-* we should pass 32-bit ABI flags only. This change fixes the last part.
Change-Id: I00adf4b633952f7a5fde5dc18ca4926a349472cd
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Six patches from trunk, reg-tested via 'make check':
2014-05-07 Evgeny Stupachenko <evstupac@gmail.com>
* tree-vect-data-refs.c (vect_grouped_load_supported): New
check for loads group of length 3.
(vect_permute_load_chain): New permutations for loads group of
length 3.
* tree-vect-stmts.c (vect_model_load_cost): Change cost
of vec_perm_shuffle for the new permutations.
2014-04-17 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/i386.c (x86_add_stmt_cost): Fix vector cost model for
Silvermont.
2014-04-17 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/x86-tune.def (TARGET_SLOW_PSHUFB): New tune definition.
* config/i386/i386.h (TARGET_SLOW_PSHUFB): New tune flag.
* config/i386/i386.c (expand_vec_perm_even_odd_1): Avoid byte shuffles
for TARGET_SLOW_PSHUFB
2014-04-17 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/i386.c (slm_cost): Adjust vec_to_scalar_cost.
* config/i386/i386.c (intel_cost): Ditto.
2014-06-18 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/i386.c (ix86_reassociation_width): Add alternative for
vector case.
* config/i386/i386.h (TARGET_VECTOR_PARALLEL_EXECUTION): New.
* config/i386/x86-tune.def (X86_TUNE_VECTOR_PARALLEL_EXECUTION): New.
* tree-vect-data-refs.c (vect_shift_permute_load_chain): New.
Introduces alternative way of loads group permutaions.
(vect_transform_grouped_load): Try alternative way of permutations.
2014-06-05 Evgeny Stupachenko <evstupac@gmail.com>
* config/i386/sse.md (*ssse3_palignr<mode>_perm): New.
* config/i386/predicates.md (palignr_operand): New.
Indicates if permutation is suitable for palignr instruction.
Change-Id: I5e505735ce3dc0ec3c2a1151713a119b24d712fe
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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BUG=15526898
Change-Id: I4e35a764d369d378808dab29beefe34d1f93249b
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Reapplying https://android-review.googlesource.com/#/c/80436 after 4.8.3
merge
Change-Id: Ie14bec963d609507e8b2c2c8d20df007f77eabe6
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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Reapplying https://android-review.googlesource.com/#/c/71782 after 4.8.3
merge
Change-Id: Ia29210fc489a73e4c20ca1f6a0907f93746a0413
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Reapplying https://android-review.googlesource.com/#/c/60083 after 4.8.3
merge
Change-Id: I93a985ae43d9349ed3fa0dd37e485f5477774f37
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Reapplying https://android-review.googlesource.com/#/c/59726 after 4.8.3
merge
Change-Id: I855de6c963d423f68899f90aada1758ae6f6c0d9
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Change-Id: I0abe59f7705b3eccc6b2f123af75b2e30917696a
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For the purpose of merging gcc-4.8.3, will put it back.
https://android-review.googlesource.com/#/c/59726
[4.7, 4.8] Release basic tuning for new Silvermont architecture
Change-Id: Id2b9e714418b3cf0a7eef0f599c39ba81df47d13
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For the purpose of merging gcc-4.8.3, will put it back.
https://android-review.googlesource.com/#/c/60083
[4.7, 4.8] Extended Silvermont tuning
Change-Id: If13a6989286c0ab57def1dd65f0bbd2f6ed8d807
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For the purpose of merging gcc-4.8.3, will put it back.
https://android-review.googlesource.com/#/c/71782
[4.6, 4.8] Add -mtune=intel support
Change-Id: Ie340828ac3809fd6694985dd52c3392b661fb9b2
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For the purpose of merging gcc-4.8.3, will put it back.
https://android-review.googlesource.com/#/c/80436
[4.7, 4.8] Backport of two patches for additional SLM-tuning.
Change-Id: I4e5e08ee8c6a9f863b4696a6eb18c2cdbf16cd1f
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32-bit: replace -msse3 by -mssse3
64-bit: setup default options as -msse4.2 -mpopcnt
Note: when multilib compiler is used -m32 will match 32-bit options and
-m64 or default (neither -m32 nor -m64) will match 64-bit options.
Change-Id: Ia20a03f54e3ff5857108e9ab0ae1c4c7c1e6cc7f
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Added arm_neon.h to gcc 4.6, 4.8 and 4.9 toolchains. Updated config.gcc files.
Change-Id: If9c12c3e31f5256b178816dffb41c86af0912db0
Signed-off-by: Anton Konovalov <anton.konovalov@intel.com>
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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To use FP_LO_REGS for the 2nd SIMD register with h[index]
See:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/SQDMULH_advsimd_elt_scalar.html
Google BUG 14825026
Change-Id: Ifd870e8ab851d93bda6734aee04d09db17461bdd
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For critical bug fixes including devirtualization and codegen.
Change-Id: I8138d3dc408fc12db5eecb01d2753d39219712f2
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This pass optimize GOT_PREL (already exists in toolchain/gcc/gcc-4.6)
Backport from svn://gcc.gnu.org/svn/gcc/branches/google/gcc-4_6-mobile
UNSPEC_GOT_PREL_SYM is now in new file arm/unspecs.md
4.9 port is slightly different due to changes in gcc passes
See Google b/14811006
r173209 | carrot | 2011-04-30 16:07:46 +0800 (Sat, 30 Apr 2011) | 21 lines
* hooks.c (hook_rtx_void_null): New function.
* hooks.h (hook_rtx_void_null): New prototype.
* target.def (got_access): New hook vector declaration.
* tree-pass.h (pass_simplify_got): New pass.
* timevar.def (TV_SIMPLIFY_GOT): New TV id.
* simplify-got.c: New source file.
* Makefile.in (simplify-got.o): Add a new file.
* passes.c (init_optimization_passes): Add a new pass.
* config/arm/arm.c (arm_output_addr_const_extra): Output GOT_PREL
relocation.
(arm_get_pic_reg): New function.
(arm_clear_pic_reg): New function.
(arm_can_simplify_got_access): New function.
(arm_loaded_global_var): New function.
(arm_load_global_address): New function.
* config/arm/arm.md (UNSPEC_GOT_PREL_SYM): New UNSPEC symbol.
* testsuite/gcc.target/arm/got1.c: New testcase.
* testsuite/gcc.target/arm/got2.c: New testcase.
Change-Id: I91e881df19bb6937a5fbcc8e6b83d158717c7773
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See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59695
http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=206703
2014-01-17 Kugan Vivekanandarajah <kuganv@linaro.org>
Backport from mainline
2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org>
Kugan Vivekanandarajah <kuganv@linaro.org>
PR target/59695
* config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect
truncation.
Change-Id: I94f2c9ad01ed489b4a167ce67a34365db37a8200
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Backport upstream patch which adds -maarch64linux for linker.
eg. ld.mcld may support multiple targets, and more likely
than not needs explicit emulation switch
[AArch64] Define BE loader name.
2014-01-20 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER): Expand
loader name using mbig-endian.
(LINUX_TARGET_LINK_SPEC): Pass linker -m flag.
Change-Id: I2d10f85fbdf5c998d17098c1381ecad628922ba0
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Change-Id: Id343d7a1b74dea14cc0856cfc1e230a01db7c740
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Backport of r207428:
2014-02-03 H.J. Lu <hongjiu.lu@intel.com>
gcc/
* config/i386/i386.c (flag_opts): Add -mlong-double-128.
(ix86_option_override_internal): Default long double to 64-bit for
32-bit Bionic and to 128-bit for 64-bit Bionic.
* config/i386/i386.h (LONG_DOUBLE_TYPE_SIZE): Use 128 if
TARGET_LONG_DOUBLE_128 is true.
(LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Likewise.
* config/i386/i386.opt (mlong-double-80): Negate -mlong-double-64.
(mlong-double-64): Negate -mlong-double-128.
(mlong-double-128): New option.
* config/i386/i386-c.c (ix86_target_macros): Define
__LONG_DOUBLE_128__ for TARGET_LONG_DOUBLE_128.
* doc/invoke.texi: Document -mlong-double-128.
gcc/testsuite/
* gcc.target/i386/long-double-64-1.c: Verify __multf3 isn't used.
* gcc.target/i386/long-double-64-4.c: Likewise.
* gcc.target/i386/long-double-80-1.c: Likewise.
* gcc.target/i386/long-double-80-2.c: Likewise.
* gcc.target/i386/long-double-80-3.c: Likewise.
* gcc.target/i386/long-double-80-4.c: Likewise.
* gcc.target/i386/long-double-80-5.c: Likewise.
* gcc.target/i386/long-double-64-2.c: Limit to ia32. Verify
__multf3 isn't used.
* gcc.target/i386/long-double-64-3.c: Likewise.
* gcc.target/i386/long-double-128-1.c: New test.
* gcc.target/i386/long-double-128-2.c: Likewise.
* gcc.target/i386/long-double-128-3.c: Likewise.
* gcc.target/i386/long-double-128-4.c: Likewise.
* gcc.target/i386/long-double-128-5.c: Likewise.
* gcc.target/i386/long-double-128-6.c: Likewise.
* gcc.target/i386/long-double-128-7.c: Likewise.
* gcc.target/i386/long-double-128-8.c: Likewise.
* gcc.target/i386/long-double-128-9.c: Likewise.
* gcc.target/i386/long-double-64-5.c: Likewise.
* gcc.target/i386/long-double-64-6.c: Likewise.
* gcc.target/i386/long-double-64-7.c: Likewise.
* gcc.target/i386/long-double-64-8.c: Likewise.
* gcc.target/i386/long-double-64-9.c: Likewise.
* gcc.target/i386/long-double-80-10.c: Likewise.
* gcc.target/i386/long-double-80-8.c: Likewise.
* gcc.target/i386/long-double-80-9.c: Likewise.
Change-Id: I2e1ce44792dd78df521fa485f2c0d2303dbb83bd
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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Flags include:
- CC1_SPEC
- CC1PLUS_SPEC
- LIB_SPEC
- STARTFILE_SPEC
- ENDFILE_SPEC
Change-Id: Ia96ca57ade849c964c91f5390e6c9cded16a9bf4
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We don't have config/i386/x86-tune.def in 4.8, instead
initial_ix86_tune_features is modified. This one is for 4.8 only.
2013-09-12 Yuri Rumyantsev <ysrumyan@gmail.com>
* config/i386/x86-tune.def: Turn on X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE
for SLM.
Update HImode imul cost for Silvermont
2013-12-13 Yuri Rumyantsev <ysrumyan@gmail.com>
* config/i386/i386.c (slm_cost): Fix imul cost for HI.
Change-Id: I3e6e7b157897e93bc3874738635db4ecf4e7f587
Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
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Only available with "-march=armv7-a", this CL add two set of libraries
1. "armv7-a/hard": -march=armv7-a -mfloat-abi=hard
2. "armv7-a/thumb/hard": -march=armv7-a -mthumb -mfloat-abi=hard
Note that -mhard-float implies -mfloat-abi=hard, which in turns select
one of the above /hard libraries dependeing on the presence of -mthumb
or not. (ie. no need to explicitly specifly -mfloat-abi=hard after -mhard-float)
Change-Id: Ib803ecaa911082d6bc4f98b542d7d28e98be6726
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2013-12-05 Jason Merrill <jason@redhat.com>
PR c++/59044
PR c++/59052
* pt.c (most_specialized_class): Use the partially instantiated
template for deduction. Drop the TMPL parameter.
See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59052
Change-Id: I4760e719def2f5eacac438af2df0b18c1f2d16a8
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This is to match the existing behavior of 32-bit toolchains.
For example in gcc/config/arm/linux-eabi.h it has the following:
do
{
TARGET_BPABI_CPP_BUILTINS();
GNU_USER_TARGET_OS_CPP_BUILTINS();
ANDROID_TARGET_OS_CPP_BUILTINS();
}
while (false)
I'll try to upstream this patch.
Change-Id: I22aa6ba5a0d7b5c9cd5a314f7079dc1edd2d382c
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This is backport of r205719 and r205754 from trunk.
Now -mtune=intel matches -mtune=slm for 4.8 and -mtune=atom for 4.6.
As written in gcc-4.8 docs:
Produce code optimized for the most current Intel processors, which are
Haswell and Silvermont for this version of GCC. If you know the CPU
on which your code will run, then you should use the corresponding
-mtune or -march option instead of -mtune=intel.
But, if you want your application performs better on both Haswell and
Silvermont, then you should use this option.
As new Intel processors are deployed in the marketplace, the behavior of
this option will change. Therefore, if you upgrade to a newer version of
GCC, code generation controlled by this option will change to reflect
the most current Intel processors at the time that version of GCC is
released.
There is no -march=intel option because -march indicates
the instruction set the compiler can use, and there is no common
instruction set applicable to all processors. In contrast,
-mtune indicates the processor (or, in this case, collection of
processors) for which the code is optimized.
Change-Id: I3ec4c3b5423d9b3547cd8e3aa77a18af3fd89598
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
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1. *.orig files are artifact after patch
2. restore 3 testdata which were reset to zero-byte in last rebase
Change-Id: I32e80c33349249cb11397b57698c2a241793652c
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Change-Id: I0f1fcf69c5076d8534c5c45562745e1a37adb197
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Error message reads:
cc1: internal compiler error: in common_handle_option, at opts.c:1774
Change-Id: I9a6e42811f0ec83d3a6c05a8bb9b1ec0e5a7144a
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