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* [4.8, REAPPLY] Release basic tuning for new Silvermont architecturePavel Chupin2014-06-196-25/+882
| | | | | | | | Reapplying https://android-review.googlesource.com/#/c/59726 after 4.8.3 merge Change-Id: I855de6c963d423f68899f90aada1758ae6f6c0d9 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Merge GCC 4.8.3Andrew Hsieh2014-06-19104-4722/+16860
| | | | Change-Id: I0abe59f7705b3eccc6b2f123af75b2e30917696a
* revert 41eff3d706b202f682f64fcc7773c64abd59ac45Andrew Hsieh2014-06-196-885/+26
| | | | | | | | | For the purpose of merging gcc-4.8.3, will put it back. https://android-review.googlesource.com/#/c/59726 [4.7, 4.8] Release basic tuning for new Silvermont architecture Change-Id: Id2b9e714418b3cf0a7eef0f599c39ba81df47d13
* revert 01b34967a57ca33621130d36e007214b93bdfeaaAndrew Hsieh2014-06-193-320/+79
| | | | | | | | | For the purpose of merging gcc-4.8.3, will put it back. https://android-review.googlesource.com/#/c/60083 [4.7, 4.8] Extended Silvermont tuning Change-Id: If13a6989286c0ab57def1dd65f0bbd2f6ed8d807
* revert 03518e5fd50ca1389a55a9d443d7277ec03d1cdeAndrew Hsieh2014-06-192-8/+0
| | | | | | | | | For the purpose of merging gcc-4.8.3, will put it back. https://android-review.googlesource.com/#/c/71782 [4.6, 4.8] Add -mtune=intel support Change-Id: Ie340828ac3809fd6694985dd52c3392b661fb9b2
* revert a108aa5cbab7efe4eedd19f68d7a9bbe021b2168Andrew Hsieh2014-06-191-2/+2
| | | | | | | | | For the purpose of merging gcc-4.8.3, will put it back. https://android-review.googlesource.com/#/c/80436 [4.7, 4.8] Backport of two patches for additional SLM-tuning. Change-Id: I4e5e08ee8c6a9f863b4696a6eb18c2cdbf16cd1f
* [4.6,4.8,4.9] Porting ARM NEON intrinsics to SSE x86Anton Konovalov2014-06-071-0/+8641
| | | | | | | | Added arm_neon.h to gcc 4.6, 4.8 and 4.9 toolchains. Updated config.gcc files. Change-Id: If9c12c3e31f5256b178816dffb41c86af0912db0 Signed-off-by: Anton Konovalov <anton.konovalov@intel.com> Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Merge "[4.8, 4.9] Fix aarch64/arm_neon.h vqdmulh_n_s16"Andrew Hsieh2014-05-271-74/+74
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| * [4.8, 4.9] Fix aarch64/arm_neon.h vqdmulh_n_s16Andrew Hsieh2014-05-201-74/+74
| | | | | | | | | | | | | | | | | | | | To use FP_LO_REGS for the 2nd SIMD register with h[index] See: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61202 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802a/SQDMULH_advsimd_elt_scalar.html Google BUG 14825026 Change-Id: Ifd870e8ab851d93bda6734aee04d09db17461bdd
* | [4.9] Refresh GCC 4.9 to the 20140514 snapshot.Ben Cheng2014-05-171-11/+11
|/ | | | | | For critical bug fixes including devirtualization and codegen. Change-Id: I8138d3dc408fc12db5eecb01d2753d39219712f2
* [4.8, 4.9] Add simplify-gotCarrot Wei2014-05-152-0/+221
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass optimize GOT_PREL (already exists in toolchain/gcc/gcc-4.6) Backport from svn://gcc.gnu.org/svn/gcc/branches/google/gcc-4_6-mobile UNSPEC_GOT_PREL_SYM is now in new file arm/unspecs.md 4.9 port is slightly different due to changes in gcc passes See Google b/14811006 r173209 | carrot | 2011-04-30 16:07:46 +0800 (Sat, 30 Apr 2011) | 21 lines * hooks.c (hook_rtx_void_null): New function. * hooks.h (hook_rtx_void_null): New prototype. * target.def (got_access): New hook vector declaration. * tree-pass.h (pass_simplify_got): New pass. * timevar.def (TV_SIMPLIFY_GOT): New TV id. * simplify-got.c: New source file. * Makefile.in (simplify-got.o): Add a new file. * passes.c (init_optimization_passes): Add a new pass. * config/arm/arm.c (arm_output_addr_const_extra): Output GOT_PREL relocation. (arm_get_pic_reg): New function. (arm_clear_pic_reg): New function. (arm_can_simplify_got_access): New function. (arm_loaded_global_var): New function. (arm_load_global_address): New function. * config/arm/arm.md (UNSPEC_GOT_PREL_SYM): New UNSPEC symbol. * testsuite/gcc.target/arm/got1.c: New testcase. * testsuite/gcc.target/arm/got2.c: New testcase. Change-Id: I91e881df19bb6937a5fbcc8e6b83d158717c7773
* [4.8] Backport fix on bad aarch64 codegen in multiple inheritance thunksAndrew Hsieh2014-04-241-1/+1
| | | | | | | | | | | | | | | | | See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59695 http://gcc.gnu.org/viewcvs/gcc?view=revision&revision=206703 2014-01-17 Kugan Vivekanandarajah <kuganv@linaro.org> Backport from mainline 2014-01-15 Matthew Gretton-Dann <matthew.gretton-dann@linaro.org> Kugan Vivekanandarajah <kuganv@linaro.org> PR target/59695 * config/aarch64/aarch64.c (aarch64_build_constant): Fix incorrect truncation. Change-Id: I94f2c9ad01ed489b4a167ce67a34365db37a8200
* Pass link -maarch64linux flagAndrew Hsieh2014-04-151-2/+3
| | | | | | | | | | | | | | | | Backport upstream patch which adds -maarch64linux for linker. eg. ld.mcld may support multiple targets, and more likely than not needs explicit emulation switch [AArch64] Define BE loader name. 2014-01-20 Marcus Shawcroft <marcus.shawcroft@arm.com> * config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER): Expand loader name using mbig-endian. (LINUX_TARGET_LINK_SPEC): Pass linker -m flag. Change-Id: I2d10f85fbdf5c998d17098c1381ecad628922ba0
* Merge "Define bionic aarch64 linker path."Andrew Hsieh2014-02-061-0/+1
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| * Define bionic aarch64 linker path.Ben Cheng2014-02-051-0/+1
| | | | | | | | Change-Id: Id343d7a1b74dea14cc0856cfc1e230a01db7c740
* | Merge "[4.8] Add -mlong-double-128 and make it default for 64-bit Bionic"Andrew Hsieh2014-02-064-6/+26
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| * [4.8] Add -mlong-double-128 and make it default for 64-bit BionicPavel Chupin2014-02-054-6/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport of r207428: 2014-02-03 H.J. Lu <hongjiu.lu@intel.com> gcc/ * config/i386/i386.c (flag_opts): Add -mlong-double-128. (ix86_option_override_internal): Default long double to 64-bit for 32-bit Bionic and to 128-bit for 64-bit Bionic. * config/i386/i386.h (LONG_DOUBLE_TYPE_SIZE): Use 128 if TARGET_LONG_DOUBLE_128 is true. (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Likewise. * config/i386/i386.opt (mlong-double-80): Negate -mlong-double-64. (mlong-double-64): Negate -mlong-double-128. (mlong-double-128): New option. * config/i386/i386-c.c (ix86_target_macros): Define __LONG_DOUBLE_128__ for TARGET_LONG_DOUBLE_128. * doc/invoke.texi: Document -mlong-double-128. gcc/testsuite/ * gcc.target/i386/long-double-64-1.c: Verify __multf3 isn't used. * gcc.target/i386/long-double-64-4.c: Likewise. * gcc.target/i386/long-double-80-1.c: Likewise. * gcc.target/i386/long-double-80-2.c: Likewise. * gcc.target/i386/long-double-80-3.c: Likewise. * gcc.target/i386/long-double-80-4.c: Likewise. * gcc.target/i386/long-double-80-5.c: Likewise. * gcc.target/i386/long-double-64-2.c: Limit to ia32. Verify __multf3 isn't used. * gcc.target/i386/long-double-64-3.c: Likewise. * gcc.target/i386/long-double-128-1.c: New test. * gcc.target/i386/long-double-128-2.c: Likewise. * gcc.target/i386/long-double-128-3.c: Likewise. * gcc.target/i386/long-double-128-4.c: Likewise. * gcc.target/i386/long-double-128-5.c: Likewise. * gcc.target/i386/long-double-128-6.c: Likewise. * gcc.target/i386/long-double-128-7.c: Likewise. * gcc.target/i386/long-double-128-8.c: Likewise. * gcc.target/i386/long-double-128-9.c: Likewise. * gcc.target/i386/long-double-64-5.c: Likewise. * gcc.target/i386/long-double-64-6.c: Likewise. * gcc.target/i386/long-double-64-7.c: Likewise. * gcc.target/i386/long-double-64-8.c: Likewise. * gcc.target/i386/long-double-64-9.c: Likewise. * gcc.target/i386/long-double-80-10.c: Likewise. * gcc.target/i386/long-double-80-8.c: Likewise. * gcc.target/i386/long-double-80-9.c: Likewise. Change-Id: I2e1ce44792dd78df521fa485f2c0d2303dbb83bd Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* | Merge "Fix aarch64 to use Android specs."Ben Cheng2014-02-051-0/+21
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| * | Fix aarch64 to use Android specs.Ben Cheng2014-02-041-0/+21
| |/ | | | | | | | | | | | | | | | | | | | | Flags include: - CC1_SPEC - CC1PLUS_SPEC - LIB_SPEC - STARTFILE_SPEC - ENDFILE_SPEC Change-Id: Ia96ca57ade849c964c91f5390e6c9cded16a9bf4
* / [4.7, 4.8] Backport of two patches for additional SLM-tuning.Alexander Ivchenko2014-01-301-2/+2
|/ | | | | | | | | | | | | | | | | | | We don't have config/i386/x86-tune.def in 4.8, instead initial_ix86_tune_features is modified. This one is for 4.8 only. 2013-09-12 Yuri Rumyantsev <ysrumyan@gmail.com> * config/i386/x86-tune.def: Turn on X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE for SLM. Update HImode imul cost for Silvermont 2013-12-13 Yuri Rumyantsev <ysrumyan@gmail.com> * config/i386/i386.c (slm_cost): Fix imul cost for HI. Change-Id: I3e6e7b157897e93bc3874738635db4ecf4e7f587 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* [4.6, 4.8] Add additional multilib option: mfloat-abi=hardAndrew Hsieh2013-12-262-4/+5
| | | | | | | | | | | | Only available with "-march=armv7-a", this CL add two set of libraries 1. "armv7-a/hard": -march=armv7-a -mfloat-abi=hard 2. "armv7-a/thumb/hard": -march=armv7-a -mthumb -mfloat-abi=hard Note that -mhard-float implies -mfloat-abi=hard, which in turns select one of the above /hard libraries dependeing on the presence of -mthumb or not. (ie. no need to explicitly specifly -mfloat-abi=hard after -mhard-float) Change-Id: Ib803ecaa911082d6bc4f98b542d7d28e98be6726
* Add built-in macro __ANDROID__ for aarch64-linux-android-gccBen Cheng2013-12-121-0/+1
| | | | | | | | | | | | | | | | | This is to match the existing behavior of 32-bit toolchains. For example in gcc/config/arm/linux-eabi.h it has the following: do { TARGET_BPABI_CPP_BUILTINS(); GNU_USER_TARGET_OS_CPP_BUILTINS(); ANDROID_TARGET_OS_CPP_BUILTINS(); } while (false) I'll try to upstream this patch. Change-Id: I22aa6ba5a0d7b5c9cd5a314f7079dc1edd2d382c
* [4.6, 4.8] Add -mtune=intel supportPavel Chupin2013-12-092-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is backport of r205719 and r205754 from trunk. Now -mtune=intel matches -mtune=slm for 4.8 and -mtune=atom for 4.6. As written in gcc-4.8 docs: Produce code optimized for the most current Intel processors, which are Haswell and Silvermont for this version of GCC. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=intel. But, if you want your application performs better on both Haswell and Silvermont, then you should use this option. As new Intel processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the most current Intel processors at the time that version of GCC is released. There is no -march=intel option because -march indicates the instruction set the compiler can use, and there is no common instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized. Change-Id: I3ec4c3b5423d9b3547cd8e3aa77a18af3fd89598 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Remove *.orig; update libgo testdataAndrew Hsieh2013-12-033-88484/+0
| | | | | | | 1. *.orig files are artifact after patch 2. restore 3 testdata which were reset to zero-byte in last rebase Change-Id: I32e80c33349249cb11397b57698c2a241793652c
* Merge "[4.8] Merge GCC 4.8.2"Andrew Hsieh2013-12-0361-1223/+91029
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| * [4.8] Merge GCC 4.8.2synergydev2013-10-1761-1223/+91029
| | | | | | | | Change-Id: I0f1fcf69c5076d8534c5c45562745e1a37adb197
* | [4.8] Backport revision 204203 to fix 3.4 kernel compilation.Ben Cheng2013-10-301-0/+1
|/ | | | | | | | | | 2013-10-30 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/58854 * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit * blockage. Change-Id: I6edddcf212f4185ab55a3a17bc7a80b1ab6b64b7
* Extend MIPS GCC4.6/4.7/4.8 -mldc1-sdc1 to control ldxc1/sdxc1 tooIceberg Fu2013-08-302-3/+3
| | | | | | | | | | | | | -mldc1-sdc1 now also controls codegen of ldxc1/sdxc1, the indexed versions (where address of load/store is computed from sum of two registers) of ldc1/sdc1 which are already controlled by this option. Although double (or struct containing double) is always aligned and the stock does guarantee 8-byte alignment, this option is to workaround issue when double is allocated from a custom allocator w/o honoring 8-byte minimal alignment. Change-Id: I79433976509b885b5699d62693fd3154bb752abf
* Add MXU support in gcc4.6/4.7/4.8 with -mmxuAndrew Hsieh2013-08-152-0/+5
| | | | | | For Ingenic MXU. Change-Id: Ie7b465c971e3642b3244ac1a77b6f86be4ab4fea
* Merge "[4.8] Always enable --eh-frame-hdr for static executable"Andrew Hsieh2013-08-076-1/+25
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| * [4.8] Always enable --eh-frame-hdr for static executableH.J. Lu2013-08-076-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See 23e3137ee2897464b051599b85a09f130d3ad05d for the reason why Port patch from http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00969.html gcc/ 2012-09-14 H.J. Lu <hongjiu.lu@intel.com> PR debug/54568 * configure.ac: Add --enable-eh-frame-hdr-for-static. Set USE_EH_FRAME_HDR_FOR_STATIC if PT_GNU_EH_FRAME is supported for static executable. * config.in: Regenerated. * configure: Likewise. * config/gnu-user.h (LINK_EH_SPEC): Defined as "--eh-frame-hdr " if USE_EH_FRAME_HDR_FOR_STATIC is defined. * config/sol2.h (LINK_EH_SPEC): Likewise. * config/openbsd.h (LINK_EH_SPEC): Likewise. * config/alpha/elf.h (LINK_EH_SPEC): Likewise. * config/freebsd.h (LINK_EH_SPEC): Likewise. * config/rs6000/sysv4.h (LINK_EH_SPEC): Likewise. gcc/testsuite/ 2012-09-13 H.J. Lu <hongjiu.lu@intel.com> PR debug/54568 * g++.dg/eh/spec3-static.C: New test. libgcc/ 2012-09-14 H.J. Lu <hongjiu.lu@intel.com> PR debug/54568 * crtstuff.c (USE_PT_GNU_EH_FRAME): Check CRTSTUFFT_O together with USE_EH_FRAME_HDR_FOR_STATIC. Change-Id: If442d27eeb1347ac5a1b943acbbeff5f708a9929
* | [4.8] Simplify GCC 4.8 BASE-VERAndrew Hsieh2013-08-071-1/+1
|/ | | | | | | | | Change 4.8.1 -> 4.8 to simplify and shield NDK make-standalone-toolchain.sh from gcc minor version upgrade Also correct a comment based on upstream Change-Id: I95791e24937d02fffa6e116761d834705020c911
* Merge "Add an internal switch -minline-thumb1-jumptable to ARM gcc4.6/4.7/4.8"Andrew Hsieh2013-08-074-3/+9
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| * Add an internal switch -minline-thumb1-jumptable to ARM gcc4.6/4.7/4.8Lai Wei-Chih2013-08-024-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default is off (ie. no changes of behavior), meaning that gcc may generate thumb1 jumptable helper calls (eg. __gnu_thumb1_case_sqi) for switch/case. Use -minline-thumb1-jumptable to compile code which can be linked with compiler-rt where helper __gnu_thumb1_case_* doesn't exist. This is mainly for use to compile NDK gabi++/stlport/libc++ to be independent of libgcc.a. The only affected binaries are all in armeabi. ABIs armeabi-v7a and x86/mips aren't affected. Size differences are libgabi++_static.a 176286 -> 176538 +0.1% libstlport_static.a 1406346 -> 1413318 +0.5% libc++_static.a 2426814 -> 2439074 +0.5% Change-Id: I582898955b28e53e988a91bc1a64b76fba677e58
* | [4.8] Merge GCC 4.8.1Ben Cheng2013-08-0535-559/+952
|/ | | | Change-Id: Ic8a60b7563f5172440fd40788605163a0cca6e30
* [4.7, 4.8] Extended Silvermont tuning.Pavel Chupin2013-06-043-79/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport r199546 from trunk: 2013-05-31 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com> Igor Zamyatin <igor.zamyatin@intel.com> Silvermont (SLM) architecture performance tuning. * config/i386/i386.h (enum ix86_tune_indices): Add X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS. (TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS): New define. * config/i386/i386.c (initial_ix86_tune_features) <X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS>: Initialize. (ix86_lea_outperforms): Handle Silvermont tuning. (ix86_avoid_lea_for_add): Add new argument to ix86_lea_outperforms call. (ix86_use_lea_for_mov): Likewise. (ix86_avoid_lea_for_addr): Likewise. (ix86_lea_for_add_ok): Likewise. (exact_dependency_1): New function. (exact_store_load_dependency): Likewise. (ix86_adjust_cost): Handle Silvermont tuning. (do_reoder_for_imul): Likewise. (swap_top_of_ready_list): New function. (ix86_sched_reorder): Changed to handle Silvermont tuning. * config/i386/i386.md (peepholes that split memory operand in fp converts): New. Also backport r199611 with fixes for the patch above and previous SLM patch: 2013-06-03 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com> * config/i386/i386.c (ix86_lea_outperforms): Fix formatting. (ix86_avoid_lea_for_addr): Likewise. (exact_dependency_1): Likewise. (ix86_adjust_cost): Likewise. (swap_top_of_ready_list): Fix formatting and !reload_completed check removed. (do_reorder_for_imul): Fix typo, formatting and !reload_completed check removed. (ix86_sched_reorder): Fix typo and formatting. (fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types list. * config/i386/cpuinfo.c (INTEL_SLM): New enum value. Note that [4.7] part of the patch doesn't contain some of optimizations (IMUL) due to missed dependencies. [4.8] part of this backport is complete. Change-Id: I4b5f92b025aab217046f5b393527636f3cf25669 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* [4.7, 4.8] Release basic tuning for new Silvermont architecturePavel Chupin2013-05-306-26/+885
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support new switches: -march=slm/-mtune=slm This is backport of trunk r199444: 2013-05-30 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com> Igor Zamyatin <igor.zamyatin@intel.com> Silvermont (SLM) architecture pipeline model, tuning and insn selection. * config.gcc: Add slm config options and target. * config/i386/slm.md: New. * config/i386/driver-i386.c (host_detect_local_cpu): Check * movbe. * gcc/config/i386/i386-c.c (ix86_target_macros_internal): New * case PROCESSOR_SLM. (ix86_target_macros_internal): Likewise. * gcc/config/i386/i386.c (slm_cost): New cost. (m_SLM): New macro flag. (initial_ix86_tune_features): Set m_SLM. (x86_accumulate_outgoing_args): Likewise. (x86_arch_always_fancy_math_387): Likewise. (processor_target_table): Add slm cost. (cpu_names): Add slm cpu name. (x86_option_override_internal): Set SLM ISA. (ix86_issue_rate): New case PROCESSOR_SLM. (ia32_multipass_dfa_lookahead): Likewise. (fold_builtin_cpu): Add slm. * config/i386/i386.h (TARGET_SLM): New target macro. (target_cpu_default): Add TARGET_CPU_DEFAULT_slm. (processor_type): Add PROCESSOR_SLM. * config/i386/i386.md (cpu): Add new value "slm". (slm.md): Include slm.md. * libgcc/config/i386/cpuinfo.c (INTEL_SLM): New enum value. Change-Id: I3ad6f5584e3fd5de52ac608dc699daaad24f2fe4 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Remove hardcoded -m32 in compiler optionsPavel Chupin2013-05-221-1/+1
| | | | | | | | | | | | | It's required for x86_64 targets where we obviously don't want to enforce -m32. It shouldn't affect standard i686 targets because i686 is enforced on configure stage and it effectively removes 64-bit support, keeping -m32 default. Patch changes 4.7 and 4.8 only. x86_64 targets are not expected to be supported in older gcc versions due to many issues and dependencies. Change-Id: Id15a677a9d3b1712eb95aba92c2c5bd98f9ed1cc Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Fix ARM/GCC-4.7,4.8 generates insufficient alignment for NEON vst/vldAndrew Hsieh2013-05-151-2/+6
| | | | | | | | | | | | | | GCC allocates memory buffer and passes it as the first hidden argument for function return large composite type (ie. > 4 bytes for all NDK toolchain). Problem is that GCC doesn't observe the aligement required by the type, and ARM EABI only requires stack to be aligned to 8-byte. Please see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57271 for external bug tracking this issue and testcase. This CL offers temp relief before formal one Change-Id: I8004bc4208487e539ba8b0c9686c44ac86c37d83
* Add new GCC/MIPS option -mldc1-sdc1Andrew Hsieh2013-04-262-1/+5
| | | | | | | | ldc1/sdc1 needs memory to be 8-byte aligned. This option is on by default for arch supports it, but can be turned off by "-mno-ldc1-sdc1" to workaround issue, for example. Change-Id: I14291dc4280e75f6c765c933b60eb1b7cd44f974
* Update -mstack-protector-guard= support based on upstream commentsAndrew Hsieh2013-04-173-7/+8
| | | | | | See http://gcc.gnu.org/ml/gcc-patches/2013-04/msg00764.html Change-Id: I8aad144f579def5629fcb7cb29a68d057b809be2
* Misc fixesAndrew Hsieh2013-04-041-1/+1
| | | | | | | | | | 1. Fixed darwin build of GCC 4.8/X86 by removing trailing ',' from the last item of enum. Not discovered before because GCC 4.8 now builds with -Wall -Werror, and gcc-4.2.1 in darwin is picky about that 2. Fixed -fuse-ld=mcld Change-Id: I7b65edfb76841f14c3290acb5a98f556d00e1139
* [4.8] Fixed GCC 4.8 ICE gen_thumb_movhi_clobber at config/arm/arm.md:5832Andrew Hsieh2013-04-022-2/+3
| | | | | | | | | See issue https://code.google.com/p/android/issues/detail?id=52732, and fix http://gcc.gnu.org/ml/gcc-patches/2010-12/msg00732.html Also see 78a68e851a2f6f9d00367cd38eeedf670bb80f01 Change-Id: Iad4deda17414f3165714da0b60f9f8cb2a6ef052
* [4.8] Fix MIPS GCC to emit -m elf32ltsmip for linkerAndrew Hsieh2013-04-021-0/+1
| | | | | | | | | | | | ARM/X86 GCC in NDK explicitly emit -m armelf_linux_eabi and -m elf_i386, respectively, for linker. Fix MIPS to do the same, to help mclinker which is built vanilla and relies on either filename (eg. eg. arm-linux-androideabi-ld.mcd implies arm) or -mtriple/-march/-m to figure out the target See 125708b8e3afa6007ce3aa7132165d27b719ccc3 Change-Id: I79d67b5a69884713b9a3aaa59012c9170b823068
* [4.8] Use memalign instead of posix_memalign in GCC x86 mm_malloc.hAndrew Hsieh2013-04-021-0/+6
| | | | | | | | | | | | | | | | posix_memalign doesn't exist in NDK. Code inludes ?mmintrin.h which in turn includes mm_malloc.h may fail to link For AOSP platform build which uses the same compiler, add -DHAVE_POSIX_MEMALIGN to restore the original behavior. Other than non-zero return value which _mm_alloc already ignores, both paths are functioanlly identical (under the hood dlmalloc.c in 32-bit ensure alignment is at least 16-byte) See 0457b0db02c4b229eab11c01025df948032c31a7 Change-Id: I2e83d544a4ac2f4549de3b41a85e009a0a085476
* [4.8] Support OpenMPAndrew Hsieh2013-04-025-7/+12
| | | | | | | | | See b6e375800c9a2f02a732cbdf5e87a860c3d954e1, 1271761f530c0050154e8d526b95f952df551751, 92c478dba755a1a2f6f00ff390666acbffd41982 and 51df2e98d22e2c6f5d2a16860bc8fc3644179c1d. Change-Id: I7b01524a5516dd31b26a68cccc616a066893db39
* [4.8] Enable MIPS floating-point madd/msub/nmadd/nmsub/recip/rsqrt with ↵Iceberg Fu2013-04-022-9/+4
| | | | | | | | 32-bit FPU. See 7609f724df8ca390935f63243fa72e1de39d00c6 Change-Id: Id77b56a1cf886584020cf30a4211de0a87b4f56e
* [4.8] Enable armv7/thumb2 multilib for arm-eabi.Ben Cheng2013-04-021-12/+17
| | | | | | | | | | | | | Configured multilib: > arm-eabi-gcc -print-multi-lib .; thumb;@mthumb thumb/thumb2;@mthumb@march=armv7 See 978fb74a5c086cc5572dc2e3f37d207acad969d7 Change-Id: Ia04c9e23cb5abb924702639c6c0f3afc9c485ff0
* [4.8] Add -mstack-protector-guard= to x86 compilersAndrew Hsieh2013-04-024-4/+29
| | | | | | | | | | | | | | | | | | | | To choose between "global" (default) and "tls" (new) for -fstack-protector, -fstack-protector-all, and -fstack-protector-strong (GCC 4.6+). Note that this alone doesn't enable any -fstack-protector* For NDK: The default "global" generates code backward compatible with older bionic For AOSP: build may add "-mstack-protector-guard=tls" to build platform code with new bionic (*1) Related CL: ad88a0863110798cef5169dcf917e18b967a7cf6 (*1) e804643b6dfcfb5842dea4b714601c6dd89f4944 Change-Id: I341c9022530b37ca289d94e1174dfa86a8eaa1bf
* [4.8] Port MIPS Android support to GCC-4.8Andrew Hsieh2013-04-023-2/+6
| | | | | | | | | Used to be local NDK patch at $NDK/build/tools/toolchain-patches/ gcc/0008-Port-MIPS-Android-support-to-GCC-4.6.patch See ec1a2a51fa75883e4bdf9f4f03e8fd16a261c275 Change-Id: I7526fc1f1c3304c14b8f6f6d5a0b26ddc1c7e4a0
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