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* Fix host 64-bit gcc4.6 buildAndrew Hsieh2014-03-051-1/+1
| | | | | | | | | | | | | | ANDROID_CC1_SPEC should be used with argument, otherwise it's not expanded and fail compilation. Note that we are not building 64-bit 4.6 target toolchain. 64-bit target toolchains are built from 4.7 and up instead. This issue only occurs when building 64-bit host compiler (x86_64), eg. aosp/prebuilts/gcc/linux-x86/host. The argument doesn't matter, although we put "-fPIC" to be consistent with its 32-bit counterpart Change-Id: I746b14a6e4471a4bd62fb4e29b574669d4b7a9d1
* Merge "Define bionic aarch64 linker path."Andrew Hsieh2014-02-061-0/+1
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| * Define bionic aarch64 linker path.Ben Cheng2014-02-051-0/+1
| | | | | | | | Change-Id: Id343d7a1b74dea14cc0856cfc1e230a01db7c740
* | Merge "[4.8] Add -mlong-double-128 and make it default for 64-bit Bionic"Andrew Hsieh2014-02-0631-10/+232
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| * [4.8] Add -mlong-double-128 and make it default for 64-bit BionicPavel Chupin2014-02-0531-10/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport of r207428: 2014-02-03 H.J. Lu <hongjiu.lu@intel.com> gcc/ * config/i386/i386.c (flag_opts): Add -mlong-double-128. (ix86_option_override_internal): Default long double to 64-bit for 32-bit Bionic and to 128-bit for 64-bit Bionic. * config/i386/i386.h (LONG_DOUBLE_TYPE_SIZE): Use 128 if TARGET_LONG_DOUBLE_128 is true. (LIBGCC2_LONG_DOUBLE_TYPE_SIZE): Likewise. * config/i386/i386.opt (mlong-double-80): Negate -mlong-double-64. (mlong-double-64): Negate -mlong-double-128. (mlong-double-128): New option. * config/i386/i386-c.c (ix86_target_macros): Define __LONG_DOUBLE_128__ for TARGET_LONG_DOUBLE_128. * doc/invoke.texi: Document -mlong-double-128. gcc/testsuite/ * gcc.target/i386/long-double-64-1.c: Verify __multf3 isn't used. * gcc.target/i386/long-double-64-4.c: Likewise. * gcc.target/i386/long-double-80-1.c: Likewise. * gcc.target/i386/long-double-80-2.c: Likewise. * gcc.target/i386/long-double-80-3.c: Likewise. * gcc.target/i386/long-double-80-4.c: Likewise. * gcc.target/i386/long-double-80-5.c: Likewise. * gcc.target/i386/long-double-64-2.c: Limit to ia32. Verify __multf3 isn't used. * gcc.target/i386/long-double-64-3.c: Likewise. * gcc.target/i386/long-double-128-1.c: New test. * gcc.target/i386/long-double-128-2.c: Likewise. * gcc.target/i386/long-double-128-3.c: Likewise. * gcc.target/i386/long-double-128-4.c: Likewise. * gcc.target/i386/long-double-128-5.c: Likewise. * gcc.target/i386/long-double-128-6.c: Likewise. * gcc.target/i386/long-double-128-7.c: Likewise. * gcc.target/i386/long-double-128-8.c: Likewise. * gcc.target/i386/long-double-128-9.c: Likewise. * gcc.target/i386/long-double-64-5.c: Likewise. * gcc.target/i386/long-double-64-6.c: Likewise. * gcc.target/i386/long-double-64-7.c: Likewise. * gcc.target/i386/long-double-64-8.c: Likewise. * gcc.target/i386/long-double-64-9.c: Likewise. * gcc.target/i386/long-double-80-10.c: Likewise. * gcc.target/i386/long-double-80-8.c: Likewise. * gcc.target/i386/long-double-80-9.c: Likewise. Change-Id: I2e1ce44792dd78df521fa485f2c0d2303dbb83bd Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* | Merge "Fix aarch64 to use Android specs."Ben Cheng2014-02-051-0/+21
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| * | Fix aarch64 to use Android specs.Ben Cheng2014-02-041-0/+21
| |/ | | | | | | | | | | | | | | | | | | | | Flags include: - CC1_SPEC - CC1PLUS_SPEC - LIB_SPEC - STARTFILE_SPEC - ENDFILE_SPEC Change-Id: Ia96ca57ade849c964c91f5390e6c9cded16a9bf4
* / [4.7, 4.8] Backport of two patches for additional SLM-tuning.Alexander Ivchenko2014-01-302-3/+3
|/ | | | | | | | | | | | | | | | | | | We don't have config/i386/x86-tune.def in 4.8, instead initial_ix86_tune_features is modified. This one is for 4.8 only. 2013-09-12 Yuri Rumyantsev <ysrumyan@gmail.com> * config/i386/x86-tune.def: Turn on X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE for SLM. Update HImode imul cost for Silvermont 2013-12-13 Yuri Rumyantsev <ysrumyan@gmail.com> * config/i386/i386.c (slm_cost): Fix imul cost for HI. Change-Id: I3e6e7b157897e93bc3874738635db4ecf4e7f587 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* [4.6, 4.8] Add additional multilib option: mfloat-abi=hardAndrew Hsieh2013-12-263-7/+9
| | | | | | | | | | | | Only available with "-march=armv7-a", this CL add two set of libraries 1. "armv7-a/hard": -march=armv7-a -mfloat-abi=hard 2. "armv7-a/thumb/hard": -march=armv7-a -mthumb -mfloat-abi=hard Note that -mhard-float implies -mfloat-abi=hard, which in turns select one of the above /hard libraries dependeing on the presence of -mthumb or not. (ie. no need to explicitly specifly -mfloat-abi=hard after -mhard-float) Change-Id: Ib803ecaa911082d6bc4f98b542d7d28e98be6726
* Merge "[4.8] backport fix for partial specialization of template"Andrew Hsieh2013-12-264-22/+52
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| * [4.8] backport fix for partial specialization of templateAndrew Hsieh2013-12-104-22/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | 2013-12-05 Jason Merrill <jason@redhat.com> PR c++/59044 PR c++/59052 * pt.c (most_specialized_class): Use the partially instantiated template for deduction. Drop the TMPL parameter. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=59052 Change-Id: I4760e719def2f5eacac438af2df0b18c1f2d16a8
* | Add built-in macro __ANDROID__ for aarch64-linux-android-gccBen Cheng2013-12-121-0/+1
|/ | | | | | | | | | | | | | | | | This is to match the existing behavior of 32-bit toolchains. For example in gcc/config/arm/linux-eabi.h it has the following: do { TARGET_BPABI_CPP_BUILTINS(); GNU_USER_TARGET_OS_CPP_BUILTINS(); ANDROID_TARGET_OS_CPP_BUILTINS(); } while (false) I'll try to upstream this patch. Change-Id: I22aa6ba5a0d7b5c9cd5a314f7079dc1edd2d382c
* [4.6, 4.8] Add -mtune=intel supportPavel Chupin2013-12-098-14/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is backport of r205719 and r205754 from trunk. Now -mtune=intel matches -mtune=slm for 4.8 and -mtune=atom for 4.6. As written in gcc-4.8 docs: Produce code optimized for the most current Intel processors, which are Haswell and Silvermont for this version of GCC. If you know the CPU on which your code will run, then you should use the corresponding -mtune or -march option instead of -mtune=intel. But, if you want your application performs better on both Haswell and Silvermont, then you should use this option. As new Intel processors are deployed in the marketplace, the behavior of this option will change. Therefore, if you upgrade to a newer version of GCC, code generation controlled by this option will change to reflect the most current Intel processors at the time that version of GCC is released. There is no -march=intel option because -march indicates the instruction set the compiler can use, and there is no common instruction set applicable to all processors. In contrast, -mtune indicates the processor (or, in this case, collection of processors) for which the code is optimized. Change-Id: I3ec4c3b5423d9b3547cd8e3aa77a18af3fd89598 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* [4.8] fix for GCC 4.8.2 libstdc++ bug in std::nth_elementDavid Turner2013-12-033-2/+63
| | | | | | | | | | | | | | | | | Backport fix for a GCC 4.8 libstdc++ issue where the generated code random segfault on std::nth_element See https://code.google.com/p/android/issues/detail?id=62910 2013-10-20 Chris Jefferson <chris@bubblescope.net> Paolo Carlini <paolo.carlini@oracle.com> PR libstdc++/58800 * include/bits/stl_algo.h (__unguarded_partition_pivot): Change __last - 2 to __last - 1. * testsuite/25_algorithms/nth_element/58800.cc: New Change-Id: I76f86bb7162a6bbc340dac84f54c16a97f9f18fc
* Remove *.orig; update libgo testdataAndrew Hsieh2013-12-0314-156732/+0
| | | | | | | 1. *.orig files are artifact after patch 2. restore 3 testdata which were reset to zero-byte in last rebase Change-Id: I32e80c33349249cb11397b57698c2a241793652c
* Merge "[4.8] Merge GCC 4.8.2"Andrew Hsieh2013-12-031137-146946/+212170
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| * [4.8] Merge GCC 4.8.2synergydev2013-10-171137-146946/+212170
| | | | | | | | Change-Id: I0f1fcf69c5076d8534c5c45562745e1a37adb197
* | Merge "Fix GCC 4.8 ICE in cc1/cc1plus with -fuse-ld=mcld"Andrew Hsieh2013-11-121-0/+1
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| * | Fix GCC 4.8 ICE in cc1/cc1plus with -fuse-ld=mcldAndrew Hsieh2013-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Error message reads: cc1: internal compiler error: in common_handle_option, at opts.c:1774 Change-Id: I9a6e42811f0ec83d3a6c05a8bb9b1ec0e5a7144a
* | | [4.6] Backport of two patches for fixing build with texinfo-5.0.Alexander Ivchenko2013-11-116-20/+20
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2013-03-20 Jack Howarth <howarth@bromo.med.uc.edu> PR bootstrap/56258 * doc/generic.texi (POINTER_PLUS_EXPR): Use @item instead of @itemx. (PLUS_EXPR): Likewise. * doc/cppopts.texi (--help): Likewise. * doc/invoke.texi (-fenable-@var{kind}-@var{pass}): Likewise (-fdump-rtl-cprop_hardreg): Likewise. (-fdump-rtl-csa): Likewise. (-fdump-rtl-dce): Likewise. (-fdump-rtl-dbr): Likewise. (-fdump-rtl-into_cfglayout): Likewise. (-fdump-rtl-outof_cfglayout): Likewise. (@gccoptlist): Move misplaced bracket. 2013-02-21 Jakub Jelinek <jakub@redhat.com> PR bootstrap/56258 * doc/invoke.texi (-fdump-rtl-pro_and_epilogue): Use @item instead of @itemx. 2013-02-21 Jakub Jelinek <jakub@redhat.com> PR bootstrap/56258 * gnat-style.texi (@title): Remove @hfill. * projects.texi: Avoid line wrapping inside of @pxref or @xref. 2013-02-21 Jakub Jelinek <jakub@redhat.com> PR bootstrap/56258 * doc/cp-tools.texinfo (Virtual Machine Options): Use just one @gccoptlist instead of 3 separate ones. Change-Id: Ib38dac55a3a3517a2f98588d93b5301368299b68 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* | Merge "[4.8] Backport revision 204203 to fix 3.4 kernel compilation."Ben Cheng2013-10-302-0/+6
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| * | [4.8] Backport revision 204203 to fix 3.4 kernel compilation.Ben Cheng2013-10-302-0/+6
| |/ | | | | | | | | | | | | | | | | | | 2013-10-30 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> PR target/58854 * config/arm/arm.c (arm_expand_epilogue_apcs_frame): Emit * blockage. Change-Id: I6edddcf212f4185ab55a3a17bc7a80b1ab6b64b7
* / Backport fix to set mips_dbx_regno entries to IGNORED_DWARF_REGNUM by defaultSteve Ellcey2013-10-255-8/+48
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2012-12-12 Steve Ellcey <sellcey@mips.com> * config/mips/mips.c (mips_option_override): Set mips_dbx_regno entries to IGNORED_DWARF_REGNUM by default. 2012-12-10 Steve Ellcey <sellcey@mips.com> PR target/54061 rtl.h (IGNORED_DWARF_REGNUM): New. * dwarf2out.c (reg_loc_descriptor): Check for IGNORED_DWARF_REGNUM. (mem_loc_descriptor): Ditto. * config/mips/mips.h (ALL_COP_REG_FIRST): New. (ALL_COP_REG_LAST): New. (ALL_COP_REG_NUM): Redefine using above macros. * config/mips/mips.c (mips_option_override): Set mips_dbx_regno coprocessor entries to IGNORED_DWARF_REGNUM. Error reads: target C++: libicui18n <= external/icu4c/i18n/olsontz.cpp external/icu4c/i18n/decimfmt.cpp: In member function 'virtual icu_50::UnicodeString& icu_50::DecimalFormat::format(const icu_50::StringPiece&, icu_50::UnicodeString&, icu_50::FieldPositionIterator*, UErrorCode&) const': external/icu4c/i18n/decimfmt.cpp:1322:1: internal compiler error: in dbx_reg_number, at dwarf2out.c:10185 See http://gcc.gnu.org/ml/gcc-patches/2012-12/msg00830.html Change-Id: I84110b5b54d8d9262043811eddb0edc1c42303f8
* Fix mips64 to use ABI_64 by defaultIceberg Fu2013-10-141-1/+9
| | | | Change-Id: Icb9e62372db5f4639012becdbc3968d4bddf139a
* Extend MIPS GCC4.6/4.7/4.8 -mldc1-sdc1 to control ldxc1/sdxc1 tooIceberg Fu2013-08-306-9/+9
| | | | | | | | | | | | | -mldc1-sdc1 now also controls codegen of ldxc1/sdxc1, the indexed versions (where address of load/store is computed from sum of two registers) of ldc1/sdc1 which are already controlled by this option. Although double (or struct containing double) is always aligned and the stock does guarantee 8-byte alignment, this option is to workaround issue when double is allocated from a custom allocator w/o honoring 8-byte minimal alignment. Change-Id: I79433976509b885b5699d62693fd3154bb752abf
* [4.8] Backport additional diagnostic supportsynergydev2013-08-2614-255/+360
| | | | | | | Squashed commit of r198331, r198900, r201467, and r201574 from trunk. Change-Id: If0d68971ffac2e7bc48576e2453d799a446f7415
* [4.8] Fix ICE when building bullet library.Alexander Ivchenko2013-08-173-5/+41
| | | | | | | | | | | | | | | | | | See b.android.com/58916 for initial issue and http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58165 for bug discussion. Backport the fix in r201780 2013-08-16 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/58165 * tree-call-cdce.c (shrink_wrap_one_built_in_call): If bi_call must be the last stmt in a bb, don't split_block, instead use fallthru edge from it and give up if there is none. Release conds vector when returning early. Change-Id: Iaaa90005e279c718a3f398b72579c13cec901246 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Add MXU support in gcc4.6/4.7/4.8 with -mmxuAndrew Hsieh2013-08-156-0/+15
| | | | | | For Ingenic MXU. Change-Id: Ie7b465c971e3642b3244ac1a77b6f86be4ab4fea
* Merge "[4.8] Backport diagnostic color support from trunk"Ben Cheng2013-08-0919-64/+679
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| * [4.8] Backport diagnostic color support from trunksynergydev2013-08-0819-64/+679
| | | | | | | | | | | | | | | | | | | | Squashed commit of r197841, r197842, and r198332 from trunk. This is capable of coloring errors, warnings, notes, carets, locus', and/or quotes. Documentation for this feature may be found here: http://gcc.gnu.org/onlinedocs/gcc/Language-Independent-Options.html Change-Id: I14f2f852562d18fcef807583635e4e2ceee64829
* | Merge "[4.6,4.7] Always enable --eh-frame-hdr for static executable"Andrew Hsieh2013-08-0719-8/+240
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| * | [4.6,4.7] Always enable --eh-frame-hdr for static executableAndrew Hsieh2013-08-0719-8/+240
| |/ | | | | | | | | | | | | See 23e3137ee2897464b051599b85a09f130d3ad05d for the reason why. backport 4.8 patch from http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00969.html Change-Id: I9496e11f314e5e2ec9359b993016723ab6366dad
* | Merge "[4.8] Always enable --eh-frame-hdr for static executable"Andrew Hsieh2013-08-0711-5/+128
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| * | [4.8] Always enable --eh-frame-hdr for static executableH.J. Lu2013-08-0711-5/+128
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See 23e3137ee2897464b051599b85a09f130d3ad05d for the reason why Port patch from http://gcc.gnu.org/ml/gcc-patches/2012-09/msg00969.html gcc/ 2012-09-14 H.J. Lu <hongjiu.lu@intel.com> PR debug/54568 * configure.ac: Add --enable-eh-frame-hdr-for-static. Set USE_EH_FRAME_HDR_FOR_STATIC if PT_GNU_EH_FRAME is supported for static executable. * config.in: Regenerated. * configure: Likewise. * config/gnu-user.h (LINK_EH_SPEC): Defined as "--eh-frame-hdr " if USE_EH_FRAME_HDR_FOR_STATIC is defined. * config/sol2.h (LINK_EH_SPEC): Likewise. * config/openbsd.h (LINK_EH_SPEC): Likewise. * config/alpha/elf.h (LINK_EH_SPEC): Likewise. * config/freebsd.h (LINK_EH_SPEC): Likewise. * config/rs6000/sysv4.h (LINK_EH_SPEC): Likewise. gcc/testsuite/ 2012-09-13 H.J. Lu <hongjiu.lu@intel.com> PR debug/54568 * g++.dg/eh/spec3-static.C: New test. libgcc/ 2012-09-14 H.J. Lu <hongjiu.lu@intel.com> PR debug/54568 * crtstuff.c (USE_PT_GNU_EH_FRAME): Check CRTSTUFFT_O together with USE_EH_FRAME_HDR_FOR_STATIC. Change-Id: If442d27eeb1347ac5a1b943acbbeff5f708a9929
* / [4.8] Simplify GCC 4.8 BASE-VERAndrew Hsieh2013-08-072-2/+2
|/ | | | | | | | | Change 4.8.1 -> 4.8 to simplify and shield NDK make-standalone-toolchain.sh from gcc minor version upgrade Also correct a comment based on upstream Change-Id: I95791e24937d02fffa6e116761d834705020c911
* Merge "Add an internal switch -minline-thumb1-jumptable to ARM gcc4.6/4.7/4.8"Andrew Hsieh2013-08-0712-9/+27
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| * Add an internal switch -minline-thumb1-jumptable to ARM gcc4.6/4.7/4.8Lai Wei-Chih2013-08-0212-9/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Default is off (ie. no changes of behavior), meaning that gcc may generate thumb1 jumptable helper calls (eg. __gnu_thumb1_case_sqi) for switch/case. Use -minline-thumb1-jumptable to compile code which can be linked with compiler-rt where helper __gnu_thumb1_case_* doesn't exist. This is mainly for use to compile NDK gabi++/stlport/libc++ to be independent of libgcc.a. The only affected binaries are all in armeabi. ABIs armeabi-v7a and x86/mips aren't affected. Size differences are libgabi++_static.a 176286 -> 176538 +0.1% libstlport_static.a 1406346 -> 1413318 +0.5% libc++_static.a 2426814 -> 2439074 +0.5% Change-Id: I582898955b28e53e988a91bc1a64b76fba677e58
* | [4.8] Merge GCC 4.8.1Ben Cheng2013-08-05562-17897/+25238
| | | | | | | | Change-Id: Ic8a60b7563f5172440fd40788605163a0cca6e30
* | [4.6,4.8] Add stack unwinding directives for __aeabi_idiv0 in libgcc.aAndrew Hsieh2013-08-034-1/+16
| | | | | | | | | | | | Same fix to 4.7 in 5ea1e88a7f14a78a01d95f66e388eb15908a5225 Change-Id: I1b2ce4ad72e6b2a327183703d9e49295cf2bad25
* | [4.7] Add stack unwinding directives for __aeabi_idiv0 in libgcc.aBen Cheng2013-08-012-0/+8
|/ | | | Change-Id: I32b4178ec6f09c08c5ecf70aabf7532e03774766
* [4.8] Fix ICE on g++.dg/cpp0x/lambda/lambda-defarg3.C.Alexander Ivchenko2013-07-301-6/+8
| | | | | | | | | | | | Backport the fix in r201317 2013-07-29 Jason Merrill <jason@redhat.com> * mangle.c (write_name): Check for null context. (write_unscoped_name): Allow PARM_DECL context. Change-Id: I4f1e9c2ddc01766818562648b6e905ef33c0de50 Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Fix gcc4.6 thumb2 fails to generate 16bit relative jump tableAndrew Hsieh2013-07-241-1/+1
| | | | | | | | | 2011-08-12 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> PR target/48328 * config/arm/arm.h (CASE_VECTOR_SHORTEN_MODE): Fix distance for tbh instructions. Change-Id: Ic269b2a12c727059714ef7653bc63eaccfd74f90
* Fix GCC 4.6 ARM broken -Os on boost 1.52.0Andrew Hsieh2013-06-212-4/+13
| | | | | | | | | | | | | | | | | See b.andriod.com/42891 Back port r190971 2012-09-05 Bin Cheng <bin.cheng@arm.com> Backport from 2012-09-04 mainline r190919 PR target/45070 * config/arm/arm.c (thumb1_extra_regs_pushed): Handle return value of size less than 4 bytes by using macro ARM_NUM_INTS. (thumb1_unexpanded_epilogue): Use macro ARM_NUM_INTS. Change-Id: Ib43bc77abae8d487e82802c8c1f1cce87d5a7e5e
* Fix segfault on const init to object addressAndrew Hsieh2013-06-203-2/+56
| | | | | | | | | | | | | | | See b.android.com/56508 and http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54986 Backport the fix in r193189 2012-11-05 Eric Botcazou <ebotcazou@adacore.com> PR tree-optimization/54986 * gimple-fold.c (canonicalize_constructor_val): Strip again all no-op conversions on entry but add them back on exit if needed. Change-Id: Ibedd829e7780ff78e7b90219ebb7c425f7d2fc01
* [4.7, 4.8] Extended Silvermont tuning.Pavel Chupin2013-06-047-85/+474
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Backport r199546 from trunk: 2013-05-31 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com> Igor Zamyatin <igor.zamyatin@intel.com> Silvermont (SLM) architecture performance tuning. * config/i386/i386.h (enum ix86_tune_indices): Add X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS. (TARGET_SPLIT_MEM_OPND_FOR_FP_CONVERTS): New define. * config/i386/i386.c (initial_ix86_tune_features) <X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS>: Initialize. (ix86_lea_outperforms): Handle Silvermont tuning. (ix86_avoid_lea_for_add): Add new argument to ix86_lea_outperforms call. (ix86_use_lea_for_mov): Likewise. (ix86_avoid_lea_for_addr): Likewise. (ix86_lea_for_add_ok): Likewise. (exact_dependency_1): New function. (exact_store_load_dependency): Likewise. (ix86_adjust_cost): Handle Silvermont tuning. (do_reoder_for_imul): Likewise. (swap_top_of_ready_list): New function. (ix86_sched_reorder): Changed to handle Silvermont tuning. * config/i386/i386.md (peepholes that split memory operand in fp converts): New. Also backport r199611 with fixes for the patch above and previous SLM patch: 2013-06-03 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com> * config/i386/i386.c (ix86_lea_outperforms): Fix formatting. (ix86_avoid_lea_for_addr): Likewise. (exact_dependency_1): Likewise. (ix86_adjust_cost): Likewise. (swap_top_of_ready_list): Fix formatting and !reload_completed check removed. (do_reorder_for_imul): Fix typo, formatting and !reload_completed check removed. (ix86_sched_reorder): Fix typo and formatting. (fold_builtin_cpu): Move M_INTEL_SLM at the end of processor types list. * config/i386/cpuinfo.c (INTEL_SLM): New enum value. Note that [4.7] part of the patch doesn't contain some of optimizations (IMUL) due to missed dependencies. [4.8] part of this backport is complete. Change-Id: I4b5f92b025aab217046f5b393527636f3cf25669 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* [4.7, 4.8] Release basic tuning for new Silvermont architecturePavel Chupin2013-05-3015-65/+1797
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support new switches: -march=slm/-mtune=slm This is backport of trunk r199444: 2013-05-30 Yuri Rumyantsev <yuri.s.rumyantsev@intel.com> Igor Zamyatin <igor.zamyatin@intel.com> Silvermont (SLM) architecture pipeline model, tuning and insn selection. * config.gcc: Add slm config options and target. * config/i386/slm.md: New. * config/i386/driver-i386.c (host_detect_local_cpu): Check * movbe. * gcc/config/i386/i386-c.c (ix86_target_macros_internal): New * case PROCESSOR_SLM. (ix86_target_macros_internal): Likewise. * gcc/config/i386/i386.c (slm_cost): New cost. (m_SLM): New macro flag. (initial_ix86_tune_features): Set m_SLM. (x86_accumulate_outgoing_args): Likewise. (x86_arch_always_fancy_math_387): Likewise. (processor_target_table): Add slm cost. (cpu_names): Add slm cpu name. (x86_option_override_internal): Set SLM ISA. (ix86_issue_rate): New case PROCESSOR_SLM. (ia32_multipass_dfa_lookahead): Likewise. (fold_builtin_cpu): Add slm. * config/i386/i386.h (TARGET_SLM): New target macro. (target_cpu_default): Add TARGET_CPU_DEFAULT_slm. (processor_type): Add PROCESSOR_SLM. * config/i386/i386.md (cpu): Add new value "slm". (slm.md): Include slm.md. * libgcc/config/i386/cpuinfo.c (INTEL_SLM): New enum value. Change-Id: I3ad6f5584e3fd5de52ac608dc699daaad24f2fe4 Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* [4.4.3] Backport of the patch from trunk/4.8 for fixing issue 54623Andrew Hsieh2013-05-272-0/+11
| | | | | | | | | | | | | 2013-05-24 Alexander Ivchenko <alexander.ivchenko@intel.com> PR tree-ssa/57385 * tree-ssa-sccvn.c (fully_constant_vn_reference_p): Check that index is not negative. See f63aa0156b8ef6b30304890529cbf642e8f78ebd and https://code.google.com/p/android/issues/detail?id=54623 Change-Id: I3dbba928565414575b9438bb1467fec21506fbc8
* [4.6], [4.7], [4.8] Backport of the patch from trunk/4.8 for fixingAlexander Ivchenko2013-05-246-0/+33
| | | | | | | | | | | | | | this issue: https://code.google.com/p/android/issues/detail?id=54623 2013-05-24 Alexander Ivchenko <alexander.ivchenko@intel.com> PR tree-ssa/57385 * tree-ssa-sccvn.c (fully_constant_vn_reference_p): Check that index is not negative. Change-Id: I8c83a3f9992b60d3f59c2b8e123ecda7c398d07e Signed-off-by: Alexander Ivchenko <alexander.ivchenko@intel.com>
* Remove hardcoded -m32 in compiler optionsPavel Chupin2013-05-222-2/+2
| | | | | | | | | | | | | It's required for x86_64 targets where we obviously don't want to enforce -m32. It shouldn't affect standard i686 targets because i686 is enforced on configure stage and it effectively removes 64-bit support, keeping -m32 default. Patch changes 4.7 and 4.8 only. x86_64 targets are not expected to be supported in older gcc versions due to many issues and dependencies. Change-Id: Id15a677a9d3b1712eb95aba92c2c5bd98f9ed1cc Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
* Fix ARM/GCC-4.7,4.8 generates insufficient alignment for NEON vst/vldAndrew Hsieh2013-05-152-4/+12
| | | | | | | | | | | | | | GCC allocates memory buffer and passes it as the first hidden argument for function return large composite type (ie. > 4 bytes for all NDK toolchain). Problem is that GCC doesn't observe the aligement required by the type, and ARM EABI only requires stack to be aligned to 8-byte. Please see http://gcc.gnu.org/bugzilla/show_bug.cgi?id=57271 for external bug tracking this issue and testcase. This CL offers temp relief before formal one Change-Id: I8004bc4208487e539ba8b0c9686c44ac86c37d83
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